CN102104099B - Method for manufacturing high-brightness light emitting diode chip - Google Patents

Method for manufacturing high-brightness light emitting diode chip Download PDF

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Publication number
CN102104099B
CN102104099B CN2009102019567A CN200910201956A CN102104099B CN 102104099 B CN102104099 B CN 102104099B CN 2009102019567 A CN2009102019567 A CN 2009102019567A CN 200910201956 A CN200910201956 A CN 200910201956A CN 102104099 B CN102104099 B CN 102104099B
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electrode
layer
nitride semiconductor
vapor deposition
semiconductor layer
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CN102104099A (en
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陈诚
郝茂盛
李士涛
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Irico Group Corp
Shanghai Blue Light Technology Co Ltd
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Irico Group Corp
Shanghai Blue Light Technology Co Ltd
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Abstract

The invention discloses a method for manufacturing a high-brightness light emitting diode chip. The method comprises the following steps: 1, preparing a semiconductor epitaxial layer on a substrate, wherein the semiconductor epitaxial layer at least comprises an N-type nitride semiconductor layer, an active layer and a P-type nitride semiconductor layer; 2, locally etching to ensure that partial N-type nitride semiconductor layer is exposed, and forming an N-type roundabout barrier layer which is lower than a preserved N electrode evaporation position for a certain height difference, wherein the exposed part of the N-type nitride semiconductor layer comprises the N-type roundabout barrier layer, the preserved N electrode evaporation position and the preserved barrier layer position, and the preserved barrier layer position is positioned on a P electrode evaporation position, and is wider than the P electrode; 3, depositing the barrier layer on the preserved barrier layer position; 4, forming a transparent conductive layer on the P-type nitride semiconductor layer; 5, evaporating an N electrode and a P electrode on the N-type nitride semiconductor layer and the P-type nitride semiconductor layer respectively; and 6, depositing a protective film on the chip. By using the method, the problem of current diffusion and improve the antistatic capability of the chip can be solved.

Description

The manufacturing approach of high-brightness LED chip
Technical field
The present invention relates to a kind of method of manufacturing technology of light-emitting diode chip for backlight unit, relate in particular to a kind of manufacturing approach of high-brightness LED chip.
Background technology
Existing LED chip construction is as depicted in figs. 1 and 2, is the shortest zone passage of distance because electric current can be assembled from the resistance minimum, the truncation surface place that promptly elliptic region indicates in Fig. 1.Electric current when the P electrode, can preferentially be selected the nearest fringe region in corner from the N electrode stream, makes that the effect of electric current diffusion is relatively poor, big electric current through the time can produce bad some situation as shown in Figure 3.
The manufacturing of existing light-emitting diode chip for backlight unit mainly comprises following 4 basic steps, sees Fig. 1 and Fig. 2:
1. on nonconducting substrate, prepare semiconductor epitaxial layers, comprise n type nitride semiconductor layer 11 at least, be positioned at the active layer 12 on the n type nitride semiconductor layer 11 and be positioned at the P type nitride semiconductor layer 13 on the active layer 12;
2. vapor deposition transparency conducting layer 15 on P type nitride semiconductor layer 13, and with photoetching and lithographic technique the position in preparatory vapor deposition N electrode, P electrode and aisle is reserved;
3. utilize electron beam evaporation plating technology vapor deposition N electrode 17 and P electrode 16;
4. utilize plasma chemical vapor deposition technique to deposit diaphragm, and reserve the solder joint part of N electrode and P electrode at chip surface.
The problem that prior art exists:
1. electric current causes the electric current diffusivity poor in N/P layer intersection charge concentration;
2. the antistatic effect of chip is poor, and the antistatic effect of chip is an importance weighing quality, particularly is applied to outdoor screen products.
Summary of the invention
Technical problem to be solved by this invention provides a kind of manufacturing approach of high-brightness LED chip, to solve the antistatic effect of electric current diffusion problem and lifting chip.
For solving the problems of the technologies described above, the present invention provides a kind of manufacturing approach of high-brightness LED chip, comprises the steps:
The first step prepares semiconductor epitaxial layers on nonconducting substrate, comprise n type nitride semiconductor layer at least, be positioned at the active layer on the n type nitride semiconductor layer and be positioned at the P type nitride semiconductor layer on the active layer;
Second step; Utilize photoetching and lithographic technique to carry out local etching; The part n type nitride semiconductor layer is exposed; Exposed portions serve is N type rotary island barrier layer, reserves N electrode vapor deposition position and reserve the position, barrier layer, and forms N type rotary island barrier layer and be lower than that to reserve N electrode vapor deposition position certain height poor, and this position, reservation barrier layer is positioned at P electrode vapor deposition position and wideer slightly than P electrode;
In the 3rd step, utilize plasma chemical vapor deposition technique reserving position, barrier layer deposited barrier layer;
The 4th step, utilize coating technique vapor deposition layer of transparent conductive layer on P type nitride semiconductor layer, and increase N electrode amplification line simultaneously herein, this N electrode amplification line can be a transparency conducting layer N electrode amplification line, also can be metal conducting layer N electrode amplification line;
The 5th step; Utilize photoetching and evaporation coating technique difference vapor deposition N electrode and P electrode on n type nitride semiconductor layer and P type nitride semiconductor layer; And the while increases N electrode amplification line herein; This N electrode amplification line can be a transparency conducting layer N electrode amplification line, also can be metal conducting layer N electrode amplification line;
The 6th step, utilize plasma chemical vapor deposition technique to deposit diaphragm at chip surface, only expose the solder joint part of N electrode and P electrode.
Between going on foot, the first step and second also comprises the steps: to utilize the preparatory vapor deposition N electrode position deposition diaphragm of plasma chemical vapor deposition technique at semiconductor layer.Said diaphragm is silicon dioxide or silicon nitride.The thickness of said diaphragm is
Figure G2009102019567D00031
Second step can specifically be divided into for two steps: steps A, and utilize photoetching and lithographic technique to carry out local etching, part n type gallium nitride layer is exposed, here for reserving N electrode vapor deposition position; Step B utilizes photoetching and lithographic technique to carry out local etching, and part n type gallium nitride layer is exposed, and is N type rotary island barrier layer here.Step A position reserved for the N-electrode deposition depth
Figure G2009102019567D00032
Step B N-type island barrier layer depth
N type rotary island barrier layer described in second step is lower than reserves N electrode vapor deposition position certain height difference for
Figure G2009102019567D00034
The diameter on barrier layer is 100um (micron)-120um described in the 3rd step, and the degree of depth is
Figure G2009102019567D00035
The thickness of transparency conducting layer is
Figure G2009102019567D00036
described in the 4th step
Preferably, in the 4th step, said N electrode amplification line is a transparency conducting layer N electrode amplification line; In the 5th step, said N electrode amplification line is a metal conducting layer N electrode amplification line.
Diaphragm is silicon dioxide or silicon nitride described in the 6th step, and the thickness of this diaphragm is
Figure G2009102019567D00037
Compare with prior art, the present invention has following beneficial effect: after the present invention adopted catch ring (N type rotary island barrier layer), electric current planar diffusion better effects if can not concentrate on the corner vertical proliferation.Electric charge is assembled in the bottom of catch ring, and is not to assemble at P layer or quantum well layer, helps promoting antistatic effect.
Description of drawings
Fig. 1 is the profile of existing light-emitting diode chip for backlight unit;
Fig. 2 is the front elevation of existing light-emitting diode chip for backlight unit;
Fig. 3 bad some situation sketch map that to be existing light-emitting diode chip for backlight unit can produce during to the P electrode from the N electrode stream at big electric current;
Fig. 4 is the profile after step 1 of the present invention is accomplished;
Fig. 5 is the vertical view after step 1 of the present invention is accomplished;
Fig. 6 is the profile after step 2 of the present invention is accomplished;
Fig. 7 is the vertical view after step 2 of the present invention is accomplished;
Fig. 8 is the profile after step 3 of the present invention is accomplished;
Fig. 9 is the vertical view after step 3 of the present invention is accomplished;
Figure 10 is the profile after step 4 of the present invention is accomplished;
Figure 11 is the vertical view after step 4 of the present invention is accomplished;
Figure 12 is the profile after step 5 of the present invention is accomplished;
Figure 13 is the vertical view after step 5 of the present invention is accomplished;
Figure 14 is the profile after step 6 of the present invention is accomplished.
Among Fig. 1 and Fig. 2, the 11st, n type nitride semiconductor layer, the 12nd, active layer, the 13rd, P type nitride semiconductor layer, the 15th, transparency conducting layer, the 16th, P electrode, the 17th, N electrode.
Among Fig. 4-Figure 14, the 1st, n type nitride semiconductor layer, the 2nd, active layer (being quantum well layer or luminous zone), the 3rd, P type nitride semiconductor layer; The 4th, N type rotary island barrier layer, the 5th, transparency conducting layer, the 6th, P electrode; The 7th, N electrode, the 8th, diaphragm, the 9th, barrier layer; 9 ' is to reserve the position, barrier layer, and 10 is transparency conducting layer N electrode amplification line, and 11 is metal conducting layer N electrode amplification line.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation.
Embodiment one:
The manufacturing approach of a kind of high-brightness LED chip of the present invention specifically comprises the steps:
Step 1; Utilize the organic metal gas phase deposition technology on nonconducting substrate, to grow semiconductor epitaxial layers; This semiconductor epitaxial layers comprises n type nitride semiconductor layer 1 at least; Be positioned at the active layer 2 on the n type nitride semiconductor layer 1 and be positioned at the P type nitride semiconductor layer 3 on the active layer 2, see Fig. 4 and Fig. 5.
Step 2; Utilize photoetching and lithographic technique to carry out local etching; Part n type nitride semiconductor layer 1 is exposed; Here for reserving N electrode vapor deposition position; The degree of depth is
Figure G2009102019567D00051
then; Utilize photoetching and lithographic technique to carry out local etching; Part n type nitride semiconductor layer 1 is exposed; Be N type rotary island barrier layer 4, the degree of depth finally forms N type rotary island barrier layer 4 and is lower than the difference in height of reserving about N electrode vapor deposition position
Figure G2009102019567D00053
for
Figure G2009102019567D00052
here; Simultaneously, utilize photoetching and lithographic technique to carry out local etching,, part n type nitride semiconductor layer 1 is exposed, see Fig. 6 and Fig. 7 reserving the reservation position, reservation barrier layer 9 ' wideer slightly, P electrode vapor deposition position than P electrode.
Step 3; Utilize plasma chemical vapor deposition technique reserving position, barrier layer 9 ' deposited barrier layer 9; The diameter on this barrier layer 9 is 100 microns-120 microns; The degree of depth can be silicon dioxide or silicon nitride for
Figure G2009102019567D00061
this barrier layer 9, sees Fig. 8 and Fig. 9; This part act as active layer sends under the P electrode light owing to receive stopping of P electrode, can't send, and electric current can hinder the diffusion of electric current because the most fugitive fruit of distance concentrate on here.
Step 4; Utilize coating technique vapor deposition layer of transparent conductive layer 5 on P type nitride semiconductor layer 3; The thickness d of this transparency conducting layer 5 is for
Figure G2009102019567D00062
and utilize photoetching and dry method or wet etching technique to expose vapor deposition P electrode zone; Transparency conducting layer N electrode amplification line 10 be need increase simultaneously herein, Figure 10 and Figure 11 seen.
Step 5 is utilized photoetching and evaporation coating technique electrode evaporation on n type nitride semiconductor layer 1 and P type nitride semiconductor layer 3, forms N electrode 7 and P electrode 6 respectively, need increase metal conducting layer N electrode amplification line 11 herein, sees Figure 12 and Figure 13; This metal conducting layer N electrode amplification line 11 is identical with the purpose of increase transparency conducting layer N electrode amplification line 10 in the step 4, and the position of formation is identical, but the mode effectiveness that forms is different; The conductive capability of metal conducting layer N electrode amplification line 11 is strong, and the electric current diffusion effect is good, though transparency conducting layer N electrode amplification line 10 conductive capabilities not as good as metal, but do not stop luminous, beneficial to the edge bright dipping.To semiconductor device, electric current diffusion problem is to influence a bigger aspect of luminous efficiency, and from graphic designs, the spacing of N electrode and P electrode distributes even more, and the electric current diffusion effect is good more.Therefore, graphic designs is become N electrode band amplification line mode, make that two continuous electrodes of straight line form fan-shaped distribution originally, help the electric current diffusion.
Step 6; Utilize plasma chemical vapor deposition technique at chip surface deposition diaphragm 8; This diaphragm can be silicon dioxide, silicon nitride etc.; The thickness of this diaphragm only exposes the solder joint part of N electrode 7 and P electrode 6 for
Figure G2009102019567D00063
, see Figure 14.
Embodiment two:
The manufacturing approach of another kind of high-brightness LED chip of the present invention, the difference of itself and embodiment 1 is step 2, other step (step 1, three, four, five, six) is all identical with embodiment 1.
The step 2 of this embodiment two is specially: utilize the preparatory vapor deposition N electrode position deposition diaphragm of plasma chemical vapor deposition technique at semiconductor layer; This diaphragm can be silicon dioxide, silicon nitride etc.; The thickness of this diaphragm is then; Utilize photoetching and lithographic technique to carry out local etching; Part n type nitride semiconductor layer 1 is exposed; Be N type rotary island barrier layer 4 and reservation N electrode vapor deposition position here, and form the difference in height that N type rotary island barrier layer 4 is lower than about reservation N electrode vapor deposition position ; Simultaneously, utilize photoetching and lithographic technique to carry out local etching,, part n type nitride semiconductor layer 1 is exposed, see Fig. 6 and Fig. 7 reserving the reservation position, reservation barrier layer 9 ' wideer slightly, P electrode vapor deposition position than P electrode.
The high-brightness LED chip that adopts the inventive method to make is shown in figure 14, and behind the employing catch ring (N type rotary island barrier layer 4), electric current planar diffusion better effects if can not concentrate on the corner vertical proliferation.Electric charge is assembled in the bottom of catch ring, and is not to assemble at P type gallium nitride layer 3 or active layer 2, helps promoting antistatic effect.

Claims (12)

1. the manufacturing approach of a high-brightness LED chip is characterized in that, comprises the steps:
The first step prepares semiconductor epitaxial layers on nonconducting substrate, comprise n type nitride semiconductor layer at least, be positioned at the active layer on the n type nitride semiconductor layer and be positioned at the P type nitride semiconductor layer on the active layer;
Second step; Utilize photoetching and lithographic technique to carry out local etching; The part n type nitride semiconductor layer is exposed; Exposed portions serve is N type rotary island barrier layer, reserves N electrode vapor deposition position and reserve the position, barrier layer, and forms N type rotary island barrier layer and be lower than that to reserve N electrode vapor deposition position certain height poor, and this position, reservation barrier layer is positioned at P electrode vapor deposition position and wideer slightly than P electrode;
In the 3rd step, utilize plasma chemical vapor deposition technique reserving position, barrier layer deposited barrier layer;
The 4th step; Utilize coating technique vapor deposition layer of transparent conductive layer on P type nitride semiconductor layer; And the while increases N electrode amplification line on the exposed portions serve n type nitride semiconductor layer; Said N electrode amplification line is a transparency conducting layer N electrode amplification line, and said exposed portions serve n type nitride semiconductor layer is for reserving N electrode vapor deposition position;
The 5th step; Utilize photoetching and evaporation coating technique difference vapor deposition N electrode and P electrode on n type nitride semiconductor layer and P type nitride semiconductor layer; And the while increases N electrode amplification line on the exposed portions serve n type nitride semiconductor layer; Said N electrode amplification line is a metal conducting layer N electrode amplification line, and said exposed portions serve n type nitride semiconductor layer is for reserving N electrode vapor deposition position;
The 6th step, utilize plasma chemical vapor deposition technique to deposit diaphragm at chip surface, only expose the solder joint part of N electrode and P electrode.
2. the manufacturing approach of high-brightness LED chip according to claim 1; It is characterized in that, also comprise the steps: to utilize the preparatory vapor deposition N electrode position deposition diaphragm of plasma chemical vapor deposition technique between the first step and second goes on foot at semiconductor layer.
3. the manufacturing approach of high-brightness LED chip according to claim 2 is characterized in that, said diaphragm is silicon dioxide or silicon nitride.
4. according to the manufacturing approach of claim 2 or 3 described high-brightness LED chips; It is characterized in that the thickness of said diaphragm is
Figure FSB00000712172300021
5. the manufacturing approach of high-brightness LED chip according to claim 1 is characterized in that, in the 3rd step, said barrier layer is silicon dioxide or silicon nitride.
6. according to the manufacturing approach of claim 1 or 5 described high-brightness LED chips; It is characterized in that; In the 3rd step; The diameter on said barrier layer is 100 microns-120 microns, and the degree of depth is
Figure FSB00000712172300022
7. the manufacturing approach of high-brightness LED chip according to claim 1; It is characterized in that second step can specifically be divided into for two steps: steps A, utilize photoetching and lithographic technique to carry out local etching; Part n type gallium nitride layer is exposed, here for reserving N electrode vapor deposition position; Step B utilizes photoetching and lithographic technique to carry out local etching, and part n type gallium nitride layer is exposed, and is N type rotary island barrier layer here.
8. the manufacturing approach of high-brightness LED chip according to claim 7; It is characterized in that, the degree of depth of reserving N electrode vapor deposition position in the steps A be among
Figure FSB00000712172300023
step B N type rotary island barrier layer the degree of depth is
Figure FSB00000712172300024
9. the manufacturing approach of high-brightness LED chip according to claim 1; It is characterized in that N type rotary island barrier layer described in second step is lower than reserves N electrode vapor deposition position certain height difference for
Figure FSB00000712172300031
10. the manufacturing approach of high-brightness LED chip according to claim 1; It is characterized in that the thickness of transparency conducting layer is
Figure FSB00000712172300032
described in the 4th step
11. the manufacturing approach of high-brightness LED chip according to claim 1 is characterized in that, diaphragm is silicon dioxide or silicon nitride described in the 6th step.
12. manufacturing approach according to claim 1 or 11 described high-brightness LED chips; It is characterized in that the thickness of diaphragm is
Figure FSB00000712172300033
described in the 6th step
CN2009102019567A 2009-12-18 2009-12-18 Method for manufacturing high-brightness light emitting diode chip Expired - Fee Related CN102104099B (en)

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Citations (3)

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Publication number Priority date Publication date Assignee Title
CN1953225A (en) * 2005-10-17 2007-04-25 三星电机株式会社 Nitride semiconductor light-emitting diode
CN101075654A (en) * 2006-09-05 2007-11-21 武汉迪源光电科技有限公司 Process for reversing pure-golden Au alloy bonding LED
CN101276871A (en) * 2007-03-29 2008-10-01 晶元光电股份有限公司 Photovoltaic element, backlight module apparatus and illumination device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1953225A (en) * 2005-10-17 2007-04-25 三星电机株式会社 Nitride semiconductor light-emitting diode
CN101075654A (en) * 2006-09-05 2007-11-21 武汉迪源光电科技有限公司 Process for reversing pure-golden Au alloy bonding LED
CN101276871A (en) * 2007-03-29 2008-10-01 晶元光电股份有限公司 Photovoltaic element, backlight module apparatus and illumination device

Non-Patent Citations (1)

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Title
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