CN102103184A - Method for extracting non-linear thermal resistance of transistor - Google Patents

Method for extracting non-linear thermal resistance of transistor Download PDF

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CN102103184A
CN102103184A CN 201110024319 CN201110024319A CN102103184A CN 102103184 A CN102103184 A CN 102103184A CN 201110024319 CN201110024319 CN 201110024319 CN 201110024319 A CN201110024319 A CN 201110024319A CN 102103184 A CN102103184 A CN 102103184A
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thermal resistance
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孙玲玲
刘军
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Hangzhou Dianzi University
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Abstract

The invention relates to a method for extracting non-linear thermal resistance of a transistor. In the conventional method, thermal resistance values extracted at different power levels are not a constant, so that the problems of difficulty in determination of the thermal resistance and the like are easy to cause. The method comprises the following steps of: establishing relations between the thermal resistance Rth of the transistor and direct current power dissipation Pd as well as model parameters RO, RA and RB, relations between the direct current power dissipation Pd and drain current Ids as well as drain-source voltage Vds and relations among a junction temperature Tj, an external temperature TA, the thermal resistance Rth and the direct current power dissipation Pd so as to determine the relation among variations; calculating the variation delta Ids of the Ids of fixed gate-source voltage along with the variations of the Tj and the Vds; measuring the relation characteristic of drain current and drain voltage under the conditions of different external temperatures and fixed gate voltage; and finally obtaining the thermal resistance according to the measured parameters and a model. The method is simple and efficient.

Description

A kind of method of extracting the non-linear thermal resistance of transistor
Technical field
The invention belongs to integrated circuit fields, relate to the integrated circuit (IC)-components modelling technique, relate in particular to the thermal resistance model extractive technique of power transistor in the integrated circuit.
Background technology
Have benefited from its high power density and voltage breakdown, as GaAs, GaN MESFET/HEMT, and Si base high-voltage LDMOS FET, SOI LDMOSFET etc. are used widely in the high frequency power integrated circuit (IC) design.Because of its big power density, these devices are usually operated under the very high junction temperature.Thermal resistance is to describe the transistor self-heating effect to cause and import/go out one of important parameter of power attenuation, the accurate extraction of this parameter, and under accurate prediction different input power level, the variation of device junction temperature, the variation of output characteristics have great significance.Thermal resistance also is to set up this transistorlike to be used for one of compact model desired parameters that carries out as the Spice instrument emulation simultaneously.
The relation of semiconductor material thermal conductivity and material temperature can singlely be tested material and be obtained, and adopts following formula to describe:
Figure 260662DEST_PATH_IMAGE001
(1)
In the formula: κ (T) is a material thermal conductivity, κ RefBe material thermal conductivity under reference temperature, T RefBe reference temperature, α represents thermal conductivity and dependence on temperature.
Under the known situation of material thermal conductivity, but material thermal resistance simple computation is:
(2)
In the formula: R ThBe thermal resistance, R Th, refThe expression material is in reference temperature T Ref. the time thermal resistance.
Consider that the transistor substrate material that adopts integrated circuit fabrication process production to obtain is composited by multiple material usually, it is the substrat structure of a complexity, that hot-fluid exists when flowing through the different materials interface is discontinuous, the employing as technologies such as isolation, the actual factors of making between obtained device size and the design size such as error, adopts following formula to calculate the gained thermal resistance and can't be equal to the true thermal resistance of device.
Be applied to the thermal resistance of compact model modeling, be treated to usually and constant that junction temperature and power consumption are irrelevant, and adopt following formula calculate certain power consumption ( P d) under the condition, the variation of device junction temperature:
Figure 53169DEST_PATH_IMAGE003
(3)
Under the continuous wave condition, P dBe calculated as follows:
Figure 2011100243194100002DEST_PATH_IMAGE004
(4)
The nonlinear characteristic of semiconductor material thermal conductivity/thermal resistance and junction temperature is known already, and following formula adopts constant R ThCalculate the method for junction temperature and in fact ignored this characteristic, it is less than normal to cause calculating the gained junction temperature during practical application; Adopt the thermal resistance extracting method of constant thermal resistance hypothesis, extracting under the different capacity level and obtaining thermal resistance value is not constant, causes problems such as thermal resistance is difficult to determine easily.
Summary of the invention
Technical matters to be solved by this invention is in order to set up conventionally test data in the transistor model process by the standard technology line, need not be by under as additional testing equipment situations such as infrared thermal imaging instruments, extraction obtains thermal resistance parameters, can accurately be used for junction temp of transistor variation, transistor thermal resistance optimal design under the assessment of power transistor self-heating effect, the different capacity level.
In order to solve the problems of the technologies described above, the invention provides a kind of method of extracting the non-linear thermal resistance of transistor, its step is as follows:
(1) sets up transistorized thermal resistance R ThDissipate with DC power P d, model parameter R O, R A, R B, DC power dissipates P dWith drain current I Ds, drain source voltage V Ds, junction temperature T jWith ambient temperature T A, thermal resistance R Th, DC power dissipates P dBecome following relation:
Figure 645955DEST_PATH_IMAGE005
Figure 916531DEST_PATH_IMAGE007
；
(2) calculate by step (1) T j Variation delta T j, outer temperature T AVariation delta T A, P d Variation delta P d , I DsVariation delta I Ds, V DsVariation delta V DsAnd R ThVariation delta R ThBecome following relation:
Figure 2011100243194100002DEST_PATH_IMAGE008
Figure 793220DEST_PATH_IMAGE009
Figure 2011100243194100002DEST_PATH_IMAGE010
；
(3) calculate fixing gate source voltage I DsWith T jWith V DsBe varied to following relation:
Figure 491049DEST_PATH_IMAGE011
Wherein
Figure 2011100243194100002DEST_PATH_IMAGE012
Be the leakage conductance of no self-heating effect influence, Represent what no self-heating effect influenced I Ds, T( I Ds)=
Figure 770031DEST_PATH_IMAGE013
/ TThe temperature coefficient of expression drain current;
(4) will K OBe made as , can calculate by step (1) T jWith and variation delta T jBecome following relation:
Figure 501227DEST_PATH_IMAGE015
Figure 2011100243194100002DEST_PATH_IMAGE016
?；
(5) calculate by step (4) I DsVariation delta I DsBecome following relation:
Figure 307640DEST_PATH_IMAGE017
；
(6) with in the step (5) T APerhaps V DsBe set to constant respectively, can obtain following equation respectively:
Figure 2011100243194100002DEST_PATH_IMAGE018
Figure 937336DEST_PATH_IMAGE019
；
(7) equation of the relation set up in the step (1) and step (6) combined obtain following equation:
；
(8) step (3) is in step (7) T( I Ds) be made as fixed value T A, under different ambient temperatures and fixed railing pole tension condition, measure the relation property of drain current and drain voltage;
(9) in step (8), thereby measure the leakage conductance that the S parameter obtains three different no self-heating effect influences under selected three different drain voltage conditions
Figure 73099DEST_PATH_IMAGE012
(10) utilize the Equation for Calculating that obtains in the step (7) to obtain three different parameters F, and then calculate K OValue, by K ODefinition can calculate R O, R AWith R B,And then calculate transistorized thermal resistance R Th
As possibility, the leakage conductance of no self-heating effect influence Be by directly at high frequency two ports of measuring SParameter obtains.
As possibility, the temperature coefficient of drain current T( I Ds) can obtain by the pulse test that changes ambient temperature.
As possibility, choose the leakage conductance of no self-heating effect influence in the tangible zone of self-heating effect
Figure 744569DEST_PATH_IMAGE012
As possibility, utilize the measurement data under the continuous wave condition to obtain thermal resistance R Th, its error can be by first or the transistorized thermal resistance that draws of a preceding iterative computation R ThAccurately revise, the method for parameter correction is as follows:
Figure 2011100243194100002DEST_PATH_IMAGE022
Δ wherein I DsCalculate by the relation property that under different ambient temperatures and fixed railing pole tension condition, measures drain current and drain voltage.
As possibility, an error range value can be set, then under specific output power condition, calculate thermal resistance poor of a thermal resistance that this iterative computation obtains and a preceding iteration gained, by judging whether this difference satisfies accuracy requirement and determine whether continuing iteration.
The invention has the advantages that the conventionally test data calculate thermal resistance in the transistor model process in order to set up by the standard technology line, thereby need be by as additional testing equipment such as infrared thermal imaging instruments, and because the test data of using in the thermal resistance leaching process also is to set up the required test data of transistor compact model simultaneously, therefore when adopting this method to set up to be used for power transistor emulation with the thermal effect model, the data that can avoid adopting different test structures to obtain carry out transistor model parameter extract the problem that may bring.
Description of drawings
Fig. 1 is AlGaN/GaN HEMT device architecture figure;
Fig. 2 for the junction temperature of the junction temperature of the thermal resistance extracted, measurement and emulation with the variable power curve map.
Embodiment
Below in conjunction with accompanying drawing a kind of embodiment of extracting the method for the non-linear thermal resistance of transistor provided by the invention is elaborated.
Suppose that the dissipation of transistorized thermal resistance and DC power exists nonlinear relationship, this nonlinear relationship and junction temperature T jRelevant
（5）
Wherein R O , R A With R B Be model parameter, P d With T j Be defined as
Figure 2011100243194100002DEST_PATH_IMAGE024
（6）
（7）
Wherein I DsBe drain current, V DsBe drain source voltage, T ABe ambient temperature (outer temperature).Because gate power dissipation is compared and can be ignored with the drain electrode power dissipation, has also ignored the contribution of gate leakage to power dissipation in (6) formula.According to (6) formula and (7) formula, T jVariation delta T jWith outer temperature T AVariation delta T A, P d Variation delta P d , and R ThVariation delta R ThHave following relation:
（8）
Wherein
Figure 737343DEST_PATH_IMAGE027
（9）
Figure 2011100243194100002DEST_PATH_IMAGE028
（10）
Δ wherein I DsAnd Δ V DsBe respectively I DsWith V DsVariable quantity.
For fixing gate source voltage (is Δ V Gs=0), I DsWith T jWith V DsVariation can be expressed as
（11）
Wherein
Figure 2011100243194100002DEST_PATH_IMAGE030
Represent what no self-heating effect influenced I Ds,
Figure 420446DEST_PATH_IMAGE031
The leakage conductance of representing no self-heating effect influence.Among the present invention,
Figure 2011100243194100002DEST_PATH_IMAGE032
Be to use =real ( Y 22+ Y 12) direct high frequency two ports of measuring YExtract in the parameter. T( I Ds)=
Figure 565436DEST_PATH_IMAGE030
/ TThe temperature coefficient of expression drain current.Generally T( I Ds) can be by the pulse that changes underlayer temperature I Ds- V DsTest directly obtains (because pulse test P d≈ 0, so T j≈ T).
(6) are brought into (5), again (5) and (6) are brought into (7), can obtain T j
Figure 516075DEST_PATH_IMAGE033
（12）
And then obtain Δ T j
（13）
Wherein
Figure 460897DEST_PATH_IMAGE035
.
(10) are brought into (13), (12) and (13) are being brought into (11), can obtain Δ I Ds
Figure 2011100243194100002DEST_PATH_IMAGE036
（14）
If order T ABe constant, only change V Ds , then (14) only become with V DsThe equation that changes
Figure 626430DEST_PATH_IMAGE037
（15）
If order V Ds Be constant, only change T A, then (14) only become with T AThe equation that changes
Figure 2011100243194100002DEST_PATH_IMAGE038
（16）
In conjunction with Δ in (7) I Ds Relation, can obtain following equation
Figure 444345DEST_PATH_IMAGE039
（17）
In order to satisfy various bias conditions, (17) can be organized into
Figure DEST_PATH_IMAGE040
?（18）
With K O, i Separating (18) for unknown quantity gets
Figure 944596DEST_PATH_IMAGE041
（19）
Find out easily, F i Can directly from measurement data, extract.And only need measure three F iJust can obtain K O, i Like this, according to K ODefinition just can obtain R O , R AWith R B
Figure DEST_PATH_IMAGE042
（20）
Figure 178262DEST_PATH_IMAGE043
（21）
Figure DEST_PATH_IMAGE044
（22）
Wherein
Figure 713149DEST_PATH_IMAGE045
, ,
Figure 639648DEST_PATH_IMAGE047
,
Figure DEST_PATH_IMAGE048
In order to verify method of the present invention, made depletion type (D-mode) AlGaN/GaN HEMT in Shijiazhuang special IC National Key Laboratory, adopt 8 grid to refer to T type grid, grid width 80 , grid long 0.3
Figure 664553DEST_PATH_IMAGE049
, grid center distance 40
Figure 726050DEST_PATH_IMAGE049
, gate-to-source spacing 1
Figure 72717DEST_PATH_IMAGE049
Concrete device architecture is referring to Fig. 1.Saturated I DsBe 1A/mm, direct current mutual conductance (g m) be 130mS/mm.Characteristic frequency f tBe 15 GHz.Maximum oscillation frequency f MaxBe 26 GHz.
Adopt the Cascade probe station of HP4156C analyzing parameters of semiconductor instrument and band alternating temperature case to measure among the present invention V Gs=0 V, V Ds, 1=21 V, V Ds, 2=24 V, V Ds, 3=27V, V Ds, 4=30V, T A=25 ℃ and 40 ℃ (is Δ V Ds=3V and Δ T A =15 ℃) under the condition I Ds/ T AWith I DsCharacteristic.From test data, calculated F i ( i=1,2,3).For determining device
Figure 485244DEST_PATH_IMAGE032
Characteristic, at 50 MHz, V Gs=0V and V Ds=0～30V has tested two ports of device with Agilent E8363B vector network analyzer under the step-length 3V condition SParameter.Adopt GSG PAD, and (Open+Short) method has carried out going embedding to test data with the open circuit short circuit.With what record SParameter changes into YParameter is used for V Ds, 1=21V, V Ds, 2=24V and V Ds, 3Under=27V the condition
Figure 513243DEST_PATH_IMAGE032
Extraction.Adopted thermal infrared imaging instrument direct acquisition device in addition under various power dissipation conditions T jCharacteristic.
The thermal resistance that the present invention changes with power dissipation in determining reality R ThShi Caiyong simple iterative calculation method.At first, usefulness is measured I Ds/ T ACalculate R O , R AWith R BInitial value.Then, with this initial value correction T( I Ds), thereby obtain more accurately K O, i P d=1W is the criterion of iterative loop.Table 1 has been listed the resistance value of six iteration altogether.The 6th time error minimum (| R Th, 6– R Th, 5| ≈ 0.01), the extraction value is R O =16.17 ℃/W, R A=0.635 ℃/W 2, R B=-0.005 ℃/W 3
Each resistance value in six circulations when table 1. extracts thermal resistance
J 1 2 3 4 5 6
R O (°C/W) 14.59 15.74 16.06 16.15 16.17 16.17
R A (°C/W 2) 0.907 0.712 0.656 0.640 0.636 0.635
R B (°C/W 3) -0.019 -0.009 -0.007 -0.006 -0.0055 -0.005
R th (°C/W) 15.48 16.45 16.71 16.78 16.79 16.80
In the iterative process, be used to revise iteration error T( I Ds) bring in (11) by (13) and to solve
Figure DEST_PATH_IMAGE050
（23）
Δ wherein I DsDraw by the measurement data approximate treatment
Δ I ds?=? I ds( V ds?+Δ V ds,? T A+Δ T A?)?-? I ds( V ds,? T A) （24）
Adopting the constant thermal resistance is 15.84 ℃/W( k SiC=4.08W/cmK, k GaN=1.5 W/cmK) do the accuracy contrast with method of the present invention.Fig. 2 is by the constant thermal resistance R ThWith T j_ RefCalculate R Th, T j, T j, and T jWith T J_refError with power dissipation P d Situation of change, test condition is V Gs=0V, V Ds=0 to 30V, step-length 1V. P d During=9.5W T J_refError 40 ° of C are arranged.The non-linear thermal resistance model that the present invention proposes then has well identical with test data.And by formula (12) basis R O , R AWith R BThe extraction value calculate T j Also have well identical with test result.Confirmed validity of the present invention.

Claims (5)

1. a method of extracting the non-linear thermal resistance of transistor is characterized in that, this method may further comprise the steps:
Step (1) is set up transistorized thermal resistance R ThDissipate with DC power P d, model parameter R O, R A, R BRelation; Setting up DC power dissipates P dWith drain current I Ds, drain source voltage V DsRelation; Set up junction temperature T jWith ambient temperature T A, thermal resistance R Th, DC power dissipates P dRelation:
Figure 2011100243194100001DEST_PATH_IMAGE001
Figure 905387DEST_PATH_IMAGE002
；
Step (2) calculates by step (1) T j Variation delta T j , outer temperature T AVariation delta T A, P d Variation delta P d , I DsVariation delta I Ds, V DsVariation delta V DsAnd R ThVariation delta R ThBecome following relation:
Figure 832892DEST_PATH_IMAGE004
Figure 2011100243194100001DEST_PATH_IMAGE005
Figure 34066DEST_PATH_IMAGE006
；
Step (3) is at fixing gate source voltage V GsSituation under calculate Δ I DsWith T jWith V DsBe varied to following relation:
Figure 2011100243194100001DEST_PATH_IMAGE007
Wherein
Figure 679811DEST_PATH_IMAGE008
Be the leakage conductance of no self-heating effect influence,
Figure 2011100243194100001DEST_PATH_IMAGE009
Represent what no self-heating effect influenced I Ds, T( I Ds)=
Figure 493309DEST_PATH_IMAGE009
/ TThe temperature coefficient of expression drain current;
Step (4) will K OBe made as , calculate by step (1) T jWith and variation delta T jBecome following relation:
Figure 912974DEST_PATH_IMAGE012
；
Step (5) calculates I DsVariation delta I DsBecome following relation:
Figure 2011100243194100001DEST_PATH_IMAGE013
；
Step (6) is with in the step (5) T ABe set to constant, obtain:
；
With in the step (5) V DsBe set to constant, obtain:
Figure 2011100243194100001DEST_PATH_IMAGE015
；
Step (7) combines the equation of the relation set up in the step (1) and step (6) and obtains following equation:
Figure 663204DEST_PATH_IMAGE016
Figure 2011100243194100001DEST_PATH_IMAGE017
；
Step (8) arrives step (3) in the step (7) T( I Ds) be made as fixed value T A, under different ambient temperatures and fixed railing pole tension condition, measure the relation property of drain current and drain voltage;
Step (9) thus measure the leakage conductance that scattering parameter obtains three different no self-heating effects influences under selected three different drain voltage conditions
Figure 627618DEST_PATH_IMAGE008
Step (10) is utilized the leakage conductance of three different no self-heating effect influences
Figure 108278DEST_PATH_IMAGE008
And integrating step (7) obtains three different parameters F, and then calculate three K OValue, by K ODefinition can calculate R O, R AWith R B, and then calculate transistorized thermal resistance R Th
2. a kind of method of extracting the non-linear thermal resistance of transistor according to claim 1 is characterized in that, the leakage conductance of the no self-heating effect influence in the step (9)
Figure 400719DEST_PATH_IMAGE008
Be from the scattering parameter of high frequency two ports measured, to obtain.
3. a kind of method of extracting the non-linear thermal resistance of transistor according to claim 1 is characterized in that, the temperature coefficient of the drain current in the step (8) T( I Ds) obtain by the pulse test that changes ambient temperature.
4. a kind of method of extracting the non-linear thermal resistance of transistor according to claim 1 is characterized in that the thermal resistance of utilizing the measurement data under the continuous wave condition to obtain R Th, its error is by first or the transistorized thermal resistance that draws of a preceding iterative computation R ThRevising, specifically is corrected parameter
Figure 320133DEST_PATH_IMAGE018
:
Figure 2011100243194100001DEST_PATH_IMAGE019
。
5. a kind of method of extracting the non-linear thermal resistance of transistor according to claim 4, it is characterized in that, an error range value is set, then under the output power condition of setting, calculate the poor of thermal resistance that a thermal resistance that this iteration obtains and a preceding iteration obtain, by judging whether this difference satisfies accuracy requirement and determine whether continuing iteration.
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CN104316855A (en) * 2014-10-14 2015-01-28 北京工业大学 Junction temperature testing method of HEMT (High Electron Mobility Transistor) device
CN104316855B (en) * 2014-10-14 2017-02-15 北京工业大学 Junction temperature testing method of HEMT (High Electron Mobility Transistor) device
CN106443401A (en) * 2016-10-16 2017-02-22 北京工业大学 Power MOS device temperature rise and thermal resistance component test device and method
CN106501699B (en) * 2016-10-20 2019-02-19 北京工业大学 The method for real-time measurement of bipolar transistor junction temperature under a kind of saturation state
CN106501699A (en) * 2016-10-20 2017-03-15 北京工业大学 The method for real-time measurement of bipolar transistor junction temperature under a kind of saturation
CN106802385B (en) * 2017-01-12 2019-03-08 中国科学院微电子研究所 Thermal resistance extraction method of SOI MOS device
CN106802385A (en) * 2017-01-12 2017-06-06 中国科学院微电子研究所 Thermal resistance extraction method of SOI MOS device
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CN111983411A (en) * 2020-07-10 2020-11-24 中国电子科技集团公司第十三研究所 Method and device for testing thermal resistance of multi-finger-gate transistor and terminal equipment
CN111983411B (en) * 2020-07-10 2022-12-27 中国电子科技集团公司第十三研究所 Method and device for testing thermal resistance of multi-finger-gate transistor and terminal equipment
CN113533922A (en) * 2021-06-07 2021-10-22 大连理工大学 Method for quickly and accurately measuring junction temperature of GaN power electronic device with Cascode structure
CN113533922B (en) * 2021-06-07 2022-06-14 大连理工大学 Method for quickly and accurately measuring junction temperature of GaN power electronic device with Cascode structure
CN116187113A (en) * 2023-05-04 2023-05-30 成都明夷电子科技有限公司 Integrated circuit chip thermal simulation junction temperature correction method based on Gao Beigong external thermal imaging
CN116187113B (en) * 2023-05-04 2023-08-04 成都明夷电子科技有限公司 Integrated circuit chip thermal simulation junction temperature correction method based on Gao Beigong external thermal imaging

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