CN102097784B - Relay protective optical fiber digital interface device - Google Patents
Relay protective optical fiber digital interface device Download PDFInfo
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- CN102097784B CN102097784B CN201110026783.7A CN201110026783A CN102097784B CN 102097784 B CN102097784 B CN 102097784B CN 201110026783 A CN201110026783 A CN 201110026783A CN 102097784 B CN102097784 B CN 102097784B
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Abstract
The invention relates to a relay protective optical fiber digital interference device, which comprises a switching value input circuit, a switching value output circuit and two central processing units (CPUs), wherein the output end of the switching value input circuit is connected to input ports of the two CPUs respectively; the output ends of the two CPUs are connected to the input end of an AND gate circuit; the output end of the AND gate circuit is in control connection with the switching value output circuit; each CPU comprises a transmission part and a receiving part; signals input into each CPU channel are processed by a delay judging module, a coding and framing module and a transcoder module of the transmission parts, and transmitted to a photoelectric conversion module; and the CPUs receive the signals from the photoelectric conversion module, process the signals by a code pattern inverse transformation module and a de-framing and decoding module of the receiving parts and output the signals by the output circuit. The relay protective optical fiber digital interference device adopts the two CPU and the two channels, realizes the increasing of transmission time and great improvements on safety and reliability.
Description
Technical field
The invention belongs to technical field of relay protection, relate to a kind of high integrated relay protective optical fiber digital interface device.
Background technology
Relay protective optical fiber digital interface device is to utilize transmission line, is specifically designed to the power equipment with simple function that transmits relay protection signal, can transmit the command signal of a plurality of relaying protections, and it is different from power line carrier transreceiver.Relay protective optical fiber digital interface device is used for transmitting relaying protection trip signal, thus higher to the requirement in transmission time, in general several milliseconds; Also very high to the stability requirement of the transmission reliability of order, device in addition, if because wrong order or loss order cause protection tripping or malfunction, loss is inconceivable so.
Existing a kind of relaying protection fiber optic data communication interface device as shown in Figure 1; this device detects command signal by a cpu chip by interruption; then signal is sent to SCC serial communication controller and peripheral chip circuit by serial ports, coding and decoding then, then carry out opto-electronic conversion.The Key Circuit of this device is that series winding connects, and key node is many, and transmitting each other data has certain time delay; When any key node breaks down, whole equipment is just out of service, increases failure rate; Transfer of data link is many, has increased unreliability; If send order and take orders, start simultaneously, may cause parallel conflict, increased unreliability.
Summary of the invention
The object of this invention is to provide a kind of binary channels relay protective optical fiber digital interface device, to solve the problem that existing interface plant failure rate is high, reliability and stability are poor.
For achieving the above object, relay protective optical fiber digital interface device of the present invention, comprise switching value input circuit, switching value output circuit and CPU, the output of switching value input circuit is connected into the input port of CPU, CPU control connection switching value output circuit, described CPU is divided into transmitting portion and receiving unit, and transmitting portion comprises delay judgement module, coding and framing module and code conversion module, and receiving unit comprises pattern inverse transform module, separates frame and decoder module; The signal of input CPU is after delay judgement module, coding and the framing module and code conversion resume module of transmitting portion, send to photoelectric conversion module, the signal that CPU receives from photoelectric conversion module is exported by output circuit after pattern inverse transform module, solution frame and the decoding resume module of receiving unit.
Further, described CPU is the CPLD chip with parallel processing capability.
Further, also comprise service unit, this service unit is connected with described CPU, and service unit is provided with the interface being connected with man-machine interface communication.
Further, described service unit is a single-chip microcomputer.
Further, described CPU receiving unit also comprises differentiates time module and output expansion module, and described signal is exported by output after processing through decoder module, differentiation time module, output expansion module.
Another relay protective optical fiber digital interface device technical scheme of the present invention is: comprise switching value input circuit, switching value output circuit, also comprise two CPU, two CPU form two-way independent channel with optical-fibre channel separately respectively, the output of described switching value input circuit is connected into respectively the input port of two CPU, the output of two CPU is connected into AND circuit input, the output control connection switching value output circuit of AND circuit; Described two CPU are divided into transmitting portion and receiving unit, and transmitting portion comprises delay judgement module, coding and framing module and code conversion module, and receiving unit comprises pattern inverse transform module, separates frame and decoder module; Input the signal of each CPU channel after delay judgement module, coding and the framing module and code conversion resume module of transmitting portion, send to photoelectric conversion module, the signal that CPU receives from photoelectric conversion module is exported by output circuit after pattern inverse transform module, solution frame and the decoding resume module of receiving unit.
Further, described CPU is the CPLD chip with parallel processing capability.
Further, also comprise two single-chip microcomputers, single-chip microcomputer is provided with the interface being connected with man-machine interface communication, two are connected corresponding with described two CPU of single-chip microcomputer.
Further, described CPU receiving unit also comprises differentiates time module and output expansion module, and described signal is exported by output after processing through decoder module, differentiation time module, output expansion module.
Further, when described AND circuit does not have input command, with the input of door be high level, after order is come, input changes low level into.
Relay protective optical fiber digital interface device of the present invention; CPU is divided into transmitting portion and receiving unit; transmitting portion comprises delay judgement module, coding and framing module and code conversion module; receiving unit comprises pattern inverse transform module, separates frame and decoder module; order sending and receiving, Code And Decode can be carried out simultaneously; and can be in the inner realization of CPU; reduce command transfer link; key components reduces to one, makes reliability, stability, the command transfer time of interface arrangement have significantly raising.CPU adopts the CPLD chip possess parallel processing capability, if a plurality of order arrives simultaneously, adopts the parallel behavior of CPLD, can parallel processing command signal, and can not cause order to lose.
Another relay protective optical fiber digital interface device of the present invention, adopts two CPU and optical-fibre channel forms separately binary channels, has increased reliability and stability; Each CPU is divided into transmitting portion and receiving unit, transmitting portion comprises delay judgement module, coding and framing module and code conversion module, receiving unit comprises pattern inverse transform module, separates frame and decoder module, at detection, transmission, decoding and coding, the output receiving course of order, all in CPU inside, realize like this, reduce command transfer link, key components reduces to one, makes reliability, stability, the command transfer time of interface arrangement have significantly raising.CPU adopts the CPLD chip possess parallel processing capability, if a plurality of order arrives simultaneously, adopts the parallel behavior of CPLD, can parallel processing command signal, and can not cause order to lose.Interface arrangement stable and reliable operation of the present invention, by quality control computational methods, calculate failure rate, with existing interface arrangement, compare and reduced by three magnitudes, thereby improved the stability of power system operation, adopt reliable encoding and decoding technique, increase the reliability of order, also reduced maintenance cost, this is all a no small expense to user and manufacturer simultaneously.
Accompanying drawing explanation
Fig. 1 is the theory diagram of existing interface device;
Fig. 2 is the theory diagram of interface arrangement embodiment of the present invention;
Fig. 3 is the theory diagram of binary channels interface arrangement of the present invention;
Fig. 4 is the theory diagram of CPLD of the present invention.
Embodiment
One, relay protective optical fiber digital interface device (single channel)
Relay protective optical fiber digital interface device of the present invention is as Fig. 2, shown in Fig. 4, the relay protective optical fiber digital interface device of this embodiment comprises switching value input circuit, switching value output circuit, CPU and service unit, CPU is the CPLD chip with parallel processing capability, service unit is provided with the interface being connected with man-machine interface communication, service unit is a single-chip microcomputer, the output of switching value input circuit is connected into the input port of CPLD chip, CPLD chip controls connecting valve amount output circuit, CPLD chip is divided into transmitting portion and receiving unit, it is delay judgement module that transmitting portion is provided with input time delay, decimation blocks, coding and framing module, code conversion module, receiving unit is provided with pattern inverse transform module, synchronization module, solution frame module, decoder module, differentiation time module and output expansion module.
Switching value input circuit is mainly that the command signal of outer protection input is transformed into the logic level of device inside through light-coupled isolation.Switching value output circuit is mainly that received command signal is transformed into corresponding contact output.The core of device is CPLD, and it receives orders after signal, through the input time delay module of transmitting portion, decimation blocks, then coding, framing, then through code bit conversion, sends to photoelectric conversion module, converts light signal to; Because CPLD has parallel processing capability, it also carries out code bit conversion the data that receive from optical-electric module through the pattern inverse transform module of receiving unit when sending, and then separates frame, decoding, through optional time delay, command signal is delivered to order output loop.Service unit is a single-chip microcomputer, and it does some initial work when powering on, and the parameter of receive-after-transmit time delay is provided to CPLD, does in addition the management work of some other affairs, but it does not participate in the transmission of order.
In CPLD chip, be also provided with the latch 1, latch 2 and the buffer that are connected with single-chip microcomputer.
According to Fig. 4, as follows to CPLD chip schematic block diagram illustration:
Label is that be input in buffer 1.～data are 9. respectively:
1. .1 ... the state that says the word of 4 command channels;
2. .5 ... the state that says the word of 8 command channels;
3. .1 ... the receipts coomand mode of 4 command channels;
4. .5 ... the receipts coomand mode of 8 command channels;
5.. receiving alarm;
6.. error rate alarm;
7.. OOF alarm
;
8.. light path A interrupts (light path receiving alarm A);
9.. light path B interrupts (light path receiving alarm B).
transmitting portion
1) input time delay module
Time delay module can avoid noise to think by mistake " order " state.When input order signal is found low level, time delay module is started working.The work clock of time delay module is 64k, and the time of delay is exactly the counting to clock pulse.
2) decimation blocks
The clock frequency that data send is 64K, and the data of a frame are totally 80 bits, and transmitting time is 1.25ms, and therefore between two frames, transmission time interval is 1.25ms; Therefore need to be to command signal sampling once every 1.25ms.
3) coding and framing module
Coding and framing are all subject to the control of command mode.Front 4 orders are called to A group command, rear 4 orders are called B group command, in the time of 4 command job mode, only need encode to the command signal of A group command, framing, transmission, in the time of 8 command job mode, need the processes such as coding framing transmission that A, B two group commands are hocketed.Encoding and decoding adopt 48 block codes, and this kind of method can occur correcting lower than the error code of 24 in 48, have increased the reliability of transmission.
4) code conversion module
Through coding, be 64khz with the clock frequency of the framing module output data data that namely shift register shifts out, these data changed into the signal of 256khz, data 1 are become to 1100, data 0 are become to 1010.
receiving unit
1) pattern inverse transform module
It is 1100 or 1010 that CPLD receives data mode from code conversion circuit, need to change into 1,1010 1100 and change into 0, and pattern inverse transform module completes such function.
2) synchronization module
Before separating frame decoding, need to carry out synchronously, synchronous whole process comprises two processes of Search/Track, has just started shooting or first will search for synchronous head in the time of OOF state.Completed and synchronously just can separate frame, when separating frame, also will follow the tracks of synchronously, to avoid step-out to reenter the state of search.
3) separate frame module
After reaching synchronously, just can separate frame, in data processing unit, have four kinds of frames, be respectively A group command frame, B group command frame (corresponds respectively to front four orders, rear four orders), record frame, other ancillary frame (frame, claim frame are set), difference between frame is exactly when framing, to add different frame distinguishing marks, and concrete difference is synchronous head 8 Bit datas below.
4) decoder module
Command decode is the inverse process of command code.
5) differentiate time module
The effect of differentiation time and input time delay is just the same, and unique difference is the time delay to output command differentiating time module, and input time delay is the time delay to input command.
6) output expansion module
Output expansion is exactly that the effective status of order (order is low level) is expanded to a kind of processing of order being carried out for the normal operation of system.
Two, relay protective optical fiber digital interface device (binary channels)
Binary channels relay protective optical fiber digital interface device of the present invention as shown in Figure 3, this interface arrangement comprises switching value input circuit, switching value output circuit, two CPU, two service units, two service units are single-chip microcomputer, single-chip microcomputer is provided with the interface being connected with man-machine interface communication, two CPU all adopt the CPLD chip with parallel processing capability, two CPLD chips form two-way independent channel with optical-fibre channel separately respectively, the output of switching value input circuit is connected into respectively the input port of two CPLD chips, the output of two CPLD chips is connected into the input of AND circuit, the output control connection switching value output circuit of AND circuit, two CPLD chips are divided into transmitting portion and receiving unit as shown in Figure 4.It is delay judgement module, decimation blocks, coding and framing module, code conversion module that transmitting portion is provided with input time delay; Receiving unit is provided with pattern inverse transform module, synchronization module, solution frame module, decoder module, differentiation time module and output expansion module.
Switching value input circuit is mainly that the command signal of outer protection input is transformed into the logic level of device inside through light-coupled isolation.Switching value output circuit is mainly that received command signal is transformed into corresponding contact output.The core of device is CPLD, and it receives orders after signal, through the input time delay module of transmitting portion, and decimation blocks, then coding, framing, then through code bit conversion, send to photoelectric conversion module, convert light signal to; Because CPLD has parallel processing capability, it also carries out code bit conversion the data that receive from optical-electric module through the pattern inverse transform module of receiving unit when sending, and then separates frame, decoding, through optional time delay, command signal is delivered to order output loop.Service unit is a single-chip microcomputer, and it does some initial work when powering on, and the parameter of receive-after-transmit time delay is provided to CPLD, does in addition the management work of some other affairs, but it does not participate in the transmission of order.
CPLD(A) and CPLD(B) and separately optical-fibre channel forms two-way independent channel.The command signal that interface arrangement is received is sent to CPLD (A) and CPLD (B) simultaneously, and they are worked respectively, and command signal is sent into optical channel; Being transformed into command signal from the light signal that optical channel is received separately, two-way command signal, after AND circuit is processed, becomes a road signal, by output circuit, is exported again.
AND circuit, when not ordering, with the input of door be high level, after order is come, input just changes low level into, like this, two-way transmission channel, as long as You Yi road correctly transmits, after AND circuit, correct output command signal.Reliability is just guaranteed like this.
In CPLD chip, be also provided with the latch 1, latch 2 and the buffer that are connected with single-chip microcomputer.
According to Fig. 4, as follows to CPLD chip schematic block diagram illustration:
Label is that be input in buffer 1.～data are 9. respectively:
1. .1 ... the state that says the word of 4 command channels;
2. .5 ... the state that says the word of 8 command channels;
3. .1 ... the receipts coomand mode of 4 command channels;
4. .5 ... the receipts coomand mode of 8 command channels;
5.. receiving alarm;
6.. error rate alarm;
7.. OOF alarm
;
8.. light path A interrupts (light path receiving alarm A);
9.. light path B interrupts (light path receiving alarm B).
transmitting portion
1) input time delay module
Time delay module can avoid noise to think by mistake " order " state.When input order signal is found low level, time delay module is started working.The work clock of time delay module is 64k, and the time of delay is exactly the counting to clock pulse.
2) decimation blocks
The clock frequency that data send is 64K, and the data of a frame are totally 80 bits, and transmitting time is 1.25ms, and therefore between two frames, transmission time interval is 1.25ms; Therefore need to be to command signal sampling once every 1.25ms.
3) coding and framing module
Coding and framing are all subject to the control of command mode.Front 4 orders are called to A group command, rear 4 orders are called B group command, in the time of 4 command job mode, only need encode to the command signal of A group command, framing, transmission, in the time of 8 command job mode, need the processes such as coding framing transmission that A, B two group commands are hocketed.Encoding and decoding adopt 48 block codes, and this kind of method can occur correcting lower than the error code of 24 in 48, have increased the reliability of transmission.
4) code conversion module
Through coding, be 64khz with the clock frequency of the framing module output data data that namely shift register shifts out, these data changed into the signal of 256khz, data 1 are become to 1100, data 0 are become to 1010.
receiving unit
1) pattern inverse transform module
It is 1100 or 1010 that CPLD receives data mode from code conversion circuit, need to change into 1,1010 1100 and change into 0, and pattern inverse transform module completes such function.
2) synchronization module
Before separating frame decoding, need to carry out synchronously, synchronous whole process comprises two processes of Search/Track, has just started shooting or first will search for synchronous head in the time of OOF state.Completed and synchronously just can separate frame, when separating frame, also will follow the tracks of synchronously, to avoid step-out to reenter the state of search.
3) separate frame module
After reaching synchronously, just can separate frame, in data processing unit, have four kinds of frames, be respectively A group command frame, B group command frame (corresponds respectively to front four orders, rear four orders), record frame, other ancillary frame (frame, claim frame are set), difference between frame is exactly when framing, to add different frame distinguishing marks, and concrete difference is synchronous head 8 Bit datas below.
4) decoder module
Command decode is the inverse process of command code.
5) differentiate time module
The effect of differentiation time and input time delay is just the same, and unique difference is the time delay to output command differentiating time module, and input time delay is the time delay to input command.
6) output expansion module
Output expansion is exactly that the effective status of order (order is low level) is expanded to a kind of processing of order being carried out for the normal operation of system.
Claims (4)
1. a relay protective optical fiber digital interface device, comprise switching value input circuit, switching value output circuit, it is characterized in that: also comprise two CPU, two CPU form two-way independent channel with optical-fibre channel separately respectively, the output of described switching value input circuit is connected into respectively the input port of two CPU, the output of two CPU is connected into AND circuit input, the output control connection switching value output circuit of AND circuit; Described two CPU are divided into transmitting portion and receiving unit, and transmitting portion comprises delay judgement module, coding and framing module and code conversion module, and receiving unit comprises pattern inverse transform module, separates frame and decoder module; Input the signal of each CPU channel after delay judgement module, coding and the framing module and code conversion resume module of transmitting portion, send to photoelectric conversion module, the signal that CPU receives from photoelectric conversion module is exported by output circuit after pattern inverse transform module, solution frame and the decoding resume module of receiving unit; Described CPU is the CPLD chip with parallel processing capability.
2. relay protective optical fiber digital interface device according to claim 1, is characterized in that: also comprise two single-chip microcomputers, single-chip microcomputer is provided with the interface being connected with man-machine interface communication, two are connected corresponding with described two CPU of single-chip microcomputer.
3. relay protective optical fiber digital interface device according to claim 1; it is characterized in that: described CPU receiving unit also comprises differentiates time module and output expansion module, and the signal of each CPU channel of described input is exported by output circuit after processing through decoder module, differentiation time module, output expansion module.
4. according to the relay protective optical fiber digital interface device described in any one in claim 1-3, it is characterized in that: when described AND circuit does not have input command, with the input of door be high level, after order is come, input changes low level into.
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| CN201110026783.7A CN102097784B (en) | 2011-01-25 | 2011-01-25 | Relay protective optical fiber digital interface device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110026783.7A CN102097784B (en) | 2011-01-25 | 2011-01-25 | Relay protective optical fiber digital interface device |
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| CN102097784A CN102097784A (en) | 2011-06-15 |
| CN102097784B true CN102097784B (en) | 2014-02-05 |
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Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07322477A (en) * | 1994-05-19 | 1995-12-08 | Hitachi Ltd | Protection relay device using optical cable |
| JPH08274718A (en) * | 1995-03-29 | 1996-10-18 | Nec Corp | Interface device |
| CN101162839B (en) * | 2007-10-24 | 2010-11-24 | 国电南瑞科技股份有限公司 | Circuit relay protection information exchange method and device thereof |
| CN201134808Y (en) * | 2007-11-30 | 2008-10-15 | 南京中德保护控制系统有限公司 | Optical fiber channel simulation apparatus of circuit differential protection |
| CN101350519B (en) * | 2008-09-12 | 2011-12-14 | 南京因泰莱电器股份有限公司 | Real-time synchronization equipment for protecting optical fibre longitudinal difference |
| CN201438636U (en) * | 2009-07-22 | 2010-04-14 | 天津市电力公司 | Simple bus differential protection device for digital transformer station |
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2011
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