CN102097784B - Relay protective optical fiber digital interface device - Google Patents

Abstract

The invention relates to an optical fiber digital interface device for relay protection, comprising a switching value input circuit, a switching value output circuit, and two CPUs, the output ends of the switching value input circuit are respectively connected to the input ports of the two CPUs, and the output ends of the two CPUs are connected to the The input terminal of the gate circuit and the output terminal of the AND gate circuit are connected to the switching value output circuit; the two CPUs are divided into a sending part and a receiving part, and the signals input to each CPU channel pass through the delay judgment module of the sending part, the encoding and framing module and After the code conversion module is processed, it is sent to the photoelectric conversion module, and the signal received by the CPU from the photoelectric conversion module is output by the output circuit after being processed by the code type inverse conversion module, deframing and decoding module of the receiving part; the present invention adopts dual CPUs, dual The channel has realized the improvement of the transmission time, and the security and reliability have been greatly improved.

Description

Optical fiber digital interface device for relay protection

technical field

The invention belongs to the technical field of relay protection and relates to a highly integrated optical fiber digital interface device for relay protection.

Background technique

The optical fiber digital interface device for relay protection is a power device with a single function specially used to transmit relay protection signals by using optical transmission channels. It can transmit multiple command signals for relay protection, which is different from power line carrier transceivers. The relay protection optical fiber digital interface device is used to transmit the relay protection trip signal, so the requirements for the transmission time are relatively high, generally within a few milliseconds; in addition, the requirements for the transmission reliability of the command and the stability of the device are also very high. If the protection refuses to move or malfunctions due to wrong or lost orders, the loss is unimaginable.

An existing optical fiber communication interface device for relay protection is shown in Figure 1. The device detects the command signal through an interrupt by a CPU chip, and then transmits the signal to the SCC serial port communication controller and the peripheral chip circuit through the serial port, and then encodes Decoding, and then photoelectric conversion. The key circuit of the device is connected in series, there are many key nodes, and there is a certain delay in transmitting data between each other; when any key node fails, the entire device will stop running, increasing the failure rate; there are many data transmission links, increasing This increases unreliability; if sending commands and receiving commands starts at the same time, it may cause parallel conflicts and increase unreliability.

Contents of the invention

The purpose of the present invention is to provide a dual-channel relay protection optical fiber digital interface device to solve the problems of high failure rate, poor reliability and stability of the existing interface device.

In order to achieve the above object, the relay protection optical fiber digital interface device of the present invention comprises a switching value input circuit, a switching value output circuit and a CPU, the output end of the switching value input circuit is connected to the input port of the CPU, and the CPU controls and connects the switching value output circuit , the CPU is divided into a sending part and a receiving part, and the sending part includes a delay judgment module, an encoding and framing module and a pattern conversion module, and the receiving part includes a pattern inverse transformation module, an unframing and a decoding module; the signal input to the CPU After being processed by the delay judgment module, encoding and framing module and code conversion module of the sending part, it is sent to the photoelectric conversion module, and the signal received by the CPU from the photoelectric conversion module passes through the code inverse conversion module of the receiving part, deframes and decodes After processing by the module, it is output by the output circuit.

Further, the CPU is a CPLD chip with parallel processing capability.

Further, it also includes a service unit, the service unit is connected to the CPU, and the service unit is provided with an interface for communicating with the man-machine interface.

Further, the service unit is a single-chip microcomputer.

Further, the CPU receiving part also includes a discrimination time module and an output expansion module, and the signal is output by the output terminal after being processed by the decoding module, the discrimination time module and the output expansion module.

The technical scheme of another optical fiber digital interface device for relay protection of the present invention is as follows: it includes a switching value input circuit, a switching value output circuit, and two CPUs, and the two CPUs respectively form two independent channels with their respective optical fiber channels, and the switch The output terminals of the quantity input circuit are respectively connected to the input ports of the two CPUs, the output terminals of the two CPUs are connected to the input terminals of the AND gate circuit, and the output terminals of the AND gate circuit are connected to the switching value output circuit; the two CPUs are equally divided into sending Part and receiving part, the sending part includes a delay judgment module, encoding and framing module and code conversion module, the receiving part includes a code inverse conversion module, deframing and decoding module; the signal input to each CPU channel passes through the delay of the sending part After being processed by the timing judgment module, encoding and framing module and code conversion module, it is sent to the photoelectric conversion module, and the signal received by the CPU from the photoelectric conversion module is processed by the code inverse conversion module, deframing and decoding module of the receiving part, and then output circuit output.

Further, the CPU is a CPLD chip with parallel processing capability.

Further, it also includes two single-chip microcomputers, the single-chip microcomputers are provided with an interface for communicating with the man-machine interface, and the two single-chip microcomputers are correspondingly connected to the two CPUs.

Further, the CPU receiving part also includes a discrimination time module and an output expansion module, and the signal is output by the output terminal after being processed by the decoding module, the discrimination time module and the output expansion module.

Further, when there is no command input to the AND gate circuit, the input of the AND gate is at high level, and when the command comes, the input changes to low level.

In the optical fiber digital interface device for relay protection of the present invention, the CPU is divided into a sending part and a receiving part, the sending part includes a delay judgment module, an encoding and framing module and a code conversion module, and the receiving part includes a code inverse conversion module, a deframing module, and a code conversion module. And decoding module, so that the command sending and receiving, encoding and decoding can be carried out at the same time, and can be realized inside the CPU, reducing the command transmission link, reducing the key components to one, making the reliability, stability and command transmission time of the interface device There has been a substantial improvement. The CPU uses a CPLD chip with parallel processing capabilities. If multiple commands arrive at the same time, the parallel processing characteristics of the CPLD can be used to process command signals in parallel without causing loss of commands.

Another relay protection optical fiber digital interface device of the present invention adopts dual channels formed by two CPUs and respective optical fiber channels, which increases reliability and stability; each CPU is divided into a sending part and a receiving part, and the sending part includes a delay Judgment module, encoding and framing module and code conversion module, the receiving part includes code conversion module, deframing and decoding module, so that the process of command detection, transmission, decoding and encoding, and output receiving are all realized inside the CPU, reducing In the command transmission link, the key components are reduced to one, which greatly improves the reliability, stability and command transmission time of the interface device. The CPU uses a CPLD chip with parallel processing capabilities. If multiple commands arrive at the same time, the parallel processing characteristics of the CPLD can be used to process command signals in parallel without causing loss of commands. The interface device of the present invention is stable and reliable in operation, and the failure rate is calculated by the quality control calculation method, which is reduced by three orders of magnitude compared with the existing interface device, thereby improving the stability of the power system operation, and adopting reliable encoding and decoding technology, The reliability of the command is increased, and the maintenance cost is reduced at the same time, which is not a small expense for the user and the manufacturer.

Description of drawings

Fig. 1 is a functional block diagram of an existing interface device;

Fig. 2 is a functional block diagram of an embodiment of the interface device of the present invention;

Fig. 3 is a functional block diagram of the dual-channel interface device of the present invention;

Fig. 4 is a functional block diagram of the CPLD of the present invention.

Detailed ways

1. Optical fiber digital interface device for relay protection (single channel)

The relay protection optical fiber digital interface device of the present invention is shown in Fig. 2, Fig. 4, and the relay protection optical fiber digital interface device of this embodiment comprises switch quantity input circuit, switch quantity output circuit, a CPU and service unit, and CPU has CPLD chip with parallel processing capability, the service unit is provided with an interface for communicating with the man-machine interface interface, the service unit is a single-chip microcomputer, the output end of the switch input circuit is connected to the input port of the CPLD chip, and the CPLD chip controls the connection switch output circuit, the CPLD chip is divided into a sending part and a receiving part. The sending part is equipped with an input delay or delay judgment module, a sampling module, an encoding and framing module, and a code conversion module; the receiving part is provided with a code inverse conversion module, synchronization module, deframing module, decoding module, discrimination time module and output expansion module.

The switching value input circuit is mainly to transform the command signal input by the external protection into the logic level inside the device through optocoupler isolation. The switching value output circuit mainly transforms the received command signal into corresponding contact output. The core of the device is the CPLD. After receiving the command signal, it passes through the input delay module and sampling module of the sending part, then encodes, frames, and then undergoes code bit conversion, and then sends it to the photoelectric conversion module to convert it into an optical signal; because CPLD It has parallel processing capability. While sending, it also converts the data received from the photoelectric module through the code inverse conversion module of the receiving part, and then deframes and decodes the command signal. sent to the command output loop. The service unit is a single-chip microcomputer. It does some initialization work when it is powered on, provides parameters for sending and receiving delays to the CPLD, and manages other affairs, but it does not participate in the transmission of commands.

The CPLD chip is also provided with a latch 1, a latch 2 and a buffer connected to the microcontroller. the

According to Figure 4, the block diagram of the CPLD chip is explained as follows:

The data marked as input into the buffer ①～⑨ are respectively:

①.1...4 command channel sending status;

②.5...8 command channel sending status;

③.1...4 command channel receiving status;

④.5...8 command channel receiving command status;

⑤. Receive alarm;

⑥. BER alarm;

⑦. Out-of-frame alarm ;

⑧. Optical path A is interrupted (optical path receiving alarm A);

⑨. Optical path B is interrupted (optical path receiving alarm B).

sending part

1) Input delay module

A delay block prevents noise from being mistaken for a "command" state. The delay module starts to work when the input command signal finds a low level. The working clock of the delay module is 64k, and the delay time is the count of clock pulses.

2) Sampling module

The clock frequency of data transmission is 64K, the data in one frame is 80 bits in total, and the transmission time is 1.25ms, so the transmission time interval between two frames is 1.25ms; therefore, the command signal needs to be sampled every 1.25ms.

3) Coding and framing module

Both encoding and framing are controlled by command mode. The first 4 commands are called group A commands, and the last 4 commands are called group B commands. In the working mode of 4 commands, it is only necessary to encode, frame and send the command signals of the commands in group A. In the working mode of 8 commands, it is necessary to Alternately carry out the process of coding, grouping and frame sending for the two groups of commands A and B. Encoding and decoding adopts 48-bit block code, which can correct errors of less than 24 bits in 48 bits and increase the reliability of transmission.

4) code conversion module

After the encoding and framing module outputs the data, that is, the clock frequency of the data shifted out by the shift register is 64khz, convert these data into 256khz signals, change data 1 into 1100, and change data 0 into 1010.

receiving part

1) Code inversion module

The CPLD receives data in the form of 1100 or 1010 from the code conversion circuit. It needs to convert 1100 into 1 and 1010 into 0. The code inverse conversion module completes such a function. the

2) Synchronization module

Synchronization is required before frame decoding. The whole process of synchronization includes two processes of search and tracking. When the device is just turned on or in a frame out-of-sync state, the synchronization header must be searched first. After the synchronization is completed, the frame can be deframed, and the synchronization must be tracked at the same time to avoid out-of-synchronization and re-enter the search state.

3) Deframing module

After the synchronization is achieved, the frame can be deframed. There are four types of frames in the data processing unit, which are group A command frames, group B command frames (corresponding to the first four commands and the last four commands respectively), record frames, and other auxiliary frames ( Set frame, request frame), the difference between frames is to add different frame identification marks when framing, the specific difference is the 8-bit data behind the synchronization header.

4) Decoding module

Command decoding is the reverse process of command encoding.

5) Discrimination time module

The function of the judgment time and the input delay is exactly the same, the only difference is that the judgment time module is the delay of the output command, and the input delay is the delay of the input command.

6) Output expansion module

Output expansion is to expand the valid state of the command (command is low level), and to process the command for the normal operation of the system.

2. Relay protection optical fiber digital interface device (dual channel)

The dual-channel relay protection optical fiber digital interface device of the present invention is shown in Figure 3, and the interface device includes a switching value input circuit, a switching value output circuit, two CPUs, and two service units, both of which are single-chip microcomputers. There is an interface for communicating with the man-machine interface. Both CPUs use CPLD chips with parallel processing capabilities. The two CPLD chips form two independent channels with their respective optical fiber channels. The output terminals of the switch input circuit are respectively connected to two CPLDs. The input port of the chip, the output ends of the two CPLD chips are connected to the input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the switching value output circuit; the two CPLD chips are equally divided into a sending part and a receiving part as shown in Figure 4 . The sending part is equipped with an input delay or delay judgment module, a sampling module, an encoding and framing module, and a pattern conversion module; the receiving part is equipped with a pattern inverse transformation module, a synchronization module, a deframing module, a decoding module, and a time discrimination module and output expansion modules.

The switching value input circuit is mainly to transform the command signal input by the external protection into the logic level inside the device through optocoupler isolation. The switching value output circuit mainly transforms the received command signal into corresponding contact output. The core of the device is the CPLD. After receiving the command signal, it passes through the input delay module of the sending part, the sampling module, then encodes, frames, and then undergoes code bit conversion, and then sends it to the photoelectric conversion module to convert it into an optical signal; because CPLD It has parallel processing capability. While sending, it also converts the data received from the photoelectric module through the code inverse conversion module of the receiving part, and then deframes and decodes the command signal. sent to the command output loop. The service unit is a single-chip microcomputer. It does some initialization work when it is powered on, provides parameters for sending and receiving delays to the CPLD, and manages other affairs, but it does not participate in the transmission of commands.

CPLD (A) and CPLD (B) and their respective fiber channels form two independent channels. The command signal received by the interface device is transmitted to CPLD (A) and CPLD (B) at the same time, they work separately, and send the command signal to the optical channel; then convert the optical signal received from the respective optical channel into a command signal, two-way After the command signal is processed by the AND gate circuit, it becomes a signal and is output by the output circuit.

In the AND gate circuit, when there is no command, the input of the AND gate is at a high level. After the command comes, the input is changed to a low level. In this way, as long as one of the two transmission channels is correctly transmitted, after passing through the AND gate circuit, The command signal can be output correctly. This way reliability is guaranteed.

The CPLD chip is also provided with a latch 1, a latch 2 and a buffer connected to the microcontroller. the

According to Figure 4, the block diagram of the CPLD chip is explained as follows:

The data marked as input into the buffer ①～⑨ are respectively:

①.1...4 command channel sending status;

②.5...8 command channel sending status;

③.1...4 command channel receiving status;

④.5...8 command channel receiving command status;

⑤. Receive alarm;

⑥. BER alarm;

⑦. Out-of-frame alarm ;

⑧. Optical path A is interrupted (optical path receiving alarm A);

⑨. Optical path B is interrupted (optical path receiving alarm B).

sending part

1) Input delay module

A delay block prevents noise from being mistaken for a "command" state. The delay module starts to work when the input command signal finds a low level. The working clock of the delay module is 64k, and the delay time is the count of clock pulses.

2) Sampling module

The clock frequency of data transmission is 64K, the data in one frame is 80 bits in total, and the transmission time is 1.25ms, so the transmission time interval between two frames is 1.25ms; therefore, the command signal needs to be sampled every 1.25ms.

3) Coding and framing module

Both encoding and framing are controlled by command mode. The first 4 commands are called group A commands, and the last 4 commands are called group B commands. In the working mode of 4 commands, it is only necessary to encode, frame and send the command signals of the commands in group A. In the working mode of 8 commands, it is necessary to Alternately carry out the process of coding, grouping and frame sending for the two groups of commands A and B. Encoding and decoding adopts 48-bit block code, which can correct errors of less than 24 bits in 48 bits and increase the reliability of transmission.

4) code conversion module

After the encoding and framing module outputs the data, that is, the clock frequency of the data shifted out by the shift register is 64khz, convert these data into 256khz signals, change data 1 into 1100, and change data 0 into 1010.

receiving part

1) Code inversion module

The CPLD receives data in the form of 1100 or 1010 from the code conversion circuit. It needs to convert 1100 into 1 and 1010 into 0. The code inverse conversion module completes such a function. the

2) Synchronization module

Synchronization is required before frame decoding. The whole process of synchronization includes two processes of search and tracking. When the device is just turned on or in a frame out-of-sync state, the synchronization header must be searched first. After the synchronization is completed, the frame can be deframed, and the synchronization must be tracked at the same time to avoid out-of-synchronization and re-enter the search state.

3) Deframing module

After the synchronization is achieved, the frame can be deframed. There are four types of frames in the data processing unit, which are group A command frames, group B command frames (corresponding to the first four commands and the last four commands respectively), record frames, and other auxiliary frames ( Set frame, request frame), the difference between frames is to add different frame identification marks when framing, the specific difference is the 8-bit data behind the synchronization header.

4) Decoding module

Command decoding is the reverse process of command encoding.

5) Discrimination time module

The function of the judgment time and the input delay is exactly the same, the only difference is that the judgment time module is the delay of the output command, and the input delay is the delay of the input command.

6) Output expansion module

Output expansion is to expand the valid state of the command (command is low level), and to process the command for the normal operation of the system.

Claims (4)

1. a relay protective optical fiber digital interface device, comprise switching value input circuit, switching value output circuit, it is characterized in that: also comprise two CPU, two CPU form two-way independent channel with optical-fibre channel separately respectively, the output of described switching value input circuit is connected into respectively the input port of two CPU, the output of two CPU is connected into AND circuit input, the output control connection switching value output circuit of AND circuit; Described two CPU are divided into transmitting portion and receiving unit, and transmitting portion comprises delay judgement module, coding and framing module and code conversion module, and receiving unit comprises pattern inverse transform module, separates frame and decoder module; Input the signal of each CPU channel after delay judgement module, coding and the framing module and code conversion resume module of transmitting portion, send to photoelectric conversion module, the signal that CPU receives from photoelectric conversion module is exported by output circuit after pattern inverse transform module, solution frame and the decoding resume module of receiving unit; Described CPU is the CPLD chip with parallel processing capability.

2. relay protective optical fiber digital interface device according to claim 1, is characterized in that: also comprise two single-chip microcomputers, single-chip microcomputer is provided with the interface being connected with man-machine interface communication, two are connected corresponding with described two CPU of single-chip microcomputer.

3. relay protective optical fiber digital interface device according to claim 1; it is characterized in that: described CPU receiving unit also comprises differentiates time module and output expansion module, and the signal of each CPU channel of described input is exported by output circuit after processing through decoder module, differentiation time module, output expansion module.

4. according to the relay protective optical fiber digital interface device described in any one in claim 1-3, it is characterized in that: when described AND circuit does not have input command, with the input of door be high level, after order is come, input changes low level into.

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