CN102096579B - Composition and structure of embedded self-adaptive fuzzy microprocessor - Google Patents
Composition and structure of embedded self-adaptive fuzzy microprocessor Download PDFInfo
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- CN102096579B CN102096579B CN 200910227187 CN200910227187A CN102096579B CN 102096579 B CN102096579 B CN 102096579B CN 200910227187 CN200910227187 CN 200910227187 CN 200910227187 A CN200910227187 A CN 200910227187A CN 102096579 B CN102096579 B CN 102096579B
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Abstract
The invention provides a circuit structure and operating method of an embedded self-adaptive fuzzy microprocessor. The microprocessor is formed by the combination of a fuzzy logic functional part and a two-valued logic function part. The circuit structure mainly comprises related function parts, such as a self-adaptive arithmetical logic operator, a general/dedicated register group, a controller, a time/counter, a Cache (or EPRON (Erasable Programmable Read Only Memory)), a program counter, a digital-to-analogue converter, a discrimination register, a comparer, a control gate and pulse source/on-off/frequency dividing circuit, and the like. The embedded self-adaptive fuzzy microprocessor can be used for carrying out addition and subtraction arithmetic operations on any R-scale data, directly carrying out logic operation on any R-scale data, and also directly carrying out addition and subtraction operations and logical operation on any analog signal.
Description
[technical field]
The present invention relates to composition and the structure of the fuzzy microprocessor of a kind of inlaid self-adaptive, and required self-adaptation arithmetic and logic unit and some basic fuzzy logic circuit, more particularly relate to adapt to the method for arbitrary carry system addition, subtraction operation.
[background technology]
Present general microprocessor, employing all be two-valued function, and outside input mostly be non-two-value coded signal, such as decimal data signal and simulating signal etc.Non-two-value coded signal need to be converted to just can be sent into microprocessor behind the two-value coded signal and process, and the two-value coded signal after microprocessor processes is converted to the signal output that meets outside need again.Like this, signal is changed repeatedly needs the time, has not only reduced the work efficiency of microprocessor, and some application problem uses two-valued function to be not easy to solve.More be in the environment of uncertain fuzzy message, to make rational judgement such as the thinking activities of the mankind in real world, two-valued function be difficult to describe with the Coping with Reality world in the object of many ambiguities.Carry out work in order to make microprocessor can imitate better the human law of thought, the functions such as more objective easy realization artificial intelligence, pattern-recognition, speech recognition and process control, just need to have new, simply method is removed Face of Challenge.Just must improve microprocessor theory and structure, the fuzzy logic technology then is a kind of preferably selection at all.
Fuzzy logic has obtained application in a lot of fields, but the development of fuzzy hardware lags behind the application of fuzzy logic far away.The development of fuzzy hardware is an important branch in the fuzzy logic research field.Development obfuscation circuit and Fuzzy function parts are to satisfy the needs of using.Fuzzy logic is the set of using infinite successive value, and the set of this infinite successive value is also referred to as continuous logic.So fuzzy logic circuit and continuous logic circuit belong to the same class logical circuit, they are without essential distinction.Can come diagnostic cast fuzzy logic circuit by the method for research continuous logic circuit like this.The fuzzy logic circuit is the another kind of functional circuit between mimic channel and digital circuit, and it has the dual nature of Analog signals and digital signal.
Utilize this dual nature of fuzzy logic circuit, adopt fuzzy logic circuit and its functional part to consist of fuzzy logic system.Both made it to have and directly to process the arbitrary carry system digital signal, can directly process the arbitrary mould analog signal again.Thereby can effectively bring into play the characteristic of fuzzy logic, to satisfy the needs of artificial intelligence, pattern-recognition, speech recognition and process control.Make the realization of artificial intelligence, pattern-recognition, speech recognition and process control become easier, easier, its performance is better, more reliable.
[summary of the invention]
Fundamental purpose of the present invention is for composition and the structure of the fuzzy microprocessor of a kind of inlaid self-adaptive are provided.A more far-reaching purpose of the present invention is the method for the adaptation arbitrary carry system addition, subtraction operation that provides, not only can be used as the foundation of electronics self-adaptation full adder, full subtracter design and many-valued full adder, full subtracter design, also can be used as the foundation of non-electronic full adder, full subtracter design, and can greatly improve design effort efficient.The fuzzy microprocessor of inlaid self-adaptive of the present invention not only can directly carry out computing and the arbitrary value logic is carried out computing any R system number, and also can directly carry out computing to the arbitrary continuation simulating signal.
The invention provides a kind of general-purpose operation method of self-adaptation full adder and a kind of general-purpose operation method of self-adaptation full subtracter.In the implementation method of self-adaptation full adder, adopt and transmit carry control signal U
C0Replace transmitting carry C
iMethod.This method is with respect to direct transmission carry C
i, this method both had been convenient to implement.In full subtracter embodiment to relevant borrow C
JiAlso be to adopt transmission borrow control signal to replace C
Ji
In the fuzzy microprocessor of inlaid self-adaptive of the present invention, adopt the exclusive data exchange register to combine with D/A, the carry C input current potential of realistic requirement is provided for self-adaptation arithmetic and logic unit (ALU).In addition, the hardware such as Output rusults employing comparer of ALU are judged.
The present invention also provides and has been used for forming the fuzzy required a series of basic fuzzy logic element circuits that are made of metal-oxide-semiconductor of microprocessor of inlaid self-adaptive, as fuzzy logic threshold gate circuit, variable window fuzzy logic threshold not gate, fuzzy logic get little gate circuit, fuzzy logic is got the basic circuits such as large gate circuit, fuzzy logic adding circuit, fuzzy logic subtraction circuit, fuzzy logic not circuit.They have had complete function system, can satisfy to consist of the needs of any indistinct usage flogic system, provide reliable guarantee for implementing the fuzzy microprocessor of inlaid self-adaptive.
Other benefits of the present invention and more far-reaching purpose are apparent for the professional and technical personnel in this field.
[description of drawings]
In order to understand better the present invention, provide the application's the building-block of logic of relevant functional part of the fuzzy microprocessor of inlaid self-adaptive and each required logic gates schematic diagram thereof.In the accompanying drawings:
Fig. 1 illustrates the structured flowchart according to the fuzzy microprocessor of a kind of inlaid self-adaptive of the present invention
Fig. 2 illustrates the building-block of logic according to a self-adaptation arithmetic and logic unit of the present invention.
Fig. 3 illustrates the building-block of logic according to a self-adaptation full adder of the present invention.
Fig. 4 illustrates the building-block of logic according to a self-adaptation full subtracter of the present invention.
Fig. 5 illustrates according to fuzzy logic threshold gate circuit theory diagrams of the present invention.
Fig. 6 illustrates according to fuzzy logic variable window threshold not circuit schematic diagram of the present invention.
Fig. 7 illustrates fuzzy logic according to the present invention and gets one of wicket circuit theory diagrams.
Fig. 8 illustrates fuzzy logic according to the present invention and gets two of wicket circuit theory diagrams.
Fig. 9 illustrates fuzzy logic according to the present invention and gets one of gate circuit theory diagrams.
Figure 10 illustrates fuzzy logic according to the present invention and gets two of gate circuit theory diagrams.
Figure 11 illustrates according to fuzzy logic adding circuit schematic diagram of the present invention.
Figure 12 illustrates according to fuzzy logic subtraction circuit schematic diagram of the present invention.
Figure 13 illustrates according to one of fuzzy logic not circuit schematic diagram of the present invention.
Figure 14 illustrates according to two of fuzzy logic not circuit schematic diagram of the present invention.
[embodiment]
The fuzzy microprocessor of inlaid self-adaptive of the present invention adopts fuzzy logic circuit and two-valued function circuit to be combined into.The parts that every any R system data-signal or simulating signal will be passed through all adopt the fuzzy logic circuit to consist of, if the parts that only have separately binary signal to pass through then adopt the two-valued function circuit to consist of.In the fuzzy microprocessor of the inlaid self-adaptive shown in Fig. 1, except self-adaptation arithmetic and logic unit ALU, threshold gate, D/A1, D/A2 and control gate 1.～3., all the other each functional parts are the two-valued function parts.
Fig. 2 is self-adaptation arithmetic and logic unit structural drawing provided by the invention.It mainly is made of self-adaptation full adder and self-adaptation full subtracter and some logical operation circuits.When the E end is high level, carry out arithmetical operation: if I
2I
1I
0During=HHH, carry out additive operation, namely F=A adds B; If I
2I
1I
0During=HHL, carry out subtraction, namely F=A subtracts B.When the E end is low level, carry out logical operation:
If I
2I
1I
0During=HHH, get macrooperation, i.e. F=A ∨ B
If I
2I
1I
0During=HHL, get large inverse, namely F=(A ∨ B) is non-
If I
2I
1I
0During=HLH, carry out minimizing operation, i.e. F=A ∧ B
If I
2I
1I
0During=HLL, get little inverse, namely F=(A ∧ B) is non-
If I
2I
1I
0During=LHH, carry out threshold operation, i.e. F=A ⊙ B
If I
2I
1I
0During=LHL, carry out the threshold inverse, namely F=(A ⊙ B) is non-
If I
2I
1I
0During=LLH, carry out the A inverse, namely F=A is non-
If I
2I
1I
0During=LLL, carry out the B inverse, namely F=B is non-
Fig. 3 is a self-adaptation full adder building-block of logic provided by the invention.Among the figure with input end A
iLevel and the carry control signal U of input
CiIn fuzzy logic threshold gate G0, compare, work as A
i=U
CiThe time, door G0 is output as maximum level, otherwise door G0 is output as minimum level.The input end of two-value and door G1 is delivered in the output of door G0, and another input of door G1 is U
Ci, to only have when two inputs of door G1 are high level, the output of door G1 just is high level.The output of door G1 divides three the tunnel to transmit, and one the tunnel delivers to two-valued function or door G2 as carry control signal U
C0Output, another road is delivered to fuzzy logic and is got wicket G12.When Ruo Dangmen G1 is output as maximum level, just allow addend B
iDeliver to fuzzy logic by door G12 and get gate G15 as entirely adding and counting S
iOutput, the carry control signal U of door G2 output this moment
C0Be high level.The high level of door G1 output is got wicket G13 with fuzzy logic after two-valued function not gate G11 negate simultaneously, door G14 blocks.This moment is except B
iIn addition, the status information of the operation of other circuit all can not be sent to the input end of a G15, not that is to say to affect operation result, and which kind of state comparator circuit G6 this moment (adopting the fuzzy logic comparator circuit) is output as and can have influence on a maximum level of G2 output.Thereby realized the full adder operational method 1. as (A
i+ C
I-1) greater than R-1, i.e. (A
i+ C
I-1During)=radix R, entirely add and S
i=B
i, produce carry C
i=1.
Carry control signal U when input
CiDuring for high level, fuzzy logic is got wicket G3 and is exported 1 level, is equivalent to C
I-1=1; Carry control signal U when input
CiDuring for low level, fuzzy logic is got wicket G3 and is exported 0 level, is equivalent to C
I-1=0.Fuzzy logic adding circuit G5 and addend A are delivered in the output of door G3
iAddition is namely finished (A in door G5
i+ C
I-1) computing.The operation result of the output of door G5 is delivered to respectively fuzzy logic comparator circuit G6, fuzzy logic adding circuit G7 and fuzzy logic subtraction circuit G9.Addend B
iBy delivering to fuzzy logic comparator circuit G6 and fuzzy logic adding circuit G8 after the fuzzy logic not gate G4 negate.(A
i+ C
I-1) and B
iRadix-minus-one complement in door G6, compare.
As (A
i+ C
I-1) be less than or equal to B
iRadix-minus-one complement the time, door G6 output minimum level, door G6 output is connected respectively to two-valued function or door G2, two-valued function not gate G10 and fuzzy logic and gets wicket G14.Output door capable of being opened G13 after door G10 negate of door G6.To in fuzzy logic adding circuit G7, finish (A
i+ C
I-1)+B
iOperation result as entirely adding and S
iExport through door G15 again by door G13.This moment, door G1 output also was minimum level, so the carry control signal U of door G2 output
C0Be low level, the expression no-carry.Thereby realized the full adder operational method 2. as (A
i+ C
I-1) be less than or equal to B
iRadix-minus-one complement the time, entirely add and S
i=(A
i+ C
I-1)+B
i, this moment no-carry C
i=0.
As (A
i+ C
I-1) greater than B
iRadix-minus-one complement the time, a door G6 then exports high level, door capable of being opened G14 closes a G13 after anti-phase by door G10 simultaneously, the low level of door G1 output is closed door G12.Meanwhile door G8 finishes B
iRadix-minus-one complement add 1, make it to become B
iComplement code, in door G9, finish (A
i+ C
I-1)-B
I mendsComputing, and with its result as entirely adding and S
iExport through door G15 again by door G14.Because door G6 is output as high level, so the carry control signal U of door G2 output
C0Also be high level, expression has carry.Thereby realized the full adder operational method 3. as (A
i+ C
I-1) greater than B
iRadix-minus-one complement the time, entirely add and S=(A
i+ C
I-1)-B
Mend, carry C
i=1.Actual parallel the carrying out of aforesaid operations.
Fig. 4 is a self-adaptation full subtracter building-block of logic provided by the invention.Among the figure with input end A
iLevel and 0 level compare in fuzzy logic threshold gate G16, work as A
i=0 o'clock, door G16 was output as maximum level, otherwise door G16 is output as minimum level.The input end of two-value and door G17 is delivered in the output of door G16, and another input of door G17 is U
Ji, when two inputs just thinking a G17 were high level, the output of door G17 just was high level.The output of door G17 divides three the tunnel to transmit, and one the tunnel delivers to two-valued function or door G18 as borrow control signal C
JoOutput, another road is delivered to fuzzy logic and is got wicket G28.When Ruo Dangmen G17 is output as maximum level, just allow the subtrahend B that transmits through door G20
iRadix-minus-one complement deliver to fuzzy logic by door G28 and get gate G31 as one's own department or unit difference D
iOutput, the borrow control signal C of door G18 output this moment
JoBe high level.The high level of door G17 output is got wicket G29 with fuzzy logic after two-valued function not gate G27 negate simultaneously, door G30 blocks.This moment is except B
iRadix-minus-one complement beyond, the operation result of other circuit all can not be delivered to the input end of a G31, not that is to say to affect operation result, and which kind of state comparator circuit G22 this moment (adopting the fuzzy logic comparator circuit) is output as and can have influence on a maximum level of G18 output.Thereby 1. that has realized the full subtracter operational method works as A
i=0, C
Ji-1=1 o'clock, one's own department or unit difference D
i=B
iRadix-minus-one complement, need to high-order borrow, C
Ji=1, i.e. borrow control signal U
JoBe high level.
Borrow control signal U when input
JiDuring for high level, fuzzy logic is got wicket G19 and is exported 1 level, is equivalent to C
Ji-1=1; Carry control signal U when input
JiDuring for low level, fuzzy logic is got wicket G19 and is exported 0 level, is equivalent to C
Ji-1=0.Fuzzy logic subtraction circuit G21 is delivered in the output of door G19, finishes (A in door G21
i-C
Ji-1) computing.The operation result of the output of door G21 is delivered to respectively fuzzy logic comparator circuit G22, fuzzy logic subtraction circuit G23 and fuzzy logic adding circuit G25.(A
i-C
Ji-1) operation result and B
iIn door G22, compare.
As (A
i-C
Ji-1) more than or equal to B
iThe time, door G22 output maximum level.Door G22 output is connected respectively to two-valued function not gate G26 and fuzzy logic is got wicket G29.The output door capable of being opened G29 of door G22.To in fuzzy logic subtraction circuit G23, finish (A
i-C
Ji-1)-B
iOperation result as one's own department or unit difference D
iExport through door G31 again by door G29.Door G17 output this moment and door G26 output are minimum level, so the borrow control signal C of door G18 output
JoBe low level, expression is without borrow.Thereby realized the full subtracter operational method 2. as (A
i-C
Ji-1) more than or equal to B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)-B
i, C
Ji=0, i.e. borrow output control signal U
JoIt is 0 level.
As (A
i-C
Ji-1) less than B
iThe time, door G22 then exports minimum level, closes a G29, and simultaneously by the anti-phase door capable of being opened G30 of door G26, the low level of door G17 output is closed door G28.Subtrahend B
iBy delivering to fuzzy logic adding circuit G24 after the fuzzy logic not circuit door G20 negate, G24 finishes B at door
iRadix-minus-one complement add 1, make it to become B
iComplement code, in fuzzy logic adding circuit G25, finish (A
i-C
Ji-1)+B
I mendsComputing, and with its result as one's own department or unit difference D
iExport through door G31 again by door G30.Because door G26 is output as high level, so the borrow control signal U of door G18 output
JoAlso be high level, expression has borrow.Thereby realized the full subtracter operational method 3. as (A
i-C
Ji-1) less than B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)+B
Mend, C
Ji=1, i.e. borrow control output signal U processed
JoBe high level.Aforesaid operations is parallel to carry out.
Fuzzy logic threshold gate circuit shown in Fig. 5, it by 6 metal-oxide-semiconductor M1 pipe～M6 manage, a triode T and a diode D consist of.Wherein M1 pipe, M2 pipe consist of input circuit, and the M3 pipe is its load.Triode, M1 pipe～M3 pipe and diode consist of output circuit.Diode plays the effect of resistance, and back resistance is very large.Threshold gate has V
AAnd V
BTwo input ends, VO are output terminal.As two input end level V
A=V
BThe time, M1 pipe, all cut-offs of M2 pipe, triode T cut-off, M5 manages conducting, and M6 manages cut-off, exports VO ≈ V this moment
DDAs two input end level V
A≠ V
BThe time, M1 manages, M2 manages just a conducting in two pipes, another cut-off, and triode and M4 manage new conducting, and M5 manages cut-off, and M6 manages conducting, exports VO ≈ 0 current potential this moment.Thereby realized the threshold logic computing.
Shown in Fig. 6 is fuzzy logic variable window threshold not circuit.It by 6 metal-oxide-semiconductor M1 pipe～M6 manage, a triode T forms, M1 pipe, M2 pipe and M5 pipe form input circuit, M3 pipe, M4 pipe, M6 pipe and transistor T form active load.It has V
A, V
B, V
CThree input ends, a VO output terminal.As two input end level V wherein
A=V
BThe time, export VO ≈ 0 current potential this moment.As two input end level V wherein
A≠ V
BThe time, export VO ≈ V this moment
DDCurrent potential.Thereby realized the computing of variable window threshold NOT logic, V
CBe window width.
Shown in Fig. 7 is that five input end fuzzy logics are got wicket.Circuit structure is simple, and fan-in factor is unrestricted, and this figure circuit can be realized V
0=V
A∧ V
B∧ V
C∧ V
D∧ V
EMinimizing operation.Shown in Fig. 8 is that three input ends are got little gate circuit.N channel enhancement load pipe M4 pipe, M5 pipe and M6 pipe are connected among the figure, and P-channel enhancement type driving tube M1 pipe, M2 pipe and M3 pipe are in parallel.V
A, V
BAnd V
CBe input end, V
0Be output terminal.If work as V
A=V
B=V
C, and all rise to continuously gradually the circuit ceiling voltage from 0V, and M1 pipe, M2 pipe and M3 pipe tend to cut-off gradually from saturation conduction, and M4 pipe, M5 pipe and M6 pipe are then gradually from cut-off trend saturation conduction, output V
0Also follow input end and rise to continuously gradually the circuit ceiling voltage from 0V.When a certain end input voltage is lower than other end input voltages, output V
0It then is the minimum input voltage in the input end.Realized V
0=V
A∧ V
B∧ V
CMinimizing operation.
Shown in Fig. 9 is that fuzzy logic is got one of large gate circuit, and it has four-input terminal.N channel enhancement load pipe M1 pipe～M4 pipe is in parallel among the figure, and P-channel enhancement type driving tube M5 pipe～M8 pipe is connected.V
A, V
B, V
CAnd V
DBe input end, V
0Be output terminal.If work as V
A=V
B=V
C=V
D, and applied signal voltage all rises to supply voltage value gradually continuously from 0V, and M1 pipe～M4 pipe tends to saturation conduction gradually from cut-off, and M5 pipe～M8 pipe then tends to end output voltage V from saturation conduction gradually
0Also follow applied signal voltage and rise to continuously gradually supply voltage value from 0V.When a certain end applied signal voltage is higher than other end applied signal voltages, output V
0Then equal the highest input signal voltage in the input end.Thereby realized V
0=V
A∨ V
B∨ V
C∨ V
DGet macrooperation.What Figure 10 showed is to get two of large gate circuit, and it has two input ends, can realize V
0=V
A∨ V.
Shown in Figure 11 is adding circuit.M1 pipe～M4 pipe consists of difference channel.M6 pipe, M7 pipe and resistance R 1, R2 consist of input circuit, require M6 pipe and M7 pipe two pipe parameters symmetrical, R1=R2, and its resistance is less.V
AAnd V
BBe the adding circuit input end.The M5 pipe is efferent duct, V
0Be output terminal.M8 pipe, M9 pipe and diode D1, D2 all play resistance.This adding circuit can be realized V
0=V
A+ V
B
Shown in Figure 12 is subtraction circuit.M1 pipe～M4 pipe consists of difference channel.M6 pipe and M7 pipe consist of V
AInput circuit, M8 pipe, M9 pipe consist of V
BInput circuit.The M5 pipe is efferent duct, V
0Be output terminal.M6 pipe～M9 pipe and diode D1, D2 all play resistance.This circuit can be realized V
0=V
A-V
B
Shown in Figure 13 is one of fuzzy logic not circuit.This circuit is taked the method for " cutting bent cut-off ".If power supply is V
DD, as input end signal voltage V
AChange to V from the continuous linearity of 0V
DDThe time, then can be divided into two sections from M1 pipe and M4 pipe to the variation of the output signal voltage of pipe, one section from V
DDChange to continuously V
DDThe/2nd, rectilinearity changes section, and meets V
AThe relation of negate, another section is from V
DD/ 2 beginnings then are the curvilinear motion sections, and it is not from V
DD/ 2 linearities change to 0V, but from V
DD/ 2 non-linearly change to a certain magnitude of voltage, and this section does not meet V
AThe relation of negate; Applied signal voltage remains unchanged, if also can be divided into two sections from M2 pipe and M5 pipe to the variation of managing output signal voltage, one section changes to V from a certain magnitude of voltage
DDThe/2nd, curve variation section, this section does not meet V
AThe relation of negate, but from V
DDIt then is straight-line segment that/2 beginning linearities change to 0V, and this section meets V
AThe relation of negate.M3 pipe and M6 pipe are exactly that these two curves to pipe are partly clipped to the effect of pipe, and both rectilinearity are partly combined.Thereby realize V
0=V
AInverse.
Shown in Figure 14 is two of fuzzy logic not circuit.It is to realize on subtraction circuit basis shown in Figure 13, with the V of subtraction circuit
AInput end is connected to power supply V
DD, with its V
BInput end changes V into
AInput end has just become not circuit.Can realize V
0=V
AInverse.
Embodiment provided by the invention exemplaryly is not construed as limiting the present invention.As what propose in claims, all alternative all are comprised in the category of the present invention.
Claims (10)
1. an inlaid self-adaptive blurs microprocessor, it is characterized in that:
The composition of the fuzzy microprocessor of this inlaid self-adaptive, it is combined into by fuzzy logic functional part and two-valued function functional part, comprise: 1 or multidigit self-adaptation arithmetic and logic unit ALU, controller, programmable counter PC, general purpose register set, the special register group, timer conter, digital to analog converter D/A1 and D/A2, control gate, differentiate register RF1 and RF2, comparer, impulse source start and stop frequency dividing circuit, cache memory Cache or EPR0M, address bus AB, data bus DB, control bus CB functional part, the exclusive data exchange register will be delivered to D/A1 respectively and D/A2 changes from the binary data of Cache or EPROM, 1. the output of D/A1 deliver to the A input end of ALU through control gate, another road input of the A end of ALU is from control gate output 2., control gate input end is 2. delivered in the input of the outside A end of processor, the B input end of ALU is directly delivered in the B end input of processor outside, the carry C input end of ALU is directly delivered in the output of D/A2, for ALU provides different carry C level, 3. the output one tunnel of ALU deliver to the Fo output terminal of processor through control gate, an input end of comparer is directly delivered on another road of ALU output, the data of sending here with differentiation register RF1 compare in comparer, the comparative result of comparer is exported one tunnel Zo output terminal of delivering to processor, and another Lu Zejing differentiates register RF2 and delivers in the general-purpose register;
The fuzzy microprocessor of this inlaid self-adaptive adapts to the method for any R system additive operation, comprising: 1. as (A
i+ C
I-1) greater than R-1, i.e. (A
i+ C
I-1During)=radix R, one's own department or unit and number S
i=B
i, C
i=1; 2. as (A
i+ C
I-1) be less than or equal to B
iRadix-minus-one complement the time, one's own department or unit and the number S
i=(A
i+ C
I-1)+B
i, C
i=0; 3. as (A
i+ C
I-1) greater than B
iRadix-minus-one complement the time, one's own department or unit and the number S
i=(A
i+ C
I-1)-B
I mends, C
i=1, wherein R is radix, A
iAnd B
iBe respectively summand and addend, B
I mendsBe B
iComplement code, C
I-1Be carry, the S from low level
iBe one's own department or unit and number, C
iFor producing the carry to a high position, its implementation, both voltage available type circuit realizations, also available current type circuit realization, also available non-electronic technology realization;
The fuzzy microprocessor of this inlaid self-adaptive adapts to the method for any R system subtraction, comprising: 1. work as A
i=0, C
Ji-1=1 o'clock, one's own department or unit difference D
i=R-1-B
i, i.e. D
i=B
iRadix-minus-one complement, C
Ji=1; 2. as (A
i-C
Ji-1) more than or equal to B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)-B
i, C
Ji=0; 3. as (A
i-C
Ji-1) less than B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)+B
I mends, C
Ji=1; Wherein R is radix, A
iAnd B
iBe respectively minuend and subtrahend, B
I mendsBe B
iComplement code, C
Ji-1Be borrow, the D from low level
iBe one's own department or unit difference, C
JiBe the borrow to a high position, implementation method, voltage available type circuit realizes that also available current type circuit is realized, also available non-electronic technology realizes;
The structure of self-adaptation arithmetic and logic unit ALU: get gate G32, door G52, door G53 and door G56 by self-adaptation full adder Q1, self-adaptation full subtracter Q2, fuzzy logic, fuzzy logic is got wicket G33 and door G40～door G51, fuzzy logic threshold gate G34, fuzzy logic threshold not gate G35, fuzzy logic not gate G54, two-valued function not gate G36～door G39, two-valued function or door G55 circuit consist of U
CiBe carry and borrow control input end, C
I-1Be carry, borrow value input, A
iAnd B
iBe respectively two any R system numeric datas or two arbitrary value logical data input ends, the E end is Enable Pin, and when the E end was high level, the self-adaptation arithmetic and logic unit carried out the arithmetic plus and minus calculation, when E holds as low level, then carries out logical operation, I
2I
1I
0Assembled state determines the calculation function of self-adaptation arithmetic and logic unit, U
C0Be carry, borrow control output end, F
oBe the operation result output terminal, ALU can expand;
Each parts annexation to each other among the self-adaptation arithmetic and logic unit ALU: carry, borrow control inputs U
CiEnd connects the U of full adder Q1
CiThe U of end and full subtracter Q2
JiEnd, carry, borrow numerical value input C
I-1End connects the C of full adder Q1
I-1The C of end and full subtracter Q2
Ji-1End, A
iAnd B
iEnd connects respectively A, B end and A, the B end of full subtracter Q2 and the input end of door G32～door G35 door of full adder Q1, A
iAlso the input end with door G50 links to each other, B
iAlso the input end with door G51 links to each other, the U of Q1
C0Output terminal is connected to the input end of a G40, the S of Q1
iOutput terminal is connected to the input end of a G41, the U of Q2
J0Output terminal is connected to the input end of a G42, the D of Q2
iOutput terminal is connected to the input end of a G43, the output of door G32 is connected to input end of a G44 and the input end of door G48, the output of door G33 is connected to input end of a G45 and the input end of door G49, the output of door G34 is connected to the input end of a G46, the output of door G35 is connected to the input end of a G47, I
2End is connected to input and the input of door G40～door G45 and the input of door G48, door G51 of a G36, I
1End is connected to input and the input of door G40～door G44 and the input of door G46～door G48 of a G37, I
0End is connected to input and the door G40 of a G38, door G41, door G44, door G45, the input that door G46 and door G50 get wicket, the output of door G36 is connected to a G46, door G47, door G50, the input that door G51 gets wicket, the output of door G37 is connected to a G45, door G49, door G50, the input that door G51 gets wicket, the output of door G38 is connected to a G42, door G43, door G47, door G48, door G49, the input that door G51 gets wicket, the E end is connected to the input of a G39～each gate circuit of door G43, the output of door G39 is connected to a G44～door G51 and respectively gets the input of wicket, the output of door G44～door G47 is connected respectively to each input end of a G52, the output of door G48～door G51 is connected respectively to each input end of a G53, the input that a G54 is linked in the output of door G53, two input ends of a G55 are linked respectively in the output of the output of door G40 and door G42, and door G55 is output as carry and borrow control output end U
C0, door G41, door G43, door G52 and each output of door G54 are connected respectively to each input end of a G56, and a door G56 is output as operation result F
oOutput terminal;
The structure of self-adaptation full adder Q1: A
i, B
iBe the input end of two any R system addends, U
CiBe carry control signal input end, C
I-1Be the carry value input; S
iBe the output terminal of one's own department or unit and number, U
C0Be carry control signal output terminal; Wherein door G0 is the fuzzy logic threshold gate, door G3, door G12, door G13 and door G14 are fuzzy logic and get wicket, door G4 is the fuzzy logic not gate, door G5, door G7 and door G8 are the fuzzy logic adding circuit, and door G6 is the fuzzy logic comparator circuit, and door G9 is the fuzzy logic subtraction circuit, door G15 then gets the gate for fuzzy logic, door G1 then is two-valued function and door, and door G2 then is two-valued function or door, and door G10 and door G11 are the two-valued function not gate;
Each parts annexation to each other: A among the self-adaptation full adder Q1
iEnd is input end of connection door G0 and the input end of door G5 respectively, B
iEnd is input end of connection door G4, door G7 and the input end of door G12 respectively, U
CiEnd is the input end of input end and the door G3 of another input end of connection door G0 and door G1 respectively, carry C
I-1Another input end of end difference connection door G3 and the input end of door G8, another input end of the output connection door G1 of door G0, the output of door G1 is the input end of input end of connection door G2 and door G11 input end and door G12 respectively, the output of door G3 is connected to the input end of a G5, the output of door G5 is connection door G6 and the input end of door G7 with door G9 respectively, the input end of door G7 output connection door G13, another input end of the output difference connection door G6 of door G4 and the input end of door G8, another input end of the output connection door G9 of door G8, the input end of the output connection door G14 of door G9, the input end of door G6 output difference connection door G2 and door G10 and door G14, the input end of the output connection door G13 of door G10, the output difference connection door G13 of door G11 and the input end of door G14, door G12, the output of door G13 and door G14 is three input ends of connection door G15 respectively, and door G15 is output as and entirely adds and S
i, door G2 output U
C0As the control signal to high-order carry;
The structure of self-adaptation full subtracter Q2: A wherein
i, B
iBe the input end of any R system minuend and subtrahend, U
JiBe borrow control signal input end, C
Ji-1Be the borrow value input; D
iBe the output terminal of one's own department or unit difference, U
JoBe borrow control signal output terminal; Wherein door G16 is the fuzzy logic threshold gate, door G19, door G28, door G29 and door G30 are fuzzy logic and get wicket, door G20 is the fuzzy logic not gate, door G21, door G23 are the fuzzy logic subtraction circuit, and door G22 is the fuzzy logic comparator circuit, and door G24 and door G25 are the fuzzy logic adding circuit, door G31 then gets the gate for fuzzy logic, door G17 then is two-valued function and door, and door G18 then is two-valued function or door, and door G26 and door G27 are the two-valued function not gate;
Each parts annexation to each other: A among the self-adaptation full subtracter Q2
iEnd is input end of connection door G16 and the input end of door G21 respectively, B
iEnd is input end of connection door G20, door G22 and the input end of door G23 respectively, C
JiEnd is the input end of input end and the door G19 of connection door G17 respectively, borrow C
Ji-1Another input end of end difference connection door G19 and the input end of door G24, another input end grounding of door G16, another input end of the output connection door G17 of door G16, the output of door G17 is the input end of input end of connection door G18 and door G27 input end and door G28 respectively, the output of door G19 is connected to the input end of a G21, the output of door G21 is connection door G22 and the input end of door G23 with door G25 respectively, the input end of the output connection door G29 of door G23, another input end of the output difference connection door G24 of door G20 and the input end of door G28, another input end of the output connection door G25 of door G24, the input end of the output connection door G30 of door G25, the input end of door G22 output difference connection door G26 and door G29, the input end of the output connection door G18 of door G26 and door G30, the output difference connection door G29 of door G27 and the input end of door G30, door G28, the output of door G29 and door G30 is three input ends of connection door G31 respectively, and door G31 is output as one's own department or unit difference D
i, door G18 output U
JoAs the control signal to high-order borrow.
2. the fuzzy microprocessor of inlaid self-adaptive according to claim 1 is characterized in that described self-adaptation arithmetic and logic unit ALU can expand, and utilizes its U
C0End and output terminal F
oCan be extended to multidigit ALU.
3. inlaid self-adaptive according to claim 1 blurs microprocessor, it is characterized in that, the any R system of described adaptation additive operation method, its implementation voltage available type circuit realize that the self-adaptation full adder Q1 that adopts the voltage-type circuit to consist of realizes, its concrete grammar is to adopt the level of R different height to represent 0 to any radix R, 1,2 ..., (R-1) R numeral is with output carry control signal U
C0Replace carry C
i, when producing to high-order carry, represent U with the maximum level in the system
C0, represent U with minimum 0 level in the system when not producing carry
C0, i.e. C
i=1 o'clock, U
C0Be high level; C
i=0 o'clock, U
C0Be 0 level, with U
C0Deliver to high-order input carry control end U
Ci, i.e. U
Ci=U
C0, use U
CiThe carry C of control inputs
I-1Be 1 to be 0 still, work as U
CiDuring for high level, C
I-1=1, work as U
CiDuring for low level, C
I-1=0, so the numerical operation of self-adaptation full adder just becomes with level and represents that numerical value carries out computing, that is: 1. as expression A
iLevel=U
CiLevel, and when being maximum level entirely adds and counts S
i=B
i, and produce to high-order carry, this moment U
C0Level then is the maximum level in the system; 2. as (A
i+ C
I-1) be less than or equal to B
iRadix-minus-one complement the time, entirely add and count S
i=(A
i+ C
I-1)+B
i, no-carry, at this moment U
C0Level is 0 level in the system; 3. as (A
i+ C
I-1) greater than B
iRadix-minus-one complement the time, entirely add and count S
i=(A
i+ C
I-1)-B
Mend, produce to high-order carry, at this moment U
C0Level is the maximum level in the system.
4. inlaid self-adaptive according to claim 1 blurs microprocessor, it is characterized in that, the any R system of described adaptation subtraction method, its implementation voltage available type circuit realize that the self-adaptation full subtracter Q2 that adopts the voltage-type circuit to consist of realizes, its concrete grammar is to adopt the level of R different height to represent 0 to any radix R, 1,2 ..., (R-1) R numeral is with output borrow control signal U
JoReplace C
Ji, when need represent U with the maximum level in the system during to high-order borrow
Jo, do not represent U with minimum 0 level in the system when having borrow
Jo, i.e. C
i=1 o'clock, U
JoBe maximum level; C
i=0 o'clock, U
JoBe 0 level, with U
JoDeliver to high-order borrow input control end U
Ji, i.e. U
Ji=U
Jo, use U
JiThe borrow C of control inputs
Ji-iBe 1 to be 0 still, work as U
JiDuring for high level, C
Ji-1=1, work as U
JiDuring for low level, C
Ji-1=0, so the numerical operation of self-adaptation full subtracter just becomes with level and represents that numerical value carries out computing, that is: 1. as expression A
iLevel=0 level, U
JiDuring=maximum level, one's own department or unit difference D
i=R-1-B
i, need to high-order borrow, at this moment U
JoLevel then is the maximum level in the system; 2. as (A
i-C
Ji-1) more than or equal to B
iThe time, one's own department or unit difference D
i=(A
i-C
I-1)-B
i, without borrow, this moment U
JoLevel is the minimum level in the system; 3. as (A
i-C
Ji-1) less than B
iThe time, one's own department or unit difference D
i=(A
i-C
Ji-1)+B
Mend, need to high-order borrow, at this moment U
JoLevel is maximum level in the system.
5. the fuzzy microprocessor of inlaid self-adaptive according to claim 1 is characterized in that, structure and the connection of described fuzzy logic threshold gate circuit, and it has V
A, V
BTwo input ends, a V
0Output terminal, it is made of 6 metal-oxide-semiconductor M1 pipe～M6 pipe and 1 transistor T and 1 diode D, and wherein M1 pipe, M2 pipe, M4 pipe, M6 pipe are the NMOS pipe, and it is that PMOS manages that M3 pipe, M6 manage, and the source S of M1 tube grid G and M2 pipe links together as the V of threshold gate
AInput end, the source S of the grid G of M2 pipe and M1 pipe is connected together as the V of threshold gate
BInput end, M1 pipe drain electrode d, M2 pipe drain electrode d and the source S of M3 pipe and the base stage of triode link together, the grid G of M3 pipe and drain electrode d, the emitter of triode and the drain electrode d of M5 pipe are connected to positive source, the grid G of the grid G of the collector of triode and M4 pipe, drain electrode and M5 pipe links together, the grid G of the source S of M4 pipe and diode cathode and M6 pipe links together, the positive pole of diode is connected source S and is all connected earth potential with M6, the drain electrode d of the source S of M5 pipe and M6 pipe links together as V
0Output terminal;
If the connection of M1 tube grid G and M2 pipe between the source S in the threshold gate disconnected, M1 tube grid G is separately as the V of threshold gate
AInput end, the source S of M2 pipe are separately as the V of threshold gate window voltage
CInput end, V
BInput end remains unchanged, and other parts of circuit also remain unchanged, and this just becomes the variable window threshold gate;
If keep the connection of input circuit M1 pipe～M3 pipe of three input end variable window threshold gates constant, change its output circuit into active load, be that M4 pipe～M6 pipe and transistor T form active load, M1 pipe, the drain electrode d of M2 pipe and the source S of M3 pipe and the grid G of M4 pipe and the base stage of transistor T link together, and the emitter of M4 pipe drain electrode d and transistor T all meets power supply V
DD, the grid G of the drain electrode d of the source S of M4 pipe, M5 pipe and grid G, M6 pipe links together, the equal ground connection of source S of M5 pipe, M6 pipe, and the drain electrode d of M6 pipe and the collector of transistor T link together as V
0Output terminal has so just become variable window threshold not gate;
As long as the V with three input end variable window threshold not gates
CInput end and V
AInput end links together as V
AInput end, other parts of circuit remain unchanged, and have so just become V
A, V
BTwo input end threshold not gates.
6. inlaid self-adaptive according to claim 1 blurs microprocessor, it is characterized in that, described fuzzy logic is got structure and the connection of little gate circuit, fuzzy logic is got one of little gate circuit, be made of 7 metal-oxide-semiconductor M1 pipe～M7 pipes, wherein M1 pipe～M6 pipe is the PMOS pipe, and the M7 pipe is the NMOS pipe, M1 pipe～M5 pipe is five input pipes, and their grid G is respectively as V
A, V
B, V
C, V
DAnd V
EInput end, the equal earthing potential of source S of their source S and M6 pipe, their drain electrode d and M6 tube grid G, M7 tube grid G link together, and M6 pipe and M7 pipe consist of the output stage of getting wicket, and the drain electrode d of M7 pipe meets power supply V
DD, the drain electrode d of the source S of M7 pipe and M6 pipe links together as V
0Output terminal, it is unrestricted that this gets wicket input pipe quantity, and namely fan-in factor is unrestricted;
Fuzzy logic is got two of little gate circuit, and it is made of 6 metal-oxide-semiconductor M1 pipe～M6 pipes, and wherein M1 pipe～M3 pipe is the PMOS pipe, and M4 pipe～M6 pipe is the NMOS pipe, and the grid G of the grid G of M1 pipe and M4 pipe links together as V
AInput end, the grid G of the grid G of M2 pipe and M5 pipe links together as V
BInput end, the grid G of the grid G of M3 pipe and M6 pipe links together as V
cInput end, the equal ground connection of source S of M1 pipe, M2 pipe and M3 pipe, M1 pipe, M2 pipe and the drain electrode d of M3 pipe and the source S of M6 pipe link together as V
0Output terminal, the drain electrode d of M6 pipe is connected with the source S of M5 pipe, and the drain electrode d of M5 pipe is connected with the source S of M4 pipe, and the drain electrode d of M4 pipe connects power supply V
DD
7. inlaid self-adaptive according to claim 1 blurs microprocessor, it is characterized in that, described fuzzy logic is got structure and the connection of large gate circuit, fuzzy logic is got one of large gate circuit, it is made of 8 metal-oxide-semiconductor M1 pipe～M8 pipes, wherein M1 pipe～M4 pipe is the NMOS pipe, and M5 pipe～M8 pipe is the PMOS pipe, and the grid G of the grid G of M1 pipe and M5 pipe links together as V
AInput end, the grid G of the grid G of M2 pipe and M6 pipe links together as V
BInput end, the grid G of the grid G of M3 pipe and M7 pipe links together as V
CInput end, the grid G of the grid G of M4 pipe and M8 pipe links together as V
DInput end, the drain electrode d of M1 pipe～M4 pipe all meets power supply V
DD, the source S of M1 pipe～M4 pipe and the drain electrode d of M5 pipe link together as the V that gets the gate
0Output terminal, the source S of M5 pipe is connected with the drain electrode d of M6 pipe, the source S of M6 pipe is connected with the drain electrode d of M7 pipe, the source S of M7 pipe is connected with the drain electrode d of M8 pipe, the source S earthing potential of M8 pipe, and fuzzy logic is got two of large gate circuit, it is made of 4 metal-oxide-semiconductors of M1 pipe～M4 pipe, wherein M1 pipe～M2 pipe is the PMOS pipe, and M3 pipe～M4 pipe links together as V for NMOS pipe, M2 pipe, the grid G of M4 pipe and the source S of M1 pipe
AInput end, M1 pipe, the grid G of M3 pipe and the source S of M2 pipe link together as V
BInput end, the source S of the drain electrode d of M1 pipe, M2 pipe and M3 pipe, M4 pipe links together as the V that gets the gate
0Output terminal, the drain electrode d of M3 pipe, M4 pipe all meets power supply V
DD
8. inlaid self-adaptive according to claim 1 blurs microprocessor, it is characterized in that, the structure of described fuzzy logic adder circuit and connection, it is managed by 9 metal-oxide-semiconductor M1 pipe～M9,2 diode D1, D2 and 2 resistance R 1, R2 consists of, wherein M1 manages, the M2 pipe, M7 pipe～M9 pipe is the NMOS pipe, M3 pipe～M6 pipe is the PMOS pipe, form difference channel by M1 pipe～M4 pipe, the source S of the source S of M1 pipe and M2 pipe is connected with the negative pole of diode D1, the plus earth of diode D1, the grid g of the drain electrode d of M1 pipe and the source S of M3 pipe and PMOS pipe M5 links together, the M3 pipe, the drain electrode d of the grid g of M4 pipe and the source S of M4 pipe and M2 pipe links together, and the drain electrode d of M3 pipe～M5 pipe all meets power supply V
DD, M6 pipe drain electrode d links to each other as V with substrate b
AInput end, the drain electrode d of M7 pipe links to each other as V with substrate b
BInput end, the grid G of M6 pipe meets power supply V
DDThe grid G ground connection of M7 pipe, the source S of M6 pipe, M7 pipe is connected with the grid G of difference channel M1 pipe by resistance R 1, R2 respectively, the drain electrode d of the M2 tube grid G of difference channel and the grid G of M8 pipe, drain electrode d and substrate b and M9 pipe links together, the grid G of M9 pipe and source S and substrate b ground connection, the source S of the source S of M8 pipe and M5 pipe and the negative pole of diode D2 link together as V
0Output terminal, the plus earth of diode D2.
9. inlaid self-adaptive according to claim 1 blurs microprocessor, it is characterized in that, the structure of described fuzzy logic subtracter and connection, it is managed by 9 metal-oxide-semiconductor M1 pipe～M9,2 diode D1, D2 consists of, wherein M1 manages, the M2 pipe is the NMOS pipe, M3 pipe～M9 is the PMOS pipe, form difference channel by M1 pipe～M4 pipe, the source S of the source S of M1 pipe and M2 pipe is connected with the negative pole of diode D1, the plus earth of diode D1, the grid g of the drain electrode d of M1 pipe and the source S of M3 pipe and PMOS pipe M5 links together, the M3 pipe, the drain electrode d of the grid g of M4 pipe and the source S of M4 pipe and M2 pipe links together, and the drain electrode d of M3 pipe～M5 pipe all meets power supply V
DD, M6 pipe, M7 tube grid G all meet power supply V
DD, the drain electrode d of M6 pipe links to each other as V with substrate b
AInput end, the drain electrode d of the source S of M6 pipe and M7 pipe and substrate b are connected with the grid G of M1 pipe, the source S ground connection of M7 pipe, the drain electrode d of the grid G of the grid G of M2 pipe and M8 pipe, drain electrode d and substrate b and M9 pipe links together, and the grid G of M9 pipe and source S and substrate b link together as V
BInput end, the source S of the source S of M8 pipe and M5 pipe and the negative pole of diode D2 link together as V
0Output terminal.
10. inlaid self-adaptive according to claim 1 blurs microprocessor, it is characterized in that, the structure of described fuzzy logic not circuit and connection, one of fuzzy logic not circuit, consisted of by 6 metal-oxide-semiconductors of M1 pipe～M6 pipe, wherein M1 pipe～M4 pipe is the PMOS pipe, and M5 pipe, M6 pipe are the NMOS pipe, and the grid G of M1 pipe, M3 pipe, M5 pipe and M6 pipe links together as not gate V
AInput end, the drain electrode d of M1 pipe, M2 pipe all connects positive source, the drain electrode d of the source S of M1 pipe and M4 pipe and the source S of M6 pipe link together, the equal earthing potential of the source S of the grid G of M4 pipe and source S and M5 pipe, the drain electrode d of the grid G of M2 pipe and source S, M3 pipe and the drain electrode d of M5 pipe link together, and the drain electrode d of the source S of M3 pipe and M6 pipe links together as not gate V
0Output terminal;
Two of fuzzy logic not circuit, consisted of by 9 metal-oxide-semiconductor M1 pipe～M9 pipes, 2 diode D1, D2, wherein M1 pipe, M2 pipe are the NMOS pipe, M3 pipe～M9 is the PMOS pipe, form difference channel by M1 pipe～M4 pipe, the source S of the source S of M1 pipe and M2 pipe is connected with the negative pole of D1, the plus earth of D1, the grid g of the drain electrode d of M1 pipe and the source S of M3 pipe and PMOS pipe M5 links together, M3 pipe, the grid g of M4 pipe and the source S of M4 pipe and the drain electrode d of M2 pipe link together, and the drain electrode d of M3 pipe～M5 pipe all meets power supply V
DD, M6 pipe, M7 tube grid G all meet power supply V
DD, the drain electrode d of the M6 pipe power supply V that is connected with substrate b
DDThe drain electrode d of the source S of M6 pipe and M7 pipe and substrate b are connected with the grid G of M1 pipe, the source S ground connection of M7 pipe, the drain electrode d of the grid G of the grid G of M2 pipe and M9 pipe, drain electrode d and substrate b and M8 pipe links together, and the grid G of M8 pipe and source S and substrate b link together as V
AInput end, the source S of the source S of M9 pipe and M5 pipe and the negative pole of D2 link together as V
0Output terminal, the plus earth of D2.
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