CN102082149A - Ballast structure for input and output ESD (Electro-Static Discharge) protection of full-metal silicide - Google Patents
Ballast structure for input and output ESD (Electro-Static Discharge) protection of full-metal silicide Download PDFInfo
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- CN102082149A CN102082149A CN2009102528798A CN200910252879A CN102082149A CN 102082149 A CN102082149 A CN 102082149A CN 2009102528798 A CN2009102528798 A CN 2009102528798A CN 200910252879 A CN200910252879 A CN 200910252879A CN 102082149 A CN102082149 A CN 102082149A
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- type well
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- H01—ELECTRIC ELEMENTS
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Abstract
The invention relates to a ballast structure for the input and output ESD (Electro-Static Discharge) protection of full-metal silicide, characterized by comprising a joint sheet, a substrate, a NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor), wherein the NMOS is arranged on the substrate and comprises a first N-type well, a first source electrode and a first drain electrode, the first area of the first N-type well is connected with the joint sheet, the first drain electrode is arranged in the first N-type well and forms a ballast resistor with the first area; the PMOS is arranged on the substrate and comprises a second N-type well, a second source electrode and a second drain electrode, and the second source electrode is arranged in the second N-type well, and the second drain electrode is arranged in the second N-type well and connected to the first drain electrode through a conductor. The ballast structure for the input and output ESD (Electro-Static Discharge) protection of the full-metal silicide, which is provided by the invention, has the advantage of improving the ESD strength of a full-metal silicide I/O (Input/Output) driver.
Description
Technical field
The present invention relates to a kind of static discharge (Electro-Static Discharge; ESD) protection structure specifically, is that a kind of whole metal silicide that is used for is exported ballast structural into esd protection.
Background technology
In complementary gold oxygen half (CMOS) integrated circuit (IC), along with the evolution of volume production processing procedure, the size of assembly has tapered to the stage of deep-sub-micrometer (deep-submicron), with performance and the arithmetic speed of enhancement IC, and the manufacturing cost that reduces every chips.But along with the reduction of size of components, the problem of some reliabilitys appears but.
In inferior micron technology, develop in order to overcome hot carrier (hot-carrier) effect and light dope drain (Lightly-Doped Drain; LDD) processing procedure and structure; For the source electrode that reduces CMOS and parasitic patch resistance (sheet resistance) Rs and the Rd of drain, metal silicide (silicide) processing procedure and develop; For the parasitic patch resistance R g of the gate that reduces CMO S and develop and metal multi-crystal silicification thing (polycide) processing procedure; In more advanced processing procedure, metal silicide is made with metal multi-crystal silicification thing, automatic aligning metal silicide (self-aligned silicide and develop; Salicide) processing procedure.
Yet, aforementioned processing procedure and dwindle after size of components, all cause CMOS IC (for example NMOS and PMOS) that the protective capability of ESD is significantly reduced.In the face of the static that produces in the external environment time, these CMOS IC are more serious because of the situation that ESD damages.For instance, when the channel width (channel width) of an output buffer stage commonly used (output buffer) assembly is fixed on 300 microns (μ m), NMOS with the conventional art manufacturing of 2 μ m can withstand voltagely surpass 3 kilovolts, but add the assembly that the LDD technology is made with 1 μ m processing procedure, its ESD pressure withstanding degree is less than 2 kilovolts, add LDD and aim at the assembly that the metal silicide technology is made, only about 1 kilovolt of its ESD pressure withstanding degree automatically with 1 μ m processing procedure.Under the constant situation of size of components, different processing procedures makes the esd protection ability landing significantly of assembly, and many deep-sub-micrometer CMOS IC products all face this stubborn problem.
Automatically aiming in the metal silicide processing procedure; owing to the sheet resistor value of the N type diffusion zone that adds metal silicide is very low; cause the steady resistance in drain zone not enough; therefore aim at the metal silicide processing procedure automatically esd protection circuit is caused serious threat; again because steady resistance is too little; cause the extra-high pressure of ESD directly to drop on drain, thereby cause the short circuit between gate pole oxidation layer damage or drain and the source electrode near the gate place.In order to improve the ESD toughness (robustness) of MO SFET in metal silicide CMOS processing procedure, the most direct existing settling mode is to add to aim at metal silicide together automatically to intercept light shield (Salicide Blocking; SB), this technology forms metal silicide by the zone of avoiding the esd protection assembly and improves the ESD toughness.In the CMOS processing procedure, silicon dioxide forms the temperature of metal silicide than silicon height, therefore can be used as the obstruct light shield by place oxide on the planning zone before the precipitation of metal silicide.Described oxide separates silicon and metal, avoid metal after annealing process in silication.Because blocked the silication of metal and contacting of appropriate increase and gate interval, the ESD toughness of MOSFET improves because of the increase of steady resistance.But the SB technology can increase by one light shield and the fabrication steps of being correlated with, and causes manufacturing cost to increase.So other uses the ballast technology of high steady resistance (ballast resistance) just to be suggested.
Because ESD is a kind of phenomenon of big electric current; the gathering of electric current will impact to the esd protection assembly; and the steady resistance that increases ESD ballast assembly (MOSFET) can make the ESD current path go deep into substrate (substrate) to improve the ESD toughness; and the ground protection ring of different distance (grounded guardring) causes asymmetric substrate resistance; make to refer to that (multi-finger) NMO S assembly bears the conducting of not dividing equally, because the voltage difference V on the esd protection assembly more
DropBe the ESD electric current I
ESDBe multiplied by conducting resistance R
On
V
Drop=(I
ESD* R
On) formula 1
By with steady resistance R
BallastSeries on-resistance R
On, can increase pressure reduction
V
Drop=(I
ESD* R
On') formula 2
R wherein
On'=(R
On+ R
Ballast).As shown in Figure 1, promote steady resistance R
BallastMake second breakdown voltage (V
T2) be increased to and be higher than bipolarity trigger voltage (V
T1) after, phytyl for example refers to NMOS in rapid (snapback-based) esd protection assembly that returns more, just can trigger equably under the ESD bombardment, in other words, increases steady resistance and can effectively improve the ESD toughness.
Fig. 2 shows a kind of method of known increase steady resistance, the source electrode of NMOS, gate and drain all are arranged on the substrate 18, its drain is divided into first area 10 and second area 14, separate with insulator 12 between the two, first area 10 connects the joint sheet (not shown), must pass N type well (N-Well) 16 by joint sheet via the electric current that first area 10 enters NMOS, arrive the gate channel via second area 14 again.If with equivalent electric circuit, the drain that can be considered at NMOS connects resistance R
N-WellAfter connect joint sheet again, thereby promote the ESD toughness of NMOS.N type well 16 can determine resistance R for having the low doped region of high sheet resistor value by degree of depth L and the width W of adjusting N type well 16
N-Well Resistance.Insulator 12 can be field oxide (Field Oxide; FOX) or shallow trench isolation (Shallow Trench Isolation; STI).
Fig. 3 shows the method for another kind of known increase steady resistance, between the first area 10 of drain and second area 14 sky (dummy) gate 20 is set, to force the electric current N type well 16 of flowing through.
The method of Fig. 2 and Fig. 3 does not need to increase light shield and can implement, but be only applicable to NMOS, this is because can produce parasitic diode D1 and D2 between the drain of PMOS and the N type well, as shown in Figure 4, parasitic diode D1 and D2 make electric current can't be flowed into the first area 22 and the second area 24 of drain by N type well 26.
Fig. 5 shows use polysilicon back segment ballast (poly Back-End Ballast; BEB) layout of the NMOS of technology (layout) top view and end view, this BEB technology can be applicable on PMOS and the NMOS.In the both sides of NMOS insulator 28 and 30 are set, and on insulator 28 and 30, conductor 32 and 34 are set, be connected to the drain of NMOS after making electric current via node 1,2,3, enter source electrode via the gate passage again, again via node 4,5 and 6.This technology is to reach the purpose of increase steady resistance by elongating current path, so can be applicable to NMOS and PMOS simultaneously, and correlation technique can be with reference to U.S. Patent number 6,046,087.
The another kind of known technology that increases steady resistance is called active area cutting (Active-Area-Segmentation; AAS).And U.S. Patent number 7; 005; 708 just disclose this correlation technique; as shown in Figure 6; when this technology is applied to whole metal silicide (fully silicided) esd protection MOSFET; can further reduce layout area than BEB technology,, drain be increased to the resistivity of the ESD current path of each diffusion zone of source electrode by the diffusion area of cutting drain and source dopant.
Fig. 7 is the another kind of mode of known AAS ballast technology, also is applicable to whole metal silicide MOSFET.This method is utilized zone diffusion and special circuit layout, makes the electric current of drain prolong non-directional route 36 and flows to source electrode, by elongating the purpose that current path reaches increases steady resistance.Also can use STI or FOX that diffusion zone is separated, reach the technique effect of AAS.
U.S. Patent number 7,009,252 disclose a kind of unsteady polysilicon array (Floating Poly Array in addition; FPA) technology.Fig. 8 is layout top view and the end view that uses the NMOS of FPA technology, utilizes staggered polysilicon array 38 to separate diffusion zone to increase the steady resistance value.
In the CMOS processing procedure, contact resistance (contact resistance) provides another kind to be applied to the ballast technology of whole metal silicide esd protection MOSFET.As shown in Figure 9, with 40 places as joint sheet, this contact ballast (ConTact Ballast; CTB) technology is forced steady resistance on whole metal silicide NMOS from contact 42,44,46 and diffusion zone 48.The existing report of the NMOS of tool CTB technology points out to have higher ESD toughness than the NMOS of SB technology.
Though it is still rare that existing many ballast technology applicable to whole metal silicide I/O driver, can be accomplished the esd protection technology of whole chip.In order to dwindle simultaneously circuit area and to improve the ESD toughness, often adopt I/O driver in the known COMS chip with self-protection function, it there is no in parallel extra esd protection assembly.Therefore, when using the ESD test of the full chip that the 2-kV PS pattern ESD of minimum esd protection requirement does on the I/O joint sheet, the deficiency of its steady resistance makes the ESD electric current be gathered in the surface of silicon, causes the collapse of whole metal silicide NMOS.
Therefore known ballast technology exists above-mentioned all inconvenience and problem to the protection of ESD.
Summary of the invention
Purpose of the present invention is to propose a kind of esd protection circuit that is used to export into joint sheet.
Another object of the present invention is to propose a kind of whole metal silicide that is used for and exports ballast structural into esd protection.
For achieving the above object, technical solution of the present invention is:
A kind of whole metal silicide that is used for is exported ballast structural into esd protection, it is characterized in that comprising:
Joint sheet;
Substrate;
NMOS is arranged on the described substrate, comprising:
The one N type well wherein has the first area and connects described joint sheet;
First source electrode; And
First drain is arranged in the described N type well, and is formed with steady resistance between the described first area; And
PMOS is arranged on the described substrate, comprising:
The 2nd N type well;
Second source electrode is arranged in described the 2nd N type well; And
Second drain is arranged in described the 2nd N type well, is connected to described first drain via conductor.
In view of the above, described steady resistance is protected described NMOS and described PMOS simultaneously.
A kind of whole metal silicide that is used for is exported ballast structural into esd protection, it is characterized in that comprising:
Joint sheet;
Substrate;
NMOS is arranged on the described substrate, comprising:
The one N type well wherein has the first area and connects described joint sheet;
First source electrode; And
First drain is arranged in the N type well, and is formed with first steady resistance between the described first area; And
PMOS is arranged on the described substrate, comprising:
The 2nd N type well wherein has second area and connects described joint sheet;
Second source electrode is arranged in described the 2nd N type well; And
Second drain is arranged in described the 2nd N type well, and is formed with second steady resistance between the described second area, and is connected to described first drain via conductor.
After adopting technique scheme, the whole metal silicide that is used for of the present invention is exported the advantage that has the ESD intensity of improving whole metal silicide I/O driver into the ballast structural of esd protection.
Description of drawings
Fig. 1 improves the current/voltage schematic diagram of ESD stability for steady resistance;
Fig. 2 is a kind of method schematic diagram of known increase NMOS steady resistance;
Fig. 3 is the method schematic diagram of the known increase NMOS steady resistance of another kind;
Fig. 4 is that the known technology of Fig. 2 and Fig. 3 is used in the schematic side view on the PMOS;
Fig. 5 is the NMOS layout top view and the schematic side view of known polysilicon back segment ballast technology;
Fig. 6 is the NMOS layout top view of known active area cutting technique;
Fig. 7 is the NMOS layout top view of another known active area cutting technique;
Fig. 8 is the NMOS layout top view and the schematic side view of known unsteady polysilicon array technology;
Fig. 9 is the contact ballast technology schematic diagram of known full-silicide esd protection MOSFET;
Figure 10 is the layout top view of the embodiment of the invention;
Figure 11 is the assembly sectional view by A to A ' of embodiment of the invention Figure 10;
Figure 12 is the layout top view of another embodiment of the present invention; And
Figure 13 is the assembly sectional view by A to A ' of embodiment of the invention Figure 12.
Among the figure, 10, first area 12, insulating barrier 14, second area 16, N type well 18, substrate 20, empty gate 22, first area 24, second area 26, N type well 28, insulating barrier 30, insulating barrier 32, conductor 34, conductor 36, non-directly through the path 38, polysilicon array 40, joint sheet 42, contact 44, contact 46, contact 48, diffusion zone.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof the present invention is illustrated further.
The present invention proposes the embodiment of two kinds of ballast methods, can be on the I/O driver simultaneously to the NMOS and the PMOS ballast of whole metal silicide.
Because known whole metal silicide I/O driver can't require (2-kV HBM ESD toughness) by the general esd protection of commercial IC product, must increase its ESD intensity with ballast technology.
Now see also Figure 10, Figure 10 is the layout top view of the embodiment of the invention, and N type well is separated drain diffusion and around the zone that is connected with joint sheet, so that the steady resistance of needs to be provided effectively on NMOS.Yet as previously mentioned, because this technology can't be applied on the PMOS assembly, the ballast demand of PMOS realizes with special metal path arrangement in addition.Be different from known layout (layout) configuration, the drain of PMOS is free of attachment to joint sheet but is connected to the drain of NMOS, and the drain of NMOS is electrically connected to joint sheet by N type well.
Figure 11 represents the assembly sectional view of Figure 10 embodiment by A to A '.By this layout configurations, electric current is compelled to by the N type well among the NMOS to the path of joint sheet by PMOS, makes described N type well ballast NMOS and PMOS simultaneously.Because the current lead-through path by PMOS is compelled to by N type well, its resistance in Figure 11 with resistance R
BallastExpression, its protection effect is affected under PS pattern ESD test, under PS pattern ESD test, the ESD electric current is earlier by the drain discharge of N type well steady resistance to PMOS, then by parasitizing diode between P+ and the N type well among the PMOS to V
DDEnd, the ESD clamp circuit (ESD clamp circuit) by power rail (power-rail) arrives earth terminal at last.Inevitably, though ballast N type well protection the ESD on the NMOS damage, in PS pattern ESD test, increased joint sheet also to the droop loss (I between the earth terminal
ESD* R
Ballast), the pressure drop pinching of described increase esd protection window (ESD protection window) and cause internal circuit to become more responsive to the ESD mistake, particularly in deep-sub-micrometer CMOS technology.
The another kind of embodiment that Figure 12 proposes for the present invention, and Figure 13 is the assembly sectional view by A to A ' of Figure 12.In order to improve aforementioned affect, this kind ballast technology comprises that N type well is separated drain diffusion and around the zone that is connected with joint sheet, to reach the demand of ballast on NMOS, yet, drain diffusion on the PMOS also is separated, in order to preserve the driving force of PMOS, the drain of PMOS and NMOS is connected to each other, in this configuration, the ESD electric current of PS pattern test can be directly through parasitizing the diode between P+ and the N type well and the ESD clamp circuit discharge of power rail among the PMOS, and the steady resistance R that forms between P+ and the N type well among the NMOS that do not need to flow through
BallastThe described P+ diffusion region that separates directly connects joint sheet, therefore can provide effective discharge path to the ESD electric current under the described PS pattern, and the N type well steady resistance among the PMOS avoids whole metal silicide PMOS damaged by ND pattern ESD energy.
The assembly that table 1 is listed the assembly of known no ballast technology and the present invention two embodiment is exported static discharge tolerance level into end human body discharge mode (HBM) in the all-metal silication.Numerical value in the table 1 has verified that the ESD that lowest-order is brought out on the IC damages, and its test result has confirmed that the present invention has effectively improved the ESD intensity of whole metal silicide I/O driver.
Table 1
Above embodiment is only for the usefulness that the present invention is described, but not limitation of the present invention, person skilled in the relevant technique under the situation that does not break away from the spirit and scope of the present invention, can also be made various conversion or variation.Therefore, all technical schemes that are equal to also should belong to category of the present invention, should be limited by each claim.
Claims (2)
1. one kind is used for whole metal silicide and exports ballast structural into esd protection, it is characterized in that comprising:
Joint sheet;
Substrate;
NMOS is arranged on the described substrate, comprising:
The one N type well wherein has the first area and connects described joint sheet;
First source electrode; And
First drain is arranged in the described N type well, and shape between the described first area
Become to have steady resistance; And
PMOS is arranged on the described substrate, comprising:
The 2nd N type well;
Second source electrode is arranged in described the 2nd N type well; And
Second drain is arranged in described the 2nd N type well, is connected to described first drain via conductor.
In view of the above, described steady resistance is protected described NMOS and described PMOS simultaneously.
2. one kind is used for the ballast structural that whole metal silicide is exported esd protection, it is characterized in that comprising:
Joint sheet;
Substrate;
NMOS is arranged on the described substrate, comprising:
The one N type well wherein has the first area and connects described joint sheet;
First source electrode; And
First drain is arranged in the N type well, and is formed with first steady resistance between the described first area; And
PMOS is arranged on the described substrate, comprising:
The 2nd N type well wherein has second area and connects described joint sheet;
Second source electrode is arranged in described the 2nd N type well; And
Second drain is arranged in described the 2nd N type well, and is formed with second steady resistance between the described second area, and is connected to described first drain via conductor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102528798A CN102082149A (en) | 2009-11-30 | 2009-11-30 | Ballast structure for input and output ESD (Electro-Static Discharge) protection of full-metal silicide |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009102528798A CN102082149A (en) | 2009-11-30 | 2009-11-30 | Ballast structure for input and output ESD (Electro-Static Discharge) protection of full-metal silicide |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610495A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Manufacturing method of semiconductor resistor, semiconductor resistor and electronic device |
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| US5631793A (en) * | 1995-09-05 | 1997-05-20 | Winbond Electronics Corporation | Capacitor-couple electrostatic discharge protection circuit |
| TW359021B (en) * | 1995-07-06 | 1999-05-21 | Transpacific Ip Ltd | Mutual compensation metal-oxygen half output buffer containing anti-static discharge protection circuit |
-
2009
- 2009-11-30 CN CN2009102528798A patent/CN102082149A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW359021B (en) * | 1995-07-06 | 1999-05-21 | Transpacific Ip Ltd | Mutual compensation metal-oxygen half output buffer containing anti-static discharge protection circuit |
| US5631793A (en) * | 1995-09-05 | 1997-05-20 | Winbond Electronics Corporation | Capacitor-couple electrostatic discharge protection circuit |
Non-Patent Citations (1)
| Title |
|---|
| MING-DOU KER, WEN-YI CHEN, WUU-TRONG SHIEH, I-JU WEI: "New Layout Scheme to Improve ESD Robustness of I/O Buffers in Fully-Silicided CMOS Process", 《EOS/ESD SYMPOSIUM》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610495A (en) * | 2012-03-31 | 2012-07-25 | 上海宏力半导体制造有限公司 | Manufacturing method of semiconductor resistor, semiconductor resistor and electronic device |
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Application publication date: 20110601 |