CN102082122A - Manufacturing method of electric fuse, resistor and transistor - Google Patents
Manufacturing method of electric fuse, resistor and transistor Download PDFInfo
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- CN102082122A CN102082122A CN200910225877XA CN200910225877A CN102082122A CN 102082122 A CN102082122 A CN 102082122A CN 200910225877X A CN200910225877X A CN 200910225877XA CN 200910225877 A CN200910225877 A CN 200910225877A CN 102082122 A CN102082122 A CN 102082122A
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Abstract
The invention relates to a manufacturing method of an electric fuse, a resistor and a transistor, comprising the following steps: providing a substrate, and then forming a transistor grid, the resistor and the electric fuse on the substrate, wherein the transistor grid, the resistor and the electric fuse are respectively provided with a first dielectric layer, a polycrystalline silicon layer and a hard mask; then forming a source/drain doping area in the substrate adjacent to the transistor grid; removing the resistor and the hard mask in the electric fuse, then carrying out a metal siliconization process, forming metal siliconized layers on the source/drain doping area, the resistor and the electric fuse, then forming a flattened second dielectric layer to cover the substrate, exposing the polycrystalline silicon layer of the transistor grid, the resistor and the electric fuse, and then removing the polycrystalline silicon layer in the transistor grid so as to form a groove; and finally, forming a metal layer to fill the groove.
Description
Technical field
The present invention relates to a kind of electric fuse, resistance and transistorized manufacture method.
Background technology
In general along with the microminiaturization of semiconductor technology and the raising of complexity, semiconductor element easier various defective or the impurity of being subjected to that also becomes influences, therefore making outside metal connecting line, diode or the transistor unit, also can additionally in integrated circuit, form the connecting line (fusible links) of some fusible, electric fuse (efuse) just is to guarantee the utilizability of integrated circuit.Electric fuse comprises anode, negative electrode, reaches the electric fuse body.Usually on anode and negative electrode, respectively be electrically connected with a plurality of metal plugs, and the electric fuse body is formed by polysilicon layer and metal silicide layer.
And in order to promote transistorized operating efficiency, in semiconductor industry, be to utilize metal at present as transistor gate, metal gates has advantages such as low resistance and no depletion effects, it is good to improve the operation usefulness that traditional grid uses high-resistance polycrystalline silicon material to cause, and it typically uses back grid (gate-last) technology manufacturing.
In addition, in integrated circuit, often need to add the setting of other circuit elements such as resistance, do functions such as voltage stabilizing or filter noise.And in general its main body of resistance also is to utilize polysilicon, doped region or metal oxide to make.
To sum up discuss, because the high complexity of integrated circuit technology and the high-accuracy property of various component products, therefore when pursuing the continuous lifting of yield, except attempting the improved process technology, demand to process integration also is a considerable ring, to reduce processing step and to promote production efficiency simultaneously.Therefore, developing a kind of integrated process of making metal gates, resistance and electric fuse, is crucial now problem.
Summary of the invention
In view of this, the invention provides a kind of electric fuse, resistance and transistorized manufacture method.Substrate at first is provided, form transistor gate then, resistance and electric fuse are in substrate, and transistor gate, resistance, electric fuse all has first dielectric layer, polysilicon layer, hard mask, form source electrode afterwards in the other substrate of transistor gate, then remove the hard mask in resistance and the electric fuse, carry out silication technique for metal then, form metal silicified layer in source electrode, on the resistance and on the electric fuse, second dielectric layer that forms planarization again covers substrate, and expose the polysilicon layer of transistor gate, resistance and electric fuse, remove the polysilicon layer in the transistor gate afterwards, to form groove, form metal level at last and fill up groove.
According to another preferred embodiment of the invention, the invention provides a kind of electric fuse, resistance and transistorized manufacture, substrate at first is provided, then form transistor gate, resistance and electric fuse are in substrate, and transistor gate, resistance, electric fuse all has first dielectric layer, polysilicon layer, hard mask, form source electrode then in the other substrate of transistor gate, form first metal silicified layer again in source electrode, form second dielectric layer afterwards and cover substrate, transistor gate, resistance, electric fuse and source electrode, follow planarization second dielectric layer, and expose the polysilicon layer of transistor gate, the polysilicon layer of resistance and the polysilicon layer of electric fuse, remove the polysilicon layer that exposes to the open air in the transistor gate afterwards, to form groove, form metal level then and fill up groove, form at last after the metal level, form second metal silicified layer on resistance and electric fuse.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, the preferred embodiments of the present invention cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
What Fig. 1 to Fig. 6 illustrated is the schematic diagram of according to a first advantageous embodiment of the invention electric fuse, resistance and transistorized manufacture.
What Fig. 7 to Figure 11 illustrated is the schematic diagram of electric fuse according to a second, preferred embodiment of the present invention, resistance and transistorized manufacture.
Description of reference numerals
10: substrate 12: shallow trench isolation from
14: dielectric layer 16: high dielectric material layer
18: cap rock 20,54: work function layer
22: polysilicon layer 24: hard mask
The 26:N type polysilicon bar utmost point 28:P type polysilicon bar utmost point
30: resistance 32: electric fuse
34: clearance wall 36,38: source drain doped region
40,50: pattern mask 42: blocking layer of metal silicide
44,441: metal silicide layer 46: etching stopping layer
48: interlayer dielectric layer 52: groove
56: gate metal layer 261,281: metal gate transistor
301: electric resistance structure 321: electric fuse structure
Embodiment
What Fig. 1 to Fig. 6 illustrated is the schematic diagram of according to a first advantageous embodiment of the invention electric fuse, resistance and transistorized manufacture.At first, as shown in Figure 1, provide substrate 10, have N transistor npn npn district N, P transistor npn npn district P, resistance area R and electric fuse district F, in N transistor npn npn district N, P transistor npn npn district P, resistance area R and electric fuse district F, then be respectively equipped with shallow trench isolation from 12.
Then on N transistor npn npn district N, P transistor npn npn district P, resistance area R and electric fuse district F, form dielectric layer 14 and high dielectric material layer 16 in regular turn, form cap rock 18 afterwards on N transistor npn npn district N, resistance area R and electric fuse district F.Then, holomorphism success function layer 20, for example, titanium nitride, on the cap rock 18 of N transistor npn npn district N, resistance area R and electric fuse district F and on the high dielectric material layer 16 of P transistor npn npn district P, afterwards, the work function floor 20 that utilizes the pattern mask (not shown) will be positioned on resistance area R and the electric fuse district F removes.Then, form the cap rock 18 that polysilicon layer 22 and hard mask 24 floor cover work function floor 20, resistance area R and the electric fuse district F of N transistor npn npn district N and P transistor npn npn district P in regular turn comprehensively.
As shown in Figure 2, follow patterning hard mask layer 24, polysilicon layer 22, work function layer 20, cap rock 18, high dielectric material layer 16 and dielectric layer 14, to form the N type polysilicon bar utmost point 26 in N transistor npn npn district N, form the P type polysilicon bar utmost point 28 at P transistor npn npn district P, form resistance 30 at resistance area R, form electric fuse 32 at electric fuse district F.Then, the sidewall at the N type polysilicon bar utmost point 26, the P type polysilicon bar utmost point 28, resistance 30 and electric fuse 32 forms clearance wall 34 respectively.Clearance wall 34 can be individual layer or multilayer clearance wall, is example with the multilayer clearance wall in the present invention.Afterwards, in the substrate 10 on the N type polysilicon bar utmost point 26 and the P type polysilicon bar utmost point 28 sides, each forms source drain doped region 36,38.In addition, present embodiment again can be in conjunction with strained silicon technology, uphold or the epitaxial loayer of compression stress and in the source drain doped region 36,38 of N transistor npn npn or P transistor npn npn, be provided with respectively to be used to provide, for example in the source drain doped region 38 on the P type polysilicon bar utmost point 28 sides, can optionally form the germanium silicide epitaxial loayer.
Then, form pattern mask 40, photoresist for example, at N transistor npn npn district N, P transistor npn npn district P, resistance area R and electric fuse district F, and expose resistance 30 and electric fuse 32, then remove the hard mask layer 24 on resistance 30 and the electric fuse 32, with the polysilicon layer 22 that exposes resistance 30 and the polysilicon layer 22 of electric fuse 32.
As shown in Figure 3, after removing pattern mask 40, the blocking layer of metal silicide 42 that forms patterning again covers resistance area R and electric fuse district F, and exposes the upper surface of the polysilicon layer 22 of the two ends of polysilicon layer 22 of resistance 30 and electric fuse 32.Carry out silication technique for metal then, to form metal silicide layer 44 respectively in the two ends of the polysilicon layer 22 of source electrode 36,38, resistance 30 and the upper surface of the polysilicon layer 22 of electric fuse 34.
Form etching stopping layer 46 as shown in Figure 4 then all sidedly, for example silicon nitride layer conformably covers substrate 10, blocking layer of metal silicide 42, the N type polysilicon bar utmost point 26, the P type polysilicon bar utmost point 28, resistance 30 and electric fuse 32.Then, form interlayer dielectric layer 48 again and cover etching stopping layers 46, afterwards again planarization interlayer dielectric layer 48 to the polysilicon layer 22 of the polysilicon layer 22 that exposes the N type polysilicon bar utmost point 26, the P type polysilicon bar utmost point 28, the polysilicon layer 22 of resistance 30 and the metal silicide layer 44 on metal silicide layer 44 and the electric fuse 32.Wherein, the mode of planarization interlayer dielectric layer 48 can be utilized chemico-mechanical polishing, and present embodiment can come along the hard mask layer 24 in the N type polysilicon bar utmost point 26 and the P type polysilicon bar utmost point 28 respectively and remove in planarization interlayer dielectric layer 48.
As shown in Figure 5, on interlayer dielectric layer 48, form pattern mask 50 and cover resistance area R and electric fuse district F, expose the N type polysilicon bar utmost point 26 and the P type polysilicon bar utmost point 28, then remove the polysilicon layer 22 of the N type polysilicon bar utmost point 26 and the polysilicon layer 22 in the P type polysilicon bar utmost point 28, respectively to form groove 52 at N transistor npn npn district N and P transistor npn npn district P respectively.
As shown in Figure 6, remove pattern mask 50, holomorphism success function layer 54 conformably covers the sidewall and the bottom of interlayer dielectric layer 48, clearance wall 34, resistance 30, electric fuse 32 and groove 52 again.Form gate metal layer 56 then, cover work function layer 54 and fill up groove 52.At last, planarized gate metal level 56 and work function layer 54 again, trim until the surface of gate metal layer 56 and work function layer 54 and the surface of interlayer dielectric layer 48, at this moment, work function layer 54 and gate metal layer 56 on resistance 30 and the electric fuse 32 all are removed, and expose polysilicon layer 22 and metal silicide layer 44.So far, electric fuse structure 321 of the present invention, electric resistance structure 301 are just finished with first preferred embodiment of metal gate transistor 261,281.
In addition, please refer to Fig. 1,7 to Figure 11, what Fig. 1,7 to Figure 11 illustrated is the schematic diagram of electric fuse according to a second, preferred embodiment of the present invention, resistance and transistorized manufacture, wherein has the element of identical function, will represent with identical label.The difference main with first preferred embodiment is: the gate metal layer in second preferred embodiment early forms than the metal silicide layer on resistance and the electric fuse.In addition, the metal silicide layer on metal silicide layer on the source electrode and resistance and the electric fuse is not to form in same step in second preferred embodiment.Moreover, in first preferred embodiment, be covered with blocking layer of metal silicide on resistance of finishing and the electric fuse.
As shown in Figure 1, identical with first preferred embodiment, at first, substrate 10 is provided, has N transistor npn npn district N, P transistor npn npn district P, resistance area R and electric fuse district F, at N transistor npn npn district N, P transistor npn npn district P, be covered with dielectric layer 14 and high dielectric material layer 16 in regular turn on resistance area R and the electric fuse district F, at N transistor npn npn district N, on the high dielectric material layer 16 of resistance area R and electric fuse district F cap rock 18 is arranged, and on the high dielectric material layer 16 of P transistor npn npn district P and on the cap rock 18 of N transistor npn npn district N work function floor 20 being arranged, polysilicon layer 22 and hard mask 24 floor cover the work function floor 20 of N transistor npn npn district N and P transistor npn npn district P in regular turn, the cap rock 18 of resistance area R and electric fuse district F.
As shown in Figure 7, form the N type polysilicon bar utmost point 26 respectively at N transistor npn npn district N, form the P type polysilicon bar utmost point 28 at P transistor npn npn district P, form resistance 30 at resistance area R, form electric fuse 32 at electric fuse district F, sidewall in the N type polysilicon bar utmost point 26, the P type polysilicon bar utmost point 28, resistance 30 and electric fuse 32 forms clearance wall 34 then, and clearance wall 34 can be individual layer or multilayer clearance wall.Afterwards, in the substrate 10 on the N type polysilicon bar utmost point 26 and the P type polysilicon bar utmost point 28 sides, each forms source electrode 36,38.Similarly, present embodiment again can be in conjunction with various strained silicon technology, and for example the P type polysilicon bar utmost point 28 other source electrode 38 can optionally form the germanium silicide epitaxial loayer.Carry out silication technique for metal then, form metal silicified layer 44 respectively, wherein,, therefore can not react owing to still be provided with hard mask layer 24 on polysilicon gate 26,28, resistance 30 and the electric fuse 32 in source electrode 36,38.
As shown in Figure 8, form etching stopping layer 46 all sidedly, for example silicon nitride layer conformably covers substrate 10, clearance wall 34, the N type polysilicon bar utmost point 26, the P type polysilicon bar utmost point 28, resistance 30 and electric fuse 32.Then, form interlayer dielectric layer 48 again and cover etching stopping layers 46, afterwards again planarization interlayer dielectric layer 48 to the polysilicon layer 22 of the polysilicon layer 22 that exposes the N type polysilicon bar utmost point 26, the P type polysilicon bar utmost point 28, polysilicon layer 22 on the resistance 30 and the polysilicon layer 22 on the electric fuse 32.In planarization interlayer dielectric layer 48, can come along and remove laying respectively at hard mask layer 24 in the N type polysilicon bar utmost point 26, the P type polysilicon bar utmost point 28, resistance 30 and the electric fuse 32.
As shown in Figure 9, form pattern mask 50, photoresist for example, cover resistance area R and electric fuse district F and expose N transistor npn npn district N and P transistor npn npn district P, so the polysilicon layer 22 of the polysilicon layer 22 of the N type polysilicon bar utmost point 26 among the N transistor npn npn district N and the P type polysilicon bar utmost point 28 among the P transistor npn npn district P also exposes to the open air out.Then, remove the polysilicon layer 22 in the N type polysilicon bar utmost point 26 and the P type polysilicon bar utmost point 28, to form groove 52 respectively at N transistor npn npn district N and P transistor npn npn district P.
As shown in figure 10, remove after the pattern mask 50, holomorphism success function layer 54 conformably covers the sidewall and the bottom of interlayer dielectric layer 48, clearance wall 34, resistance 30, electric fuse 32 and groove 52.Then, form gate metal layer 56, cover work function layer 54 and fill up groove 52.At last, planarized gate metal level 56 and work function layer 54 trim until the surface of gate metal layer 56 and work function layer 54 and the surface of interlayer dielectric layer 48 again, and expose the polysilicon layer 22 of resistance 30 and the polysilicon layer 22 of electric fuse 32.
As shown in figure 11, the blocking layer of metal silicide (not shown) that forms patterning covers resistance area R and electric fuse district F, and exposes the upper surface of the polysilicon layer 22 of the two ends of polysilicon layer 22 of resistance 30 and electric fuse 32.Carry out silication technique for metal then, form metal silicide layer 441 in the two ends of the polysilicon layer 22 of resistance 30 and the upper surface of the polysilicon layer 22 of electric fuse 32.At last, remove the blocking layer of metal silicide of patterning, according to another preferred embodiment of the invention, the blocking layer of metal silicide of patterning can also be selected not remove, and can remain another interlayer dielectric layer as subsequent technique.So far, electric fuse 321 of the present invention, resistance 301 are just finished with second preferred embodiment of metal gate transistor 261,281.
Electric fuse in first preferred embodiment and second preferred embodiment, after resistance and transistor are finished, just can carry out metal interconnecting technology, for example, can be in N transistor npn npn district, P transistor npn npn district, resistance area and electric fuse district form another interlayer dielectric layer comprehensively, then form a plurality of contact plungers at aforesaid interlayer dielectric layer, be electrically connected metal gates respectively, transistorized source electrode, the metal silicide layer at resistance two ends and the metal silicide layer of electric fuse, then, according to different circuit design, after forming, contact plunger can form plain conductor in addition, and contact plunger, the formation step of plain conductor and interlayer dielectric layer can repeat repeatedly, finishes until metal interconnecting.
The above only is the preferred embodiments of the present invention, and all equivalent variations and modifications of doing according to claim of the present invention all should belong to covering scope of the present invention.
Claims (17)
1. an electric fuse, resistance and transistorized manufacture method comprise:
Substrate is provided;
Form transistor gate, resistance and electric fuse in this substrate, and this transistor gate, this resistance, this electric fuse all have first dielectric layer, polysilicon layer, hard mask;
Form source electrode in the other substrate of this transistor gate;
Remove this hard mask in this resistance and this electric fuse;
Carry out silication technique for metal, form metal silicified layer respectively on this source electrode, this resistance and on this electric fuse;
Second dielectric layer that forms planarization covers this substrate, and exposes this polysilicon layer, this resistance and this electric fuse of this transistor gate;
Remove this polysilicon layer in this transistor gate, to form groove; And
Form metal level and fill up this groove.
2. electric fuse as claimed in claim 1, resistance and transistorized manufacture method, other comprises:
Before forming this source electrode, respectively at forming clearance wall on this transistor gate, this resistance and this electric fuse.
3. electric fuse as claimed in claim 1, resistance and transistorized manufacture method, other comprises:
Before carrying out this silication technique for metal, form the centre that blocking layer of metal silicide covers this polysilicon layer of this substrate, this resistance.
4. electric fuse as claimed in claim 3, resistance and transistorized manufacture method, wherein this metal silicified layer is arranged in the two ends of this polysilicon layer of this resistance, the upper surface of this polysilicon layer of this electric fuse.
5. electric fuse as claimed in claim 1, resistance and transistorized manufacture method, other comprises:
Form before this second dielectric layer, form etching stopping layer and conformably cover this transistor gate, this resistance, this electric fuse and this substrate.
6. electric fuse as claimed in claim 1, resistance and transistorized manufacture method, wherein this first dielectric layer comprises high dielectric material.
7. electric fuse as claimed in claim 1, resistance and transistorized manufacture method, wherein this metal level comprises workfunction layers and gate metal layer.
8. electric fuse as claimed in claim 7, resistance and transistorized manufacture method, wherein the generation type of this metal level comprises:
Form this workfunction layers and conformably cover this second dielectric layer and this groove; And
Forming this gate metal layer covers this workfunction layers and fills up this groove.
9. an electric fuse, resistance and transistorized manufacture method comprise:
Substrate is provided;
Form transistor gate, resistance and electric fuse in this substrate, and this transistor gate, this resistance, this electric fuse all have first dielectric layer, polysilicon layer, hard mask;
Form source electrode in the other substrate of this transistor gate;
Form first metal silicified layer in this source electrode;
Form second dielectric layer and cover this substrate, this transistor gate, this resistance, this electric fuse and this source electrode;
This second dielectric layer of planarization, and expose this polysilicon layer of this transistor gate, this polysilicon layer of this resistance and this polysilicon layer of this electric fuse;
Remove this polysilicon layer that exposes to the open air in this transistor gate, to form groove;
Form metal level and fill up this groove; And
Form after this metal level, form second metal silicified layer respectively on this resistance and this electric fuse.
10. electric fuse as claimed in claim 9, resistance and transistorized manufacture method, other comprises:
Before forming this source electrode, respectively at forming clearance wall on this transistor gate, this resistance and this electric fuse.
11. electric fuse as claimed in claim 9, resistance and transistorized manufacture method, other comprises:
Remove before this polysilicon layer in this transistor gate, form pattern mask and cover this resistance and this electric fuse.
12. electric fuse as claimed in claim 11, resistance and transistorized manufacture method, other comprises: after this polysilicon layer in removing this transistor gate, remove this pattern mask.
13. electric fuse as claimed in claim 9, resistance and transistorized manufacture method, other comprises:
Form before this second metal silicified layer, form the centre that blocking layer of metal silicide covers this polysilicon layer of this substrate and this resistance.
14. electric fuse as claimed in claim 13, resistance and transistorized manufacture method, other comprises:
Form after this second metal silicified layer, remove this blocking layer of metal silicide.
15. electric fuse as claimed in claim 9, resistance and transistorized manufacture method, wherein this second metal silicified layer is arranged in the two ends of this polysilicon layer of this resistance, the upper surface of this polysilicon layer in this electric fuse.
16. electric fuse as claimed in claim 9, resistance and transistorized manufacture method, wherein this metal level comprises workfunction layers and gate metal layer.
17. electric fuse as claimed in claim 16, resistance and transistorized manufacture method, wherein the generation type of this metal level comprises:
Form this workfunction layers and conformably cover this second dielectric layer, this groove; And
Forming this gate metal layer covers this second workfunction layers and fills up this groove.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910225877XA CN102082122B (en) | 2009-11-30 | 2009-11-30 | Manufacturing method of electric fuse, resistor and transistor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910225877XA CN102082122B (en) | 2009-11-30 | 2009-11-30 | Manufacturing method of electric fuse, resistor and transistor |
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| CN102082122A true CN102082122A (en) | 2011-06-01 |
| CN102082122B CN102082122B (en) | 2013-12-11 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137553A (en) * | 2011-11-22 | 2013-06-05 | 台湾积体电路制造股份有限公司 | Integrated circuits with electrical fuses and methods of forming the same |
| CN104183542A (en) * | 2013-05-22 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Electric-fuse structures and formation methods thereof, and semiconductor devices and formation methods thereof |
| CN105280495A (en) * | 2014-05-26 | 2016-01-27 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device and electronic device |
| CN105719945A (en) * | 2014-12-02 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5047826A (en) * | 1989-06-30 | 1991-09-10 | Texas Instruments Incorporated | Gigaohm load resistor for BICMOS process |
| US5821160A (en) * | 1996-06-06 | 1998-10-13 | Motorola, Inc. | Method for forming a laser alterable fuse area of a memory cell using an etch stop layer |
| JP2007194486A (en) * | 2006-01-20 | 2007-08-02 | Elpida Memory Inc | Semiconductor device |
-
2009
- 2009-11-30 CN CN200910225877XA patent/CN102082122B/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103137553A (en) * | 2011-11-22 | 2013-06-05 | 台湾积体电路制造股份有限公司 | Integrated circuits with electrical fuses and methods of forming the same |
| CN104183542A (en) * | 2013-05-22 | 2014-12-03 | 中芯国际集成电路制造(上海)有限公司 | Electric-fuse structures and formation methods thereof, and semiconductor devices and formation methods thereof |
| CN104183542B (en) * | 2013-05-22 | 2017-11-03 | 中芯国际集成电路制造(上海)有限公司 | Electric fuse structure and forming method thereof, semiconductor devices and forming method thereof |
| CN105280495A (en) * | 2014-05-26 | 2016-01-27 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device and electronic device |
| CN105280495B (en) * | 2014-05-26 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method and electronic device of semiconductor devices |
| CN105719945A (en) * | 2014-12-02 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
| CN105719945B (en) * | 2014-12-02 | 2019-01-22 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
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