CN102074195A

CN102074195A - Pixel circuit structure of silicon-based organic light-emitting diode (OLED) display chip and drive method thereof

Info

Publication number: CN102074195A
Application number: CN201010623538XA
Authority: CN
Inventors: 郭海成; 代永平; 凌代年; 邱成峰; 彭华军; 黄飚
Original assignee: GUANGDONG ZHONGXIAN TECHNOLOGY Co Ltd
Current assignee: GUANGDONG ZHONGXIAN TECHNOLOGY Co Ltd
Priority date: 2010-12-29
Filing date: 2010-12-29
Publication date: 2011-05-25

Abstract

The invention discloses a pixel circuit structure of a silicon-based OLED display chip and a drive method thereof. The pixel circuit structure at least has a reading-in p-channel metal oxide semiconductor (PMOS) pipe, a polysilicon-isolator-polysilicon (PIP) capacitor, a drive PMOS pipe, a writing-out PMOS pipe, a ground wire protection PMOS pipe, a video data serial bit line, a power wire which is connected with a PIP upper electrode connecting wire and a source connecting wire of the drive PMOS pipe at the same time, a 0V ground wire connected with a drain of the ground wire protection PMOS pipe through a drain connecting wire of the ground wire protection PMOS pipe, a positive phase row selection wire connected with a grid of the writing-in PMOS pipe through a grid connecting wire of the writing-in PMOS pipe, a negative phase row selection wire connected with the gird of the writing-out PMOS pipe through the grid connecting wire of the writing-out PMOS pipe, and an OLED luminescent layer drive electrode connected with a drive electrode connecting wire. The drive method comprises 9 steps which are carried out circularly after energization. The pixel circuit structure and the drive method thereof reduce production cost, the weight and space volume of the control drive circuit, and the power consumption of the whole machine.

Description

A kind of silica-based OLED display chip image element circuit structure and driving method thereof

Technical field

The invention belongs to the microelectronic applications technical field of information science technology subject, particularly relate to the field of a kind of silica-based OLED display chip image element circuit structure and driving method thereof.

Background technology

OLED (Organic Light Emitting Diode, Organic Light Emitting Diode) is a current driving apparatus, requires back plane circuitry that accurate, stable Current Control can be provided.That early stage active backboard adopts is a-Si (amorphous silicon, amorphous silicon) TFT technology, but owing to the mobility of amorphous silicon reasons such as instability low and threshold voltage are not succeedd, just transfer to LTPS (Low Temperature Poly-Silicon, low temperature polycrystalline silicon) TFT technology afterwards.Compare amorphous silicon, the mobility of LTPS is much higher, but still there is the inconsistent problem of homogeneity in threshold voltage, thereby will carry out certain circuit compensation in the design of image element circuit, and what present existing OLED display major part adopted all is LTPS TFT backplane technology.And aspect large scale OLED volume production, the manufacturing technology of LTPS is still immature, does not have unified standard production line, prepare LTPS TFT backboard and must throw huge fund construction special production line.

And silica-based OLED miniscope spare adopts monocrystalline silicon CMOS substrate technology, compare other substrate technology, monocrystalline silicon has the carrier mobility height, advantages such as threshold voltage is stable, can all be integrated in picture element matrix and peripheral driving circuit etc. on the display screen, reduce the volume and the cost of whole display system greatly, mature C MOS integrated circuit technology is also provided convenience for the substrate manufacture of silica-based OLED miniscope spare simultaneously, and monocrystalline silicon CMOS substrate production standard process flow, the processing charges that only need pay small amount just can prepare substrate on the monocrystalline silicon CMOS of any tame standard substrate production line; Each elemental area on the silica-based oled substrate can be done very for a short time simultaneously, is beneficial to the raising of display resolution.In the design of monocrystalline silicon CMOS substrate chip, what mainly consider is how accurately the electric current of OLED is flow through in control, thereby realizes that good gray scale image shows.Chip power-consumption is also extremely important simultaneously, shows that by the regular handset powered battery, low consumption circuit can prolong the serviceable life of battery because silica-based OLED miniscope spare also just can be used for the portable near eye.

Summary of the invention

At the problems referred to above, the objective of the invention is to overcome the defective that existing LTPS TFT backboard image element circuit exists, a kind of silica-based OLED display chip image element circuit structure and the driving method thereof of based single crystal silicon CMOS substrate technology is provided.

A kind of silica-based OLED display chip image element circuit structure, described silica-based OLED display chip image element circuit structure comprises: at least by reading in PMOS pipe source electrode and reading in PMOS (P-channel Metal Oxide Semiconductor, P type NMOS N-channel MOS N) tube grid and read in that PMOS pipe drain electrode constitutes read in the PMOS pipe, at least PIP (PolySi-insulator-Poly Si, the polysilicon-insulating layer-polysilicon) capacitor that constitutes by PIP capacitor low-resistance polysilicon top electrode and PIP capacitor high resistance polysilicon bottom electrode, at least by driving PMOS pipe source electrode and driving the gate pmos utmost point and drive the driving PMOS pipe that the drain electrode of PMOS pipe constitutes, at least by write out PMOS pipe source electrode and write out the gate pmos utmost point and write out that the drain electrode of PMOS pipe constitutes write out the PMOS pipe, at least the ground wire protection PMOS that protects the gate pmos utmost point and the drain electrode of ground wire protection PMOS pipe to constitute by ground wire protection PMOS pipe source electrode and ground wire manages, by reading in the video data serial bit line that PMOS pipe source electrode line is connected with the described PMOS of reading in pipe source electrode, connect PIP top electrode line simultaneously and drive the power lead that PMOS manages the source electrode line, manage the OV ground wire that drain electrode is connected by ground wire protection PMOS pipe drain electrode line with described ground wire protection PMOS, read in the capable select lines of positive that the gate pmos utmost point is connected by reading in gate pmos utmost point line with described, write out the capable select lines of negative that the gate pmos utmost point is connected by writing out gate pmos utmost point line with described, the OLED luminescent layer drive electrode that is connected with the drive electrode connecting line;

Described PIP top electrode line is connected to described PIP capacitor low-resistance polysilicon top electrode;

Described driving PMOS pipe source electrode line is connected to described driving PMOS pipe source electrode;

Described PIP capacitor high resistance polysilicon bottom electrode is connected on the drain-gate utmost point connecting line that the described PMOS of reading in pipe drains with the described driving gate pmos utmost point is communicated with by PIP bottom electrode line;

The drain electrode of described driving PMOS pipe is connected by the source-drain electrode connecting line with the described PMOS of writing out pipe source electrode;

The described ground wire protection gate pmos utmost point, described ground wire protection PMOS pipe source electrode, the drain electrode of the described PMOS of writing out pipe respectively by ground wire protection gate pmos utmost point line, ground wire protection PMOS pipe source electrode line, write out PMOS pipe drain electrode line and be connected with described drive electrode connecting line;

Described power lead, the capable select lines of described positive, the capable select lines of described negative, described OV ground wire along continuous straight runs are provided with, and the connection of mutually disjointing;

Described video data serial bit line vertically is provided with, and is not communicated with mutually with described power lead, the capable select lines of described positive, the capable select lines of described negative, described OV ground wire;

Described OLED luminescent layer drive electrode is made above 99% aluminum metal by purity, and the area that described OLED luminescent layer drive electrode covers is no more than 90% of described silica-based OLED display chip image element circuit structure area.

Carrying is not less than the constant potential value of 3.3V on the described power lead;

Alternately carry high potential signal and low-potential signal in the described video data serial bit line, and described high potential signal numerical value is not less than the constant potential value that is not less than 3.3V of carrying on the described power lead, and described low-potential signal numerical value is not higher than the numerical value than the low 0.5V of described high potential signal numerical value;

The signal that carries on described positive select lines and the described negative select lines is the reverse voltage signal that do not overlap mutually;

Described a kind of silica-based OLED display chip image element circuit structure adopts the PMOS making technology to produce realization on the n type single crystal silicon substrate;

The present invention is used for the driving method of described silica-based OLED display chip image element circuit structure, comprises as the next stage:

The back circulation that powers on was finished as the next stage:

Phase one: the 1st input of video data signal, order is finished following two steps:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 1st of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

The described positive select lines of carrying OV current potential starts the described PMOS pipe conducting of reading in, signal in the described video data serial bit line is through the described PMOS pipe source electrode line that reads in, the described PMOS pipe that reads in, described drain-gate utmost point connecting line, PIP bottom electrode line imports described PIP capacitor into to be stored, if the numerical value that imports the signal of PIP capacitor into from described video data serial bit line is lower than the numerical value that the constant potential value that is not less than 3.3V of carrying than described power lead is hanged down 0.5V, then described drain-gate utmost point connecting line starts described driving PMOS pipe and enters linear working state, and the described driving PMOS pipe that enters linear working state allows to be no more than 100 electric currents of receiving peace and flows to described source-drain electrode connecting line from described driving PMOS pipe drain electrode line via described driving PMOS pipe; If the numerical value that imports the signal of PIP capacitor into from described video data serial bit line is not less than the numerical value that the constant potential value that is not less than 3.3V of carrying than described power lead is hanged down 0.5V, then described drain-gate utmost point connecting line starts described driving PMOS pipe and enters by duty, enter and only allow to be no more than 1 electric current of receiving peace by the described driving PMOS of duty pipe and flow to described source-drain electrode connecting line via described driving PMOS pipe from described the drivings PMOS pipe line that drains

The described negative select lines that carrying is not less than the current potential of the potential value 0.5V that is carried on the described power lead enters by duty by the described described PMOS of the writing out pipe of gate pmos utmost point line startup that writes out, enter and only allow to be no more than 1 electric current of receiving peace by the described PMOS of writing out of duty pipe and flow to the described PMOS of writing out pipe drain electrode line via the described PMOS of writing out pipe from described source-drain electrode connecting line

2) 3000 to 4000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines input be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 3000 to 4000 microseconds are simultaneously imported the OV current potential on the described negative select lines in the time

The described PMOS of the reading in pipe of described positive select lines startup that carrying is not less than the current potential of the potential value 0.5V that is carried on the described power lead enters by duty, enter and only allow to be no more than 1 by the described PMOS of reading in of duty pipe and receive the electric current of peace or flow to described drain-gate utmost point connecting line or flow to the described PMOS of reading in pipe source electrode line via the described PMOS of reading in pipe via the described PMOS of reading in pipe from described drain-gate utmost point connecting line from the described PMOS of reading in pipe source electrode line

The described negative select lines of carrying OV current potential starts the described PMOS pipe conducting of writing out, if described driving PMOS pipe is in by duty, then only is no more than 1 electric current of receiving peace and enters described OLED luminescent layer drive electrode via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line, described drive electrode line from described drain-gate utmost point connecting line; If described driving PMOS pipe is in linear working state, then allow to be no more than 100 electric currents of receiving peace and enter described OLED luminescent layer drive electrode via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line, described drive electrode line from described drain-gate utmost point connecting line

Subordinate phase: finish entering the 2nd of video data signal after the 1st write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 2nd of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 1500 to 2000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 1500 to 2000 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

Phase III: finish entering the 3rd of video data signal after the 2nd write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 3rd of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 750 to 1000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 750 to 1000 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

Quadravalence section: finish entering the 4th of video data signal after the 3rd write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 4th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 350 to 500 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 350 to 500 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

Five-stage: finish entering the 5th of video data signal after the 4th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 5th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 150 to 250 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 150 to 250 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

The 6th stage: finish entering the 6th of video data signal after the 5th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 6th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 75 to 150 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 75 to 150 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

The 7th stage: finish entering the 7th of video data signal after the 6th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 7th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 35 to 100 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 35 to 100 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

The 8th stage: finish entering the 8th of video data signal after the 7th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 8th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 15 to 50 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 15 to 50 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

The 9th stage: finish entering the blank screen signal after the 8th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, 1 to 2 microsecond is simultaneously imported the constant potential value that is not less than 3.3V on the described video data serial bit line in the time

The described positive select lines of carrying OV current potential starts the described PMOS pipe conducting of reading in, the constant potential value that is not less than 3.3V of carrying on the described video data serial bit line is through the described PMOS of reading in pipe source electrode line, the described PMOS pipe that reads in, described drain-gate utmost point connecting line, PIP bottom electrode line imports described PIP capacitor into to be stored, and described drain-gate utmost point connecting line starts described driving PMOS pipe and enters by duty, enter and only allow to be no more than 1 electric current of receiving peace by the described driving PMOS of duty pipe and flow to described source-drain electrode connecting line via described driving PMOS pipe from described the drivings PMOS pipe line that drains

2) 250 to 350 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 250 to 350 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

The described negative select lines of carrying OV current potential starts the described PMOS pipe conducting of writing out, and described driving PMOS pipe is in by duty, then only is no more than 1 electric current of receiving peace and enters described OLED luminescent layer drive electrode from described drain-gate utmost point connecting line via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line, described drive electrode line.

Beneficial effect

A kind of silica-based OLED display chip image element circuit structure of the present invention and driving method thereof adopt monocrystalline silicon CMOS process technique to realize, compare existing LTPS TFT backplane technology and possess following advantage:

1) monocrystalline silicon has advantages such as carrier mobility height, threshold voltage be stable, picture element matrix and peripheral driving circuit etc. all can be integrated on the display screen, reduces the volume and the cost of whole display system greatly;

2) monocrystalline silicon CMOS substrate production standard process flow, the processing charges that only need pay small amount just can prepare substrate on the monocrystalline silicon CMOS of any tame standard substrate production line;

3) each Pixel Dimensions can be fabricated onto below 10 microns on the miniature display chip of silica-based OLED, thereby has only 1/10th of conventional OLED pixel size to arrive one of percentage, helps increasing substantially of display resolution;

4) adopt the substrate chip of CMOS integrated circuit technique manufacturing to belong to low energy-consumption electronic device, the application of silica-based OLED miniscope spare can be expanded in the portable demonstration product, thus the serviceable life of prolongation battery.

5) described ground wire protection PMOS guarantees that the voltage difference that card a kind of silica-based OLED display chip image element circuit structure of the present invention is born is no more than the magnitude of voltage that is carried on the described power lead, by the public electrode current potential of OLED luminescent layer being applied the method for negative voltage, just realized that low pressure monocrystalline silicon CMOS technology finishes the purpose of high drive OLED luminescent layer;

Description of drawings

Fig. 1 is a kind of silica-based OLED display chip image element circuit structure of the present invention, wherein:

(1) power lead (2) reads in PMOS pipe source electrode line

(3) read in PMOS pipe source electrode (4) and read in the PMOS pipe

(5) read in PMOS pipe drain electrode (6) PIP capacitor low-resistance polysilicon top electrode

(7) PIP top electrode line (8) PIP capacitor high resistance polysilicon bottom electrode

(9) PIP capacitor (10) PIP bottom electrode line

(11) drain-gate utmost point connecting line (12) drives the PMOS pipe

(13) drive the gate pmos utmost point (14) and drive PMOS pipe source electrode line

(15) drive PMOS pipe source electrode (16) and drive the drain electrode of PMOS pipe

(17) source-drain electrode connecting line (18) writes out PMOS pipe source electrode

(19) write out PMOS pipe (20) and write out the drain electrode of PMOS pipe

(21) write out PMOS pipe drain electrode line (22) video data serial bit line

(23) read in the gate pmos utmost point (24) and read gate pmos utmost point connecting line

(25) the capable select lines of positive (26) writes out the gate pmos utmost point

(27) the capable select lines of negative (28) writes out gate pmos utmost point line

(29) ground wire protection PMOS pipe source electrode line (30) ground wire protection PMOS pipe source electrode

(31) ground wire protection PMOS pipe (32) ground wire protection PMOS pipe drain electrode

(33) ground wire protection PMOS pipe drain electrode line (34) the ground wire protection gate pmos utmost point

(35) ground wire protection gate pmos utmost point line (36) OV ground wire

(37) drive electrode connecting line (38) OLED luminescent layer drive electrode

Fig. 2 is the phase one control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Fig. 3 is the subordinate phase control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Fig. 4 is the phase III control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Fig. 5 is the quadravalence section control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Fig. 6 is the five-stage control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Fig. 7 is the 6th a stage control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Fig. 8 is the 7th a stage control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Fig. 9 is the 8th a stage control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Figure 10 is the 9th a stage control flow chart of a kind of silica-based OLED display chip image element circuit driving method of the present invention,

Embodiment

Be further described in detail below in conjunction with 1 pair of a kind of silica-based OLED display chip image element circuit structure of the present invention of accompanying drawing:

Described silica-based OLED display chip image element circuit structure comprises: at least by read in PMOS pipe source electrode (3) and read in the gate pmos utmost point and read in that PMOS pipe drain electrode (5) constitutes read in PMOS pipe (4), at least the PIP capacitor (9) that constitutes by PIP capacitor low-resistance polysilicon top electrode (6) and PIP capacitor high resistance polysilicon bottom electrode (8), at least by driving PMOS pipe source electrode (15) and driving the gate pmos utmost point (13) and drive the driving PMOS pipe (12) that PMOS pipe drain electrode (16) constitutes, at least by write out PMOS pipe source electrode (18) and write out the gate pmos utmost point (26) and write out that PMOS pipe drain electrode (20) constitutes write out PMOS pipe (19), at least the ground wire of protecting the gate pmos utmost point (34) and ground wire protection PMOS pipe drain electrode (32) to constitute by ground wire protection PMOS pipe source electrode (30) and ground wire is protected PMOS pipe (31), by reading in the video data serial bit line (22) that PMOS pipe source electrode line (2) is connected with the described PMOS of reading in pipe source electrode (3), connect PIP top electrode line (7) simultaneously and drive the power lead (1) that PMOS manages source electrode line (14), manage the OV ground wire (36) that drain electrode (32) is connected by ground wire protection PMOS pipe drain electrode line (33) with described ground wire protection PMOS, read in the capable select lines of positive (25) that the gate pmos utmost point (23) is connected by reading in gate pmos utmost point line (24) with described, write out the capable select lines of negative (27) that the gate pmos utmost point (26) is connected by writing out gate pmos utmost point line (28) with described, the OLED luminescent layer drive electrode (38) that is connected with drive electrode connecting line (37);

Described PIP top electrode line (7) is connected to described PIP capacitor low-resistance polysilicon top electrode (6);

Described driving PMOS pipe source electrode line (14) is connected to described driving PMOS pipe source electrode (15);

Described PIP capacitor high resistance polysilicon bottom electrode (8) is connected on the described PMOS of reading in pipe drain electrode (5) and the drain-gate utmost point connecting line (11) that the described driving gate pmos utmost point (13) is communicated with by PIP bottom electrode line (10);

Described driving PMOS pipe drain electrode (16) is connected by source-drain electrode connecting line (17) with the described PMOS of writing out pipe source electrode (18);

The described ground wire protection gate pmos utmost point (34), described ground wire protection PMOS pipe source electrode (30), the described PMOS of writing out pipe drain electrode (20) respectively by ground wire protection gate pmos utmost point line (35), ground wire protection PMOS pipe source electrode line (29), write out PMOS pipe drain electrode line (21) and be connected with described drive electrode connecting line (37);

Described power lead (1), the capable select lines of described positive (25), the capable select lines of described negative (27), described OV ground wire along continuous straight runs are provided with, and the connection of mutually disjointing;

Described video data serial bit line (22) vertically is provided with, and is not communicated with mutually with described power lead (1), the capable select lines of described positive (25), the capable select lines of described negative (27), described OV ground wire;

Described OLED luminescent layer drive electrode (38) is made above 99% aluminum metal by purity, and the area that described OLED luminescent layer drive electrode (38) covers is no more than 90% of described silica-based OLED display chip image element circuit structure area.

Described power lead (1) is gone up the constant potential value that carrying is not less than 3.3V;

Alternately carry high potential signal and low-potential signal in the described video data serial bit line (22), and described high potential signal numerical value is not less than the constant potential value that is not less than 3.3V that described power lead (1) is gone up carrying, described low-potential signal numerical value is not higher than the numerical value than the low 0.5V of described high potential signal numerical value

The signal that carries on described positive select lines and the described negative select lines is the reverse voltage signal that do not overlap mutually.

Be further described in detail below in conjunction with accompanying drawing 2, accompanying drawing 3, accompanying drawing 4, accompanying drawing 5, accompanying drawing 6, accompanying drawing 7, accompanying drawing 8, accompanying drawing 9,10 pairs of a kind of silica-based OLED display chip image element circuit driving methods of the present invention of accompanying drawing:

The back circulation that powers on was finished as the next stage:

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously in the time described video data serial bit line (22) go up the 1st of inputting video data signal

The described positive select lines of carrying OV current potential starts described PMOS pipe (4) conducting of reading in, signal in the described video data serial bit line (22) is through the described PMOS pipe source electrode line (2) that reads in, the described PMOS pipe (4) that reads in, described drain-gate utmost point connecting line (11), PIP bottom electrode line (10) imports described PIP capacitor (9) into to be stored, be lower than the numerical value that hangs down 0.5V than the constant potential value that is not less than 3.3V of described power lead (1) carrying if import the numerical value of the signal of PIP capacitor (9) into from described video data serial bit line (22), then described drain-gate utmost point connecting line (11) starts described driving PMOS pipe (12) and enters linear working state, and the described driving PMOS pipe (12) that enters linear working state allows to be no more than 100 electric currents of receiving peace and flows to described source-drain electrode connecting line (17) from described driving PMOS pipe drain electrode line via described driving PMOS pipe (12); If from described video data serial bit line, (22) import the PIP capacitor into, the numerical value of signal (9) is not less than than described power lead, (1) goes up the numerical value that the constant potential value that is not less than 3.3V of carrying is hanged down 0.5V, then described drain-gate utmost point connecting line, (11) start described driving PMOS pipe, (12) enter by duty, enter described driving PMOS pipe by duty, (12) only allowing to be no more than 1 electric current of receiving peace manages via described driving PMOS from described driving PMOS pipe drain electrode line, (12) flow to described source-drain electrode connecting line, (17)

The described negative select lines that carrying is not less than the current potential of the potential value 0.5V that is carried on the described power lead (1) enters by duty by described gate pmos utmost point line (28) the described PMOS of the writing out pipe of startup (19) that writes out, entering the described PMOS of writing out pipe (19) by duty only allows to be no more than 1 electric current of receiving peace and manage (19) from described source-drain electrode connecting line (17) via the described PMOS of writing out and flow to the described PMOS of the writing out pipe line (21) that drains

2) 3000 to 4000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines input be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 3000 to 4000 microseconds are simultaneously imported the OV current potential on the described negative select lines in the time

Carrying is not less than described power lead, the described positive select lines of the current potential of the potential value 0.5V that is carried (1) starts the described PMOS of reading in pipe, (4) enter by duty, enter the described PMOS of reading in pipe by duty, (4) only allow to be no more than 1 and receive the electric current of peace or from the described PMOS of reading in pipe source electrode line, (2) via the described PMOS pipe that reads in, (4) flow to described drain-gate utmost point connecting line, (11) or from described drain-gate utmost point connecting line, (11) via the described PMOS pipe that reads in, (4) flow to the described PMOS of reading in pipe source electrode line, (2)

The described negative select lines of carrying OV current potential starts described PMOS pipe (19) conducting of writing out, if described driving PMOS pipe (12) is in by duty, then only is no more than 1 electric current of receiving peace and enters described OLED luminescent layer drive electrode (38) via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line (21), described drive electrode line from described drain-gate utmost point connecting line (11); If described driving PMOS pipe (12) is in linear working state, then allow to be no more than 100 electric currents of receiving peace and enter described OLED luminescent layer drive electrode (38) via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line (21), described drive electrode line from described drain-gate utmost point connecting line (11)

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously in the time described video data serial bit line (22) go up the 2nd of inputting video data signal

2) 1500 to 2000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 1500 to 2000 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously in the time described video data serial bit line (22) go up the 3rd of inputting video data signal

2) 750 to 1000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 750 to 1000 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously in the time described video data serial bit line (22) go up the 4th of inputting video data signal

2) 350 to 500 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 350 to 500 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously in the time described video data serial bit line (22) go up the 5th of inputting video data signal

2) 150 to 250 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 150 to 250 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously in the time described video data serial bit line (22) go up the 6th of inputting video data signal

2) 75 to 150 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 75 to 150 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously in the time described video data serial bit line (22) go up the 7th of inputting video data signal

2) 35 to 100 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 35 to 100 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously in the time described video data serial bit line (22) go up the 8th of inputting video data signal

2) 15 to 50 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 15 to 50 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

1) 1 to 2 microsecond of this stage after beginning input OV current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead (1) on the described negative select lines in the time, 1 to 2 microsecond simultaneously is the last constant potential value that is not less than 3.3V of importing of described video data serial bit line (22) in the time

The described positive select lines of carrying OV current potential starts described PMOS pipe (4) conducting of reading in, described video data serial bit line (22) is gone up the constant potential value that is not less than 3.3V of carrying through the described PMOS of reading in pipe source electrode line (2), the described PMOS pipe (4) that reads in, described drain-gate utmost point connecting line (11), PIP bottom electrode line (10) imports described PIP capacitor (9) into to be stored, and described drain-gate utmost point connecting line (11) starts described driving PMOS pipe (12) and enters by duty, entering described driving PMOS pipe (12) by duty only allows to be no more than 1 electric current of receiving peace and manages (12) from described drivings PMOS pipe drain electrode line via described driving PMOS and flow to described source-drain electrode connecting line (17)

2) 250 to 350 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead (1), 250 to 350 microseconds are simultaneously carried the OV current potential on the described negative select lines in the time

The described negative select lines of carrying OV current potential starts described PMOS pipe (19) conducting of writing out, and described driving PMOS pipe (12) is in by duty, then only is no more than 1 electric current of receiving peace and enters described OLED luminescent layer drive electrode (38) from described drain-gate utmost point connecting line (11) via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line, described drive electrode line.

In sum, the embodiment of the invention provides a kind of silica-based OLED display chip image element circuit structure and driving method thereof, by this method reduced the size in complete machine space and reduced Overall Power Consumption.

It will be appreciated by those skilled in the art that accompanying drawing is the synoptic diagram of a preferred embodiment, the invention described above embodiment sequence number is not represented the quality of embodiment just to description.

The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. silica-based OLED display chip image element circuit structure; it is characterized in that; at least by reading in PMOS pipe source electrode (3) and reading in PMOS (P-channel Metal Oxide Semiconductor; P type NMOS N-channel MOS N) tube grid and read in that PMOS pipe drain electrode (5) constitutes read in PMOS pipe (4); at least PIP (Poly Si-insulator-Poly Si, the polysilicon-insulating layer-polysilicon) capacitor that constitutes by PIP capacitor low-resistance polysilicon top electrode (6) and PIP capacitor high resistance polysilicon bottom electrode (8); at least by driving PMOS pipe source electrode (15) and driving the gate pmos utmost point (13) and drive the driving PMOS pipe (12) that PMOS pipe drain electrode (16) constitutes; at least by write out PMOS pipe (19) source electrode (18) and write out PMOS pipe (19) grid and write out that PMOS pipe (19) drain electrode constitutes write out PMOS pipe (19); at least the ground wire of protecting the gate pmos utmost point (34) and ground wire protection PMOS pipe drain electrode (32) to constitute by ground wire protection PMOS pipe source electrode (30) and ground wire is protected PMOS pipe (31); by reading in the video data serial bit line (22) that PMOS pipe source electrode line (2) is connected with the described PMOS of reading in pipe source electrode (3); connect PIP top electrode line (7) simultaneously and drive the power lead (1) that PMOS manages source electrode line (14); manage the OV ground wire that drain electrode (32) is connected by ground wire protection PMOS pipe drain electrode line (33) with described ground wire protection PMOS; read in the capable select lines of positive (25) that the gate pmos utmost point (23) is connected by reading in gate pmos utmost point line with described; manage the capable select lines of negative (27) that (19) grid is connected by writing out PMOS pipe (19) gate trace with the described PMOS of writing out; the OLED luminescent layer drive electrode (38) that is connected with drive electrode connecting line (37).

2. a kind of silica-based OLED display chip image element circuit structure according to claim 1; it is characterized in that; described PIP top electrode line (7) is connected to described PIP capacitor low-resistance polysilicon top electrode (6); described driving PMOS pipe source electrode line (14) is connected to described driving PMOS pipe source electrode (15); described PIP capacitor high resistance polysilicon bottom electrode (8) is connected on the described PMOS of reading in pipe drain electrode (5) and the drain-gate utmost point connecting line (11) that the described driving gate pmos utmost point (13) is communicated with by PIP bottom electrode line (10); described driving PMOS pipe drain electrode (16) is managed (19) source electrode (18) with the described PMOS of writing out and is connected by source-drain electrode connecting line (17), the described ground wire protection gate pmos utmost point (34); described ground wire protection PMOS pipe source electrode (30); the described PMOS pipe (19) that writes out drains respectively by ground wire protection gate pmos utmost point line (35); ground wire protection PMOS pipe source electrode line (29); writing out PMOS pipe (19) drain electrode line is connected with described drive electrode connecting line (37).

3. a kind of silica-based OLED display chip image element circuit structure according to claim 1, it is characterized in that, described power lead (1), the capable select lines of described positive (25), the capable select lines of described negative (27), described OV ground wire along continuous straight runs are provided with, and the connection of mutually disjointing.

4. a kind of silica-based OLED display chip image element circuit structure according to claim 1, it is characterized in that, described video data serial bit line (22) vertically is provided with, and is not communicated with mutually with described power lead (1), the capable select lines of described positive (25), the capable select lines of described negative (27), described OV ground wire.

5. a kind of silica-based OLED display chip image element circuit structure according to claim 1, it is characterized in that, described OLED luminescent layer drive electrode (38) is made above 99% aluminum metal by purity, and the area that described OLED luminescent layer drive electrode (38) covers is no more than 90% of described silica-based OLED display chip image element circuit structure area.

6. a kind of silica-based OLED display chip image element circuit structure according to claim 3 is characterized in that, described power lead (1) is gone up the constant potential value that carrying is not less than 3.3V.

7. a kind of silica-based OLED display chip image element circuit structure according to claim 3, it is characterized in that, alternately carry high potential signal and low-potential signal in the described video data serial bit line (22), and described high potential signal numerical value is not less than the constant potential value that is not less than 3.3V that described power lead (1) is gone up carrying, described low-potential signal numerical value is not higher than the numerical value than the low 0.5V of described high potential signal numerical value, and the signal that carries on described positive select lines and the described negative select lines is the reverse voltage signal that do not overlap mutually.

8. a kind of silica-based OLED display chip image element circuit structure according to claim 1 is characterized in that, described a kind of silica-based OLED display chip image element circuit structure adopts the PMOS making technology to produce realization on the n type single crystal silicon substrate.

9. be suitable for a kind of silica-based OLED display chip image element circuit driving method of the present invention, it is characterized in that, comprise that powering on back circulation finishes as the next stage:

The described negative select lines that carrying is not less than the current potential of the potential value 0.5V that is carried on the described power lead (1) manage (19) gate trace by the described PMOS of writing out and is started the described PMOS of writing out and manage (19) and enter by duty, entering the described PMOS of writing out pipe (19) by duty only allows to be no more than 1 electric current of receiving peace and manage (19) from described source-drain electrode connecting line (17) via the described PMOS of writing out and flow to the described PMOS of writing out pipe (19) line that drains

The described negative select lines of carrying OV current potential starts described PMOS pipe (19) conducting of writing out, if described driving PMOS pipe (12) is in by duty, then only is no more than 1 electric current of receiving peace and enters described OLED luminescent layer drive electrode (38) via the described PMOS of writing out, the described PMOS of writing out pipe (19) drain electrode line, described drive electrode line from described drain-gate utmost point connecting line (11); If described driving PMOS pipe (12) is in linear working state, then allow to be no more than 100 electric currents of receiving peace and enter described OLED luminescent layer drive electrode (38) via the described PMOS of writing out, the described PMOS of writing out pipe (19) drain electrode line, described drive electrode line from described drain-gate utmost point connecting line (11)

The described negative select lines that carrying is not less than the current potential of the potential value 0.5V that is carried on the described power lead (1) manage (19) gate trace by the described PMOS of writing out and is started the described PMOS of writing out and manage (19) and enter by duty, entering the described PMOS of writing out pipe (19) by duty only allows to be no more than 1 electric current of receiving peace and manage (19) from described source-drain electrode connecting line (17) via the described PMOS of writing out and flow to the described PMOS of the writing out pipe line (21) that drains

Carrying is not less than described power lead, the described positive select lines of the current potential of the potential value 0.5V that is carried (1) starts the described PMOS of reading in pipe, (4) enter by duty, enter the described PMOS of reading in pipe by duty, (4) only allow to be no more than 1 and receive the electric current of peace or from the described PMOS of reading in pipe source electrode line, (2) via the described PMOS pipe that reads in, (4) flow to described drain-gate utmost point connecting line, (11) or from described drain-gate utmost point connecting line, (11) via the described PMOS pipe that reads in, (4) flow to the described PMOS of reading in pipe source electrode, (3) line, (2)