CN102074192A

CN102074192A - Driving circuit for display

Info

Publication number: CN102074192A
Application number: CN201010623513XA
Authority: CN
Inventors: 郭海成; 代永平; 凌代年; 邱成峰; 彭华军; 黄飚
Original assignee: GUANGDONG ZHONGXIAN TECHNOLOGY Co Ltd
Current assignee: GUANGDONG ZHONGXIAN TECHNOLOGY Co Ltd
Priority date: 2010-12-29
Filing date: 2010-12-29
Publication date: 2011-05-25

Abstract

The invention discloses a driving circuit for a display, which comprises a pixel unit circuit matrix, a row driver circuit, a column driver circuit, a frequency division shunt circuit, a Vcom inversion switch circuit and an organic light emitting diode (OLED) luminescent layer test area, wherein the column driver circuit is divided into upper and lower groups of circuits which are in mirror symmetry to drive odd and even data lines respectively; and a row scanning driver is positioned on the left part of the driving circuit and is provided with 606 driving units, and the driving units are controlled synchronously according to a frame trigger clock pulse and a scanning clock pulse to be driven sequentially.

Description

A kind of circuit of display driving

Technical field

The application relates to the microelectronics display technique, and more specifically, the application relates to a kind of silica-based OLED display screen and driving circuit.

Background technology

(Organic Light Emitting Diode OLED) is current driving apparatus to Organic Light Emitting Diode, requires back plane circuitry that accurate, stable Current Control can be provided.What active backboard in early days adopted is that (amorphous silicon, a-Si) TFT technology still owing to the low reasons such as instability that reach threshold voltage of mobility of amorphous silicon, make its not achieving success to amorphous silicon.Compare amorphous silicon, low temperature polycrystalline silicon (Low Temperature Poly-Silicon, LTPS) mobility of TFT is much higher, but still there is the inconsistent problem of homogeneity in threshold voltage, so need carry out certain circuit compensation in the design of image element circuit, what present existing OLED display major part adopted all is LTPS TFT backplane technology.And aspect large scale OLED volume production, the manufacturing technology of LTPS is still immature, does not have unified standard production line, prepare LTPS TFT backboard and must throw huge fund construction special production line.

Silica-based OLED miniscope spare adopts monocrystalline silicon CMOS substrate technology, compare other substrate technology, monocrystalline silicon has the carrier mobility height, advantages such as threshold voltage is stable, can all be integrated in picture element matrix and peripheral driving circuit etc. on the display screen, reduce the volume and the cost of whole display system greatly, mature C MOS integrated circuit technology is also provided convenience for the substrate manufacture of silica-based OLED miniscope spare simultaneously, and monocrystalline silicon CMOS substrate production standard process flow, the processing charges that only need pay small amount just can prepare substrate on the monocrystalline silicon CMOS of any tame standard substrate production line; Each elemental area on the silica-based oled substrate can be done very for a short time simultaneously, is beneficial to the raising of display resolution.In the design of monocrystalline silicon CMOS substrate chip, what mainly consider is how accurately the electric current of OLED is flow through in control, thereby realizes that good gray scale image shows.Chip power-consumption is also extremely important simultaneously, shows that by the regular handset powered battery, low consumption circuit can prolong the serviceable life of battery because silica-based OLED miniscope spare also just can be used for the portable near eye.

Summary of the invention

Electric current and reduction circuit power consumption for accurately controlling OLED overcome the defective that above-mentioned existing LTPS TFT backboard image element circuit exists, and the application provides a kind of a kind of silica-based OLED display screen and driving circuit of based single crystal silicon CMOS substrate technology.

An aspect according to the application provides a kind of circuit of display driving, comprising: pixel unit circuit matrix, row driver circuits, column driver circuit, frequency division current divider circuit, Vcom inversion switching circuit and OLED luminescent layer test section; Wherein column driver circuit is divided into two groups of circuit up and down of mirror image symmetry, drives the odd and even data line respectively; Wherein, described line scanning driver is positioned at the left part of driving circuit, has 606 driver elements, triggers clock and the control of scan clock impulsive synchronization according to frame, drives successively.

In sum,, can reduce the size in complete machine space, reduce Overall Power Consumption by using the present invention.

Description of drawings

Fig. 1 illustrates according to display screen area synoptic diagram of the present invention;

Fig. 2 illustrates the synoptic diagram in width modulation frame period time-division;

Fig. 3 illustrates the illustrative view of functional configuration of display screen;

Fig. 4 illustrates the synoptic diagram of pixel unit circuit;

Fig. 5 illustrates the synoptic diagram of line scanner circuit;

Fig. 6 illustrates the synoptic diagram of column scan device circuit;

Fig. 7 illustrates the synoptic diagram of level shifter circuit;

Fig. 8 illustrates the synoptic diagram of frequency division current divider circuit;

Fig. 9 illustrates the synoptic diagram of Vcom inversion switching circuit;

Figure 10 illustrates the artwork distributing of structure shown in Figure 3;

Figure 11 illustrates the detailed structure of image element circuit shown in Figure 4.

Embodiment

Below in conjunction with the drawings and specific embodiments a kind of silica-based OLED display screen provided by the invention and driving circuit are described in detail.

Specification for the described monochromatic OLEDoS display chip of the application (SVGA), its general feature comprises: monochromatic silica-based OLED (OLEDoS) display chip has 864 * 606 pixel resolutions, realize that according to the time-division PWM mode gray scale shows, in order to nearly eye display application.The video signal of importing this chip is a 16b field data stream, and promptly according to the difference setting of sub-number of fields order from 1-8, gray scale can realize that 2-256 level gray scale shows.The electronegative potential of the digital signal that the OLEDoS chip can be imported is V _L, can get 0V, noble potential is V _H, can get 3.3V.

Generally speaking, the feature that has of the application's display chip comprises: be suitable for the monochromatic SVGA pixel resolution that shows purposes; A setting can be carried out the demonstration of 2-256 level gray scale according to interface circuit input signal; Adopt CMOS technology to realize OLED luminescent layer load driving; The duty of OELD luminescent layer driving tube can be free external in the pixel cell; The OLED luminescent layer has been realized the pulsed drive pattern; The requirement of no fixed pixel clock setting forms the video Data Transmission passage; Integrated ranks driver on the OLEDoS chip is comprising input signal buffer circuit module, voltage distribution circuit module, interface electrostatic protection circuit module, divider circuit module, line storage module etc.; Display image can be followed the input data entry mode and be carried out symmetrical minute surface conversion.

Fig. 1 illustrates the planning chart of display screen area, and as shown in Figure 1, this zone comprises cutting area and cloth map-area, comprises pad area, seal area and design pixel region in the cloth map-area, and the design pixel region is the viewing area just.Be of a size of the optimal size of design shown in the figure, but this is not the restriction for the application's function zoning, in the layout-design of reality, can adjust according to the demonstration needs, and, can change the size design of cloth map-area and cutting area according to the division of electric function.

In the embodiment shown in fig. 1, this cloth map-area by cutting area all around around, pad area is positioned at the left side of cloth map-area, pad area area occupied in the cloth map-area is little, becomes the vertical bar shape, the cutting area direct neighbor in pad area and left side along the cutting area in left side.The design pixel region accounts for most of area of cloth map-area, is centered on by seal area around the design pixel region, will design pixel region and pad area and cutting area and isolate.Seal area is at right side and cutting area direct neighbor.Seal area the left side pad area and the design pixel region between.

In a preferred embodiment, chip type is two trap CMOS processing chips; Function type is a full digital; Application approach is the silica-based OLED miniscope of time-division PWM mode; Driving load is OLED organic light emitting film layer; The pixel count of design pixel region is 864 * 606 (523,584 pixels); Pel spacing: 15 μ m * 15 μ m; Display area: 12.96mm H * 9.09mm V (0.62 inch); Total chip area: 17.00mm H * 13.00mm V (0.84 inch).

The application's OLEDoS display chip adopts time-division width modulation gray scale display mode, its ultimate principle is that the utilization human eye retina omits the physical influence that in the time range brightness sensation is had the time integral of being similar to temporarily in vision, every frame image data is divided into n (n=1-8) height field (Sub-Fields), corresponding different weights of the time of lighting of each son pixel, modulation by OLEDoS display chip pixel unit circuit drives process, OLED light-emitting zone in each pixel region is controlled at " bright " and " secretly " two states, can adopt binary representation, so just be combined into 2 ⁿNumber of greyscale levels.

Time period of the corresponding segment base of each of each binary gray-scale value two weights, and be revealed by the corresponding time, thus the human eye retina received be a series of light pulse.Because light pulse is the microsecond level, omit the time (about 20ms) temporarily much smaller than vision, human eye view nerve can not be distinguished each light pulse, and the light intensity that the view nerve is experienced is the result behind these light pulse integrations.

Fig. 2 illustrates width modulation frame period time-division, and as shown in Figure 2, value is the pixel displayed value of 10110 scale-of-two 32 number of greyscale levels, wherein 1 represents ON state, and 0 represents OFF state; The demonstration time interval of supposing the lowest order correspondence is 1, so from right to left second and third, time interval of four, five are respectively 2,4,8,16, the time that ON state shows is: 16+0+4+2+0=22, so the light intensity that human eye is experienced is 22/ (16+8+4+2+1)=22/31 of complete bright attitude intensity.

Suppose n=8, then can realize 256 number of greyscale levels, refer to that here every two field picture is divided into 8 son fields, each son fluorescent lifetime is corresponding with the weights proportion of data bits, promptly obtains formula (1):

SF8∶SF7∶SF6∶SF5∶SF4∶SF3∶SF2∶SF1＝27∶26∶25∶24∶23∶22∶21∶20(1)

Cut apart every the effective fluorescent lifetime Teff of pixel by number of greyscale levels 2n, then the demonstration time tn of a n son SFn follows formula (2):

t^{n} = \frac{2^{n - 1} T_{eff}}{2^{n} - 1}

So, the bright attitude time T p in every two field picture pixel follows formula (3):

Tp = {(Σ_{n = 8} B 2^{n - 1})}^{\frac{Teff}{2^{n} - 1}}

Wherein B is a bit location, and this bit value is 0,1, determines that respectively being in dark attitude at the SFn interior pixel still is bright attitude.

8 time-division width modulation gray scale display mode estimations

In hypothesis is zero ideally the OLED response time, and in the merotype sequential, 75Hz is corresponding to 13.333ms during 8 of 800 * 600 resolution, i.e. 13333 μ s, 1 μ s writes 1 row, write full one with 600 μ s, the write time of a width of cloth figure is 600 * 8=4800 μ s.Effectively the demonstration time is 13333-4800=8533 μ s, is divided into 255 parts, every part of 8533/255=33 μ s, and effectively the fluorescent lifetime dutycycle is 8533/13333=64%.Consider the pattern that writes line by line, recomputating effective time is 13333-8=13325 μ s, is divided into 255 parts and is 13325/255=52 μ s, and effectively the fluorescent lifetime dutycycle is 13324/13333=99.9%.Consider the factors such as life-span of OLED in the practical application, add the current potential counter-rotating and deceive the field, 8 son fields are increased to 9 son fields.

Outside parallel 16 bit data incoming frequencies are 50M, consider that the actual physics pixel is 864 * 606, and behind the black field of insertion, actual sequential is as follows:

Write for 1 used time of row: 864 * 20ns/16=1.08 μ s

Write full 1 place and use the time: 1.08 μ s * 606=655 μ s

Effective demonstration time: 13333 μ s-(655 μ s * 9)=7438 μ s

Be divided into 255 parts: 7438 μ s/255=29.169 μ s are adjusted into: 28 μ s

A black demonstration time: 7438 μ s-(28 * 255) μ s=298 μ s

Effective fluorescent lifetime dutycycle: (7438 μ s-298 μ s)/13333 μ s=53.6%

The cycle of each another arena: 28 * 128=3584 μ s; 28 * 64=1792 μ s; 28 * 32=896 μ s; 28 * 16=448 μ s; 28 * 8=224 μ s; 28 * 4=112 μ s; 28 * 2=56 μ s; 28 μ s; Black field=298 μ s.

Fig. 3 is the synoptic diagram according to the driving circuit of display of the present invention, and as shown in Figure 3, wherein the OLEDoS display chip adopts two trap CMOS silicon device technologies, and it is integrated with substrate that input video digital processing circuit and pixel cell OLED luminescent layer drive array.Requirement according to the front display performance, Fig. 3 has illustrated to comprise the circuit structure of whole OLEDoS chip: pixel unit circuit matrix, row driver circuits, column driver circuit, frequency division current divider circuit, Vcom inversion switching circuit and OLED luminescent layer test section.

In order to reduce working frequency of chip, not only row driver is divided into two groups of circuit up and down of electricity structure mirror image symmetry, drive the odd and even data line respectively, and adopt the frequency division current divider circuit to realize the mode of 32 groups of data parallel input pixel cell display matrixes.In addition, the sort circuit structure can make chip area diminish, the display effect equilibrium.

The pixel unit circuit matrix comprises a plurality of pixel unit circuits, and wherein Fig. 4 illustrates a pixel unit circuit.Pixel unit circuit comprise 4 PMOS pipe (P2 among Fig. 4 P3 P4 P5), be used for providing the driving pulse electric current to the OLED luminescent layer, the accumulation by current pulse width realizes gray modulation.

As shown in Figure 4; P2 is as the driving tube of OLED luminescent layer; P3 is a matrix of pixel cells search switch pipe, and P4 is the driving switch pipe, and P5 is the pixel unit circuit protection tube; C1 is a holding capacitor; SV and SVB are that a pair of the overlapping mutually obtains scanning address signal, and VD is a digital video position signal, and wherein VDH is " secretly " signal; VDL is " bright " signal, Vcom is-and the common potential of 3V.

Wherein, the drain electrode of P2 connects power supply VCC, connects capacitor C 1 between the grid of P2 and the VCC, and the source class of P2 connects the drain electrode of P4.The grid of P2 connects the drain electrode of P3, and the source class of P3 connects VD, and the grid of P3 connects scanning address signal SV.The grid of P4 connects scanning address signal SVB, and the source class of P4 is connected to the OLED luminescent layer to Vcom.The source class of P4 also connects grid and the source class of P5, the grounded drain of P5.

When scanning address signal SV was low level, P3 managed conducting, and VD discharges and recharges C1, and when charging into the VDH current potential, the P2 driving tube is operated in cut-off state, does not promptly provide drive current to the OLED luminescent layer; When charging into the VDL current potential, the P2 driving tube is operated in the subthreshold value state, promptly to the OLED luminescent layer provide tens receive the peace little drive current.

In P3 conduction period, P4 ends, thereby prevents that the transient current that produces when P2 driving tube duty changes from exciting the OLED luminescent layer unexpected scintillation to occur.After P3 ended from the VD sampling, P4 is conducting immediately; PMOS pipe P5 is as the protection tube of pixel unit circuit, and when the output potential of P4 pipe was lower than 0V, P5 began conducting, thus can keep P1 P2 P3 P4 to apply potential difference (PD) be 5V.See through OLED luminescent layer Vcom public electrode access-3V current potential, the maximum voltage that finally can be applied on the OLED luminescent layer is 8V, thereby has reached the purpose of use low voltage cmos processing chip driving high voltage (such as 8V) OLED luminescent layer.

Fig. 5 illustrates the circuit structure of line scanner circuit.The line scanning driver of display chip circuit is positioned at the chip left side, and it has 606 driver elements, triggers clock Vs and scan clock pulse RCK synchro control according to frame, and they drive to a last row successively from first row.

As shown in Figure 5, row driver circuits is by horizontal shifting register, and level shifter and scanning buffer driver are formed.Horizontal shifting register is 606 bit shift register of a single-phase input, triggers under the effect of clock Vs at horizontal displacement pulse RCK and frame, produces the sweep signal from the 1st row to the 606th row successively.Sweep signal produces the scanning level of VL=0V/VH=5V by the effect of level shifter, further strengthens driving force by the scanning buffer driver, is used for 864 pixel unit circuit of each row of addressing.Specifically, horizontal shifting register scans i when capable, by the effect of this line scanning buffering driver, and 864 the PMOS switching tubes conducting that is connected with i bar scan electrode in the PEL matrix.Because be to line by line scan, at this moment other scan electrode is all the 5V current potential, and remaining PMOS switching tube all ends.Along with the effect of horizontal displacement pulse RCK, the scan electrode that is selected will change successively.

Fig. 6 illustrates the circuit structure of column scan device circuit.16 digital video signals of parallel input are divided into two 16 groups, to column scan device serial input digital video signal, under the vertical transfer register effect that seals in and go out, deposit the 1st grade of latch successively in.The 1st grade of latch is before reading in data, institute's deposit data is write the 2nd grade of latch, the 1st grade of latch is when reading in data then, the 2nd grade of latch writes out data by level shifter to the selection transmitter (STG) of storage signal numerical value simultaneously, these two groups of functions that latchs realization is write out while reading in.The 2nd grade of latch is filled with after the delegation under the read output signal effect, cooperate line scan signals, be input to the selection transmitter of each columns value simultaneously, then the one bit digital signal of every row convert to synchronously one regulation and control voltage signals (VH/VL) affact on the pixel, group effect then is that serial digital video signal changes into parallel video.The regulation and control voltage signal writes each picture element matrix line by line, drives 4 PMOS pipes collaborative work therebetween.

Fig. 7 illustrates the structure of level shifter circuit.Wherein, line driver still is all to have adopted level shifter in the circuit structure of row driver, its objective is by the control of standard 3.3V low logic voltage and realize the output of 5V high pressure, drive the work of pixel display matrix, do the power consumption that can reduce logical process partial circuit 55% in the chip like this.

Among Fig. 7, P1, P2 are the phase inverter of being made up of low-voltage device, are used to produce rp input signal

HVP1-4 and HVN1-4 adopt high-voltage CMOS technology to make, and these high tension apparatus are formed level and shifted and drive two circuit of buffering.The level displacement circuit principle of work: when in=5V, HVN2 and HVP1 conducting, HVN1 and HVP2 end, out=HVDD; On the contrary, during in=0V, out=0V.As seen, this circuit structure has realized that signal voltage is from the displacement of low level to high level.

Fig. 8 illustrates the structure of frequency division current divider circuit.As shown in Figure 8, this circuit module is made of frequency dividing circuit and divided circuit two parts.Frequency dividing circuit is the frequency halving of read clock pck, thereby makes the frequency of operation of whole display chip reduce by half.The built-in two stage latch of divided circuit, the two bits of finishing the serial input realizes running simultaneously input, the setting that has cooperated frequency of operation to reduce by half.

Fig. 9 illustrates the structure of Vcom inversion switching circuit.Inversion switching circuit comprises reverse signal input circuit, level displacement circuit, output buffers circuit three parts.The output voltage values of Vcom is 0V and 5V.Should be noted in the discussion above that owing to what adopt it is 5V_CMOS preparation technology, so the effective changing voltage of this switch is that 0V is between the 5V, if Vcom use-3V then needs external switch.

Figure 10 is the signal of artwork distributing.Wherein, the OLEDoS chip circuit is made up of ten thousand MOS transistor surplus 50, adopts one dimension Butut pattern reasonably to place these PMOS and NMOS, and cell layout comprises p type and p type two row of horizontal diffusion bar, the PMOS transistor is positioned at P type bar, and nmos pass transistor is positioned at n type bar.

Altogether the PMOS of grid pipe and NMOS pipe vertical alignment are placed, shared polycrystalline grid, it is right that a pair of like this PMOS pipe and NMOS pipe are called a transistor, and not altogether grid but a pair of PMOS of vertical alignment placement manages and the NMOS pipe to be also referred to as a transistor right.

The source-drain area of metal-oxide-semiconductor such as adjacent that links to each other in the circuit then links to each other with the diffusion region, is called the source and leaks sharedly, and a plurality of continuous arrangements and source are leaked shared metal-oxide-semiconductor and be called the diffusion chain and since metal-oxide-semiconductor usually P, N arrange in pairs, so the diffusion chain claims transistor to chain again.Power/ground is distributed in beyond the two draining riglets abreast.Gauze cloth beyond the power/ground is between P type and N type horizontal bar.

The chip layout structure should have following feature: PMOS pixel drive matrix can be considered the domain of a pixel unit and does 864 * 606 array expansion; Peripheral driving circuit also has one dimension height repeatability, and promptly each line scanning driver circuit structure is in full accord, and each row also is that circuit structure is in full accord.Therefore, as long as design a pixel symmetry repetitive body, press the two dimensional surface Butut then and then can for the PMOS display matrix; Peripheral driving circuit goes out the domain of row or delegation according to one dimension Butut pattern layout, and adjacent then row or column is made mirror and duplicated mutually, can make adjacent row or column common source line or ground wire like this, then can design the compactest domain.

The domain of design row or column adopts the core growth method.At first the pixel drive matrix being placed in the middle part of chip, is the correlation unit that core is placed row or column with these unit then, then is clock trees and input data line, expansion and growth around chip gradually, and whole the arrangement finishes until the unit.In addition, display chip to the position of PAD without limits, the position of then drawing contact can be depending on the arrangement result of chip internal unit.The headspace of accompanying pipe, test point, test circuit and Vcom public electrode is placed in last consideration again.

Figure 11 illustrates detailed silica-based OLED display chip image element circuit structure.Wherein, this silica-based OLED display chip image element circuit structure comprises: at least by reading in PMOS pipe source electrode and reading in PMOS (P-channel Metal Oxide Semiconductor; P type NMOS N-channel MOS N) tube grid and read in that PMOS pipe drain electrode constitutes read in the PMOS pipe; at least PIP (Poly Si-insulator-Poly Si, the polysilicon-insulating layer-polysilicon) capacitor that constitutes by PIP capacitor low-resistance polysilicon top electrode and PIP capacitor high resistance polysilicon bottom electrode; at least by driving PMOS pipe source electrode and driving the gate pmos utmost point and drive the driving PMOS pipe that the drain electrode of PMOS pipe constitutes; at least by write out PMOS pipe source electrode and write out the gate pmos utmost point and write out that the drain electrode of PMOS pipe constitutes write out the PMOS pipe; at least the ground wire protection PMOS that protects the gate pmos utmost point and the drain electrode of ground wire protection PMOS pipe to constitute by ground wire protection PMOS pipe source electrode and ground wire manages; by reading in the video data serial bit line that PMOS pipe source electrode line is connected with the described PMOS of reading in pipe source electrode; connect PIP top electrode line simultaneously and drive the power lead that PMOS manages the source electrode line; manage the 0V ground wire that drain electrode is connected by ground wire protection PMOS pipe drain electrode line with described ground wire protection PMOS; read in the capable select lines of positive that the gate pmos utmost point is connected by reading in gate pmos utmost point line with described; write out the capable select lines of negative that the gate pmos utmost point is connected by writing out gate pmos utmost point line with described; the OLED luminescent layer drive electrode that is connected with the drive electrode connecting line.

Described PIP top electrode line is connected to described PIP capacitor low-resistance polysilicon top electrode, and described driving PMOS pipe source electrode line is connected to described driving PMOS pipe source electrode; Described PIP capacitor high resistance polysilicon bottom electrode is connected on the drain-gate utmost point connecting line that the described PMOS of reading in pipe drains with the described driving gate pmos utmost point is communicated with by PIP bottom electrode line; The drain electrode of described driving PMOS pipe is connected by the source-drain electrode connecting line with the described PMOS of writing out pipe source electrode; The described ground wire protection gate pmos utmost point, described ground wire protection PMOS pipe source electrode, the drain electrode of the described PMOS of writing out pipe respectively by ground wire protection gate pmos utmost point line, ground wire protection PMOS pipe source electrode line, write out PMOS pipe drain electrode line and be connected with described drive electrode connecting line; Described power lead, the capable select lines of described positive, the capable select lines of described negative, described 0V ground wire along continuous straight runs are provided with, and the connection of mutually disjointing; Described video data serial bit line vertically is provided with, and is not communicated with mutually with described power lead, the capable select lines of described positive, the capable select lines of described negative, described 0V ground wire.

Described OLED luminescent layer drive electrode is made by metal or metal alloy, metal commonly used is aluminium, copper, gold, silver etc., but be not limited to that these are several, be to improve OLED stability and strengthen slin emissivity that surface of metal electrode can adopt chemical mechanical polishing method (CMP) to carry out polishing.The area that described OLED luminescent layer drive electrode covers is no more than 90% of described silica-based OLED display chip image element circuit structure area.Carrying is not less than the constant potential value of 3.3V on the described power lead; Alternately carry high potential signal and low-potential signal in the described video data serial bit line, and described high potential signal numerical value is not less than the constant potential value that is not less than 3.3V of carrying on the described power lead, and described low-potential signal numerical value is not higher than the numerical value than the low 0.5V of described high potential signal numerical value; The signal that carries on described positive select lines and the described negative select lines is the reverse voltage signal that do not overlap mutually; Described a kind of silica-based OLED display chip image element circuit structure adopts the PMOS making technology to produce realization on the n type single crystal silicon substrate.

For the described circuit of Figure 11, be provided for the driving method of described silica-based OLED display chip image element circuit structure, comprise as the next stage.

After powering on, circulation was finished as the next stage:

Phase one: the 1st input of video data signal, order is finished following two steps:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 1st of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

The described positive select lines of carrying 0V current potential starts the described PMOS pipe conducting of reading in, signal in the described video data serial bit line is through the described PMOS pipe source electrode line that reads in, the described PMOS pipe that reads in, described drain-gate utmost point connecting line, PIP bottom electrode line imports described PIP capacitor into to be stored, if the numerical value that imports the signal of PIP capacitor into from described video data serial bit line is lower than the numerical value that the constant potential value that is not less than 3.3V of carrying than described power lead is hanged down 0.5V, then described drain-gate utmost point connecting line starts described driving PMOS pipe and enters linear working state, and the described driving PMOS pipe that enters linear working state allows to be no more than 100 electric currents of receiving peace and flows to described source-drain electrode connecting line from described driving PMOS pipe drain electrode line via described driving PMOS pipe; If the numerical value that imports the signal of PIP capacitor into from described video data serial bit line is not less than the numerical value that the constant potential value that is not less than 3.3V of carrying than described power lead is hanged down 0.5V, then described drain-gate utmost point connecting line starts described driving PMOS pipe and enters by duty, enter and only allow to be no more than 1 electric current of receiving peace by the described driving PMOS of duty pipe and flow to described source-drain electrode connecting line via described driving PMOS pipe from described the drivings PMOS pipe line that drains

The described negative select lines that carrying is not less than the current potential of the potential value 0.5V that is carried on the described power lead enters by duty by the described described PMOS of the writing out pipe of gate pmos utmost point line startup that writes out, enter and only allow to be no more than 1 electric current of receiving peace by the described PMOS of writing out of duty pipe and flow to the described PMOS of writing out pipe drain electrode line via the described PMOS of writing out pipe from described source-drain electrode connecting line

2) 3000 to 4000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines input be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 3000 to 4000 microseconds are simultaneously imported the 0V current potential on the described negative select lines in the time

The described PMOS of the reading in pipe of described positive select lines startup that carrying is not less than the current potential of the potential value 0.5V that is carried on the described power lead enters by duty, enter and only allow to be no more than 1 by the described PMOS of reading in of duty pipe and receive the electric current of peace or flow to described drain-gate utmost point connecting line or flow to the described PMOS of reading in pipe source electrode line via the described PMOS of reading in pipe via the described PMOS of reading in pipe from described drain-gate utmost point connecting line from the described PMOS of reading in pipe source electrode line

The described negative select lines of carrying 0V current potential starts the described PMOS pipe conducting of writing out, if described driving PMOS pipe is in by duty, then only is no more than 1 electric current of receiving peace and enters described OLED luminescent layer drive electrode via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line, described drive electrode line from described drain-gate utmost point connecting line; If described driving PMOS pipe is in linear working state, then allow to be no more than 100 electric currents of receiving peace and enter described OLED luminescent layer drive electrode via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line, described drive electrode line from described drain-gate utmost point connecting line

Subordinate phase: finish entering the 2nd of video data signal after the 1st write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 2nd of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 1500 to 2000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 1500 to 2000 microseconds are simultaneously carried the 0V current potential on the described negative select lines in the time

Phase III: finish entering the 3rd of video data signal after the 2nd write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 3rd of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 750 to 1000 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 750 to 1000 microseconds are simultaneously carried the 0V current potential on the described negative select lines in the time

Quadravalence section: finish entering the 4th of video data signal after the 3rd write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 4th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 350 to 500 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 350 to 500 microseconds are simultaneously carried the 0V current potential on the described negative select lines in the time

Five-stage: finish entering the 5th of video data signal after the 4th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 5th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 150 to 250 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 150 to 250 microseconds are simultaneously carried the 0V current potential on the described negative select lines in the time

The 6th stage: finish entering the 6th of video data signal after the 5th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 6th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 75 to 150 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 75 to 150 microseconds are simultaneously carried the 0V current potential on the described negative select lines in the time

The 7th stage: finish entering the 7th of video data signal after the 6th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 7th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 35 to 100 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 35 to 100 microseconds are simultaneously carried the 0V current potential on the described negative select lines in the time

The 8th stage: finish entering the 8th of video data signal after the 7th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, the 8th of the inputting video data signal on the described video data serial bit line in the time of 1 to 2 microsecond simultaneously

2) 15 to 50 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 15 to 50 microseconds are simultaneously carried the 0V current potential on the described negative select lines in the time

The 9th stage: finish entering the blank screen signal after the 8th write phase of video data signal and write, finish following steps respectively:

1) 1 to 2 microsecond of this stage after beginning input 0V current potential on the described positive select lines in the time, 1 to 2 microsecond is simultaneously imported the current potential that is not less than the potential value 0.5V that is carried on the described power lead on the described negative select lines in the time, 1 to 2 microsecond is simultaneously imported the constant potential value that is not less than 3.3V on the described video data serial bit line in the time

The described positive select lines of carrying 0V current potential starts the described PMOS pipe conducting of reading in, the constant potential value that is not less than 3.3V of carrying on the described video data serial bit line is through the described PMOS of reading in pipe source electrode line, the described PMOS pipe that reads in, described drain-gate utmost point connecting line, PIP bottom electrode line imports described PIP capacitor into to be stored, and described drain-gate utmost point connecting line starts described driving PMOS pipe and enters by duty, enter and only allow to be no more than 1 electric current of receiving peace by the described driving PMOS of duty pipe and flow to described source-drain electrode connecting line via described driving PMOS pipe from described the drivings PMOS pipe line that drains

2) 250 to 350 microseconds after 10 to 800 microseconds of this stage after beginning in the time on the described positive select lines carrying be not less than the current potential of the potential value 0.5V that is carried on the described power lead, 250 to 350 microseconds are simultaneously carried the 0V current potential on the described negative select lines in the time

The described negative select lines of carrying 0V current potential starts the described PMOS pipe conducting of writing out, and described driving PMOS pipe is in by duty, then only is no more than 1 electric current of receiving peace and enters described OLED luminescent layer drive electrode from described drain-gate utmost point connecting line via the described PMOS of writing out, the described PMOS of writing out pipe drain electrode line, described drive electrode line.

It should be noted that at last above embodiment is only in order to describe technical scheme of the present invention rather than the present technique method is limited.

Claims

1. a circuit of display driving comprises: pixel unit circuit matrix, row driver circuits, column driver circuit, frequency division current divider circuit, Vcom inversion switching circuit and OLED luminescent layer test section; Wherein column driver circuit is divided into two groups of circuit up and down of mirror image symmetry, drives the odd and even data line respectively; Wherein, described line scanning driver is positioned at the left part of driving circuit, has 606 driver elements, triggers clock and the control of scan clock impulsive synchronization according to frame, drives successively.

2. the described driving circuit of claim 1, wherein, described row driver circuits comprises horizontal shifting register, level shifter and scanning buffer driver; Described horizontal shifting register is 606 bit shift register of single-phase input; Level shifter receives sweep signal, produces the scanning level, and strengthens driving force by the scanning buffer driver, comes 864 pixel unit circuit in each row of addressing.

3. the described driving circuit of claim 2, wherein, when described horizontal shifting register scans certain row, by the effect of this line scanning buffering driver, the PMOS switching tube conducting that the scan electrode corresponding with this row connects in the PEL matrix, thus the scan electrode that is selected changed.

4. the described driving circuit of claim 1, wherein, described column scan device circuit comprises vertical transfer register, first order latch, second level latch and selects transmitter; Wherein, vision signal is under the vertical transfer register effect that seals in and go out, deposit first order latch successively in, first order latch is before reading in data, institute's deposit data is write second level latch, first order latch is when reading in data then, and second level latch writes out data by level shifter to the selection transmitter of storage signal numerical value simultaneously.

5. the described driving circuit of claim 4, wherein, second level latch is filled with after the delegation under the read output signal effect, cooperates line scan signals, be input to the selection transmitter of each row, make the digital signal of every row convert the regulation and control voltage signal synchronously to and affact on the pixel.

6. the described driving circuit of claim 1, wherein, described frequency division current divider circuit is used to realize that 32 groups of data parallels are input to the pixel cell display matrix; Described pixel unit circuit matrix comprises a plurality of pixel unit circuits, and described pixel unit circuit comprises 4 PMOS pipes, is used for providing the driving pulse electric current to the OLED luminescent layer; Described pixel unit circuit is realized gray modulation by the accumulation of current pulse width.

7. the described driving circuit of claim 6, wherein, in the described pixel unit circuit; the effective driving tube of making the OLED luminescent layer of the one PMOS; the 2nd PMOS pipe is matrix of pixel cells search switch pipe, and the 3rd PMOS pipe is the driving switch pipe, and the 4th PMOS pipe is the pixel unit circuit protection tube.

8. the described driving circuit of claim 7, wherein, the drain electrode of a PMOS pipe connects power supply VCC, connects capacitor C1 between the grid of a PMOS pipe and the VCC, the source class of the one PMOS pipe connects the drain electrode of the 3rd PMOS pipe, and the grid of a PMOS pipe connects the drain electrode of the 2nd PMOS pipe; The source class of the 2nd PMOS pipe connects digital video bit signal VD, and the grid of the 2nd PMOS pipe connects scanning address signal SV; The grid of the 3rd PMOS pipe connects scanning address signal SVB, and the source class of the 3rd PMOS pipe is connected to the OLED luminescent layer to Vcom, and the source class of the 3rd PMOS pipe also connects the grid and the source class of the 4th PMOS pipe, the grounded drain of the 4th PMOS pipe.

9. the described driving circuit of claim 8, wherein, when scanning address signal SV was low level, the 2nd PMOS managed conducting, and VD discharges and recharges C1.

10. the described driving circuit of claim 9, wherein, when C1 was charged into noble potential, a PMOS pipe was operated in cut-off state, does not provide drive current to the OLED luminescent layer; When C1 was charged into electronegative potential, a PMOS pipe was operated in the subthreshold value state, to the OLED luminescent layer provide tens receive the peace little drive current.

11. the described driving circuit of claim 8 wherein, is managed conduction period at the 2nd PMOS, the 3rd PMOS pipe ends, and prevents that the transient current that produces when a PMOS plumber changes as state from exciting the OLED luminescent layer unexpected scintillation to occur.

12. the described driving circuit of claim 11, wherein, after the 2nd PMOS pipe ended from the VD sampling, the 3rd PMOS managed conducting immediately; The effective protection tube of making pixel unit circuit of the 4th PMOS, when the output potential of the 3rd PMOS pipe was lower than 0V, the 4th PMOS managed conducting, saw through OLED luminescent layer Vcom public electrode access-3V current potential, made that the maximum voltage that is applied on the OLED luminescent layer is 8V.