CN102055810B - Ethernet equipment port and link method thereof - Google Patents
Ethernet equipment port and link method thereof Download PDFInfo
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- CN102055810B CN102055810B CN 201010569161 CN201010569161A CN102055810B CN 102055810 B CN102055810 B CN 102055810B CN 201010569161 CN201010569161 CN 201010569161 CN 201010569161 A CN201010569161 A CN 201010569161A CN 102055810 B CN102055810 B CN 102055810B
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Abstract
The invention provides an Ethernet equipment port and a link method thereof. The port comprises a physical layer chip, an isolation transformer and a link control device, wherein the link control device comprises a first group of switches, a second group of switches and a switch control circuit; the first group of switches are used for connecting the receiving end of the physical layer chip with the receiving end of the isolation transformer, and connecting the transmitting end of the physical layer chip with the transmitting end of the isolation transformer; the second group of switches are used for connecting the receiving end of the physical layer chip with the transmitting end of the isolation transformer, and connecting the transmitting end of the physical layer chip with the receiving end of the isolation transformer; and the switch control circuit is used for controlling the switching-on and switching-off of the first group of switches and second group of switches according to the indication signals of the physical layer chip. The method comprises the following step: when the link of the Ethernet equipment port is unsuccessful, the link control device is used for performing forced cross reversal on straight lines or cross lines connected among Ethernet equipment ports until the link is successful.
Description
Technical field
The embodiment of the invention relates to networking technology area, relates in particular to a kind of ethernet device port and link method thereof.
Background technology
Can be connected with each other by connecting line between the ethernet device port.Connecting line can be divided into two kinds, and a kind of is direct-connected line, and a kind of is cross spider.Generally speaking, port less equipment such as router can be divided in data terminal equipment (Data Terminal Equipment, abbreviate as: DTE), the more equipment of ports such as Ethernet switch can be divided in data communications equipment, and (Data Communications Equipment abbreviates as: DCE).Be connected with each other by direct-connected line between DTE equipment on the Ethernet and the dce device, can be connected with each other by cross spider between two DTE equipment.
Fig. 1 is the connecting line schematic diagram that uses the RJ45 interface in the prior art, with the RJ45 interface not with the one side of buckle over against the paper outside, holding wire from left to right from 1 to 8 is numbered.The RJ45 interface pin is defined as follows: 1 is TX+, and data send anode; 2 is TX-, and data send negative terminal; 3 is RX+, the Data Receiving anode; 6 is RX-, the Data Receiving negative terminal.4,5,7 and 8 usefulness not are empty pin.In conjunction with RJ45 interface shown in Figure 1 following description is carried out in difference between direct-connected line and the cross spider.Fig. 2 is the line preface schematic diagram of direct-connected line two ends crystal head, and Fig. 3 is the line preface schematic diagram of cross spider two ends crystal head.Wherein direct-connected line and difference between the cross spider are that the line preface of the two ends crystal head of cross spider is: 1 is connected alternately with 3, and 2 are connected alternately with 6.
In realizing process of the present invention, the inventor finds that there are the following problems at least in the prior art:
If setting up when connecting between the ethernet device port, if direct-connected line and cross spider use wrong the time, and the ethernet device port at least one be operated under the compulsory mode problem that causes port to link.
Summary of the invention
The embodiment of the invention provides a kind of ethernet device port and link method thereof, in order to solve direct-connected line and cross spider use mistake in the prior art, and at least one is in the problem that the ethernet device port can't correctly link under the compulsory mode port of ethernet device, realized the AutoLink between the ethernet device port, simple, convenient, and effective save operation cost.
The embodiment of the invention provides a kind of ethernet device port, comprising: physical chip, isolating transformer and be connected the control device that is connected between described physical chip and the described isolating transformer;
Described connection control device comprises: first group of switch, second group of switch and ON-OFF control circuit;
Described first group of switch is used for the receiving terminal of physical chip is linked to each other with the receiving terminal of isolating transformer, and the transmitting terminal of physical chip is linked to each other with the transmitting terminal of isolating transformer;
Described second group of switch is used for the receiving terminal of physical chip is linked to each other with the transmitting terminal of isolating transformer, and the transmitting terminal of physical chip is linked to each other with the receiving terminal of isolating transformer;
Described ON-OFF control circuit is used for the index signal according to described physical chip, controls the break-make of first group of switch and second group of switch.
The embodiment of the invention also provides a kind of link method of ethernet device port, the ethernet device port is connected with each other by direct-connected line or cross spider, comprise: when the link of ethernet device port is unsuccessful, force the intersection counter-rotating by direct-connected line or cross spider that described connection control device will be connected between the ethernet device port, until linking successfully.
Ethernet device port and link method thereof that the embodiment of the invention provides, by being connected control device being provided with between physical chip and the isolating transformer, be connected to each other by different modes between the receiving terminal of the receiving terminal of this connection control device control physical chip and transmitting terminal and isolating transformer and the transmitting terminal, thereby realize that port working is under compulsory mode, direct-connected line and cross spider auto-reverse is until linking successfully.This programme has overcome direct-connected line and cross spider and used the problem that port can't link when wrong, and is simple, convenient, and effective save operation cost.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do one to the accompanying drawing of required use in embodiment or the description of the Prior Art below introduces simply, apparently, accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the connecting line schematic diagram that uses the RJ45 interface in the prior art;
Fig. 2 is the line preface schematic diagram of direct-connected line two ends crystal head in the prior art;
Fig. 3 is the line preface schematic diagram of cross spider two ends crystal head in the prior art;
The designs simplification schematic diagram of the ethernet device port that Fig. 4 provides for the embodiment of the invention;
The designs simplification schematic diagram of the ON-OFF control circuit that Fig. 5 provides for the embodiment of the invention;
The circuit diagram of the ON-OFF control circuit that Fig. 6 provides for the embodiment of the invention;
The link method flow chart of the ethernet device port that Fig. 7 provides for the embodiment of the invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
The designs simplification schematic diagram of the ethernet device port that Fig. 4 provides for the embodiment of the invention, as shown in Figure 4, this ethernet device port comprises: physical chip 1, isolating transformer 2 and be connected and be connected control device 3 between physical chip 1 and the isolating transformer 2.Wherein, connecting control device 3 comprises: first group of switch 31, second group of switch 32 and ON-OFF control circuit 33.First group of switch 31 is used for the receiving terminal RX of physical chip 1 is linked to each other with the receiving terminal RX of isolating transformer 2, and the transmitting terminal TX of physical chip 1 is linked to each other with the transmitting terminal TX of isolating transformer 2; Second group of switch 32 is used for the receiving terminal RX of physical chip 1 is linked to each other with the transmitting terminal TX of isolating transformer, and the transmitting terminal TX of physical chip 1 is linked to each other with the receiving terminal RX of isolating transformer 2; ON-OFF control circuit 33 is used for the index signal according to physical chip 1, controls the break-make of first group of switch 31 and second group of switch 32.
The designs simplification schematic diagram of the ON-OFF control circuit that Fig. 5 provides for the embodiment of the invention, as shown in Figure 5, this ON-OFF control circuit comprises: receiver module 331, control module 332, time delay module 333 and output module 334.Wherein, receiver module 331 is used to receive the index signal that physical chip 1 sends; Control module 332 is used for obtaining control signal according to index signal; Time delay module 333 is used for control signal is delayed time; Output module 334 is used for the control signal after the time-delay is exported to first group of switch 31 as first switch controlling signal, and exports to second group of switch 32 as the second switch control signal after the control signal negate after will delaying time.
Concrete, control module 332 comprises: first gating unit and second gating unit; First gating unit wherein is used for gating when index signal is first value, and control signal keeps initial value constant; Second gating unit is used for gating when index signal is second value, and control signal is the second switch control signal.First value wherein can be high level, and second value can be low level.Also have under a kind of mode, first value can be low level, and second value can be high level.
Concrete, time delay module 333 is the RC resistance-capacitance circuit.
ON-OFF control circuit with a kind of concrete form is described in detail below.The circuit diagram of ON-OFF control circuit as shown in Figure 6, wherein, the chip that specifically is applied to comprises: U1 is 74LVC125A, U2 is 74LVC14A.The concrete model of the chip that present embodiment is involved only is used for ON-OFF control circuit is described, and not in order to restriction protection scope of the present invention.The index signal of physical chip 1 can for indicate whether can LINK (link) status signal.Suppose that the LINK signal is a high level when physical chip 1 is in non-LINK state, the NOT LINK among corresponding Fig. 6 (link) is a low level.The LINK signal of this moment can control chip U1 4A-＞not conducting of 4Y passage, 3A-＞3Y passage conducting that the NOTLINK signal can control chip U1.Suppose that ON-OFF control circuit 33 receives index signal in n-hour, the control signal CTRL state of this moment is for just.
Behind the delay circuit that control signal CTRL forms through resistance R 15 and capacitor C 25, the 100ms that delayed time produces the first switch controlling signal SW_CTRLA, and also promptly when N+100ms, the SW_CTRLA signal is identical with the CTRL signal level, for just.
In this moment of N+100ms, SW_CTRLA becomes second switch control signal SW_CTRLB through the not gate of chip U2, and is opposite with the SW_CTRLA level simultaneously, for negative.
In this moment of N+100ms, SW _ TRLB signal upgrades the CTRL state by 3A-＞3Y path of U1 simultaneously, and with its counter-rotating, the CTRL signal is for negative.
Behind the delay circuit that control signal CTRL forms through resistance R 15 and capacitor C 25 again, the 100ms that delay time produces the first switch controlling signal SW_CTRLA, and also promptly when N+200ms, the SW_CTRLA signal is identical with the CTRL signal level, for bearing.
So circulation, the first switch controlling signal SW_CTRLA and second switch control signal SW_CTRLB are every will to reverse once through 100ms, and these two signals are controlled first group of switch and second group of switch respectively, make its continuous closure, disconnect.Wherein, can difference as required limiting the first switch controlling signal SW_CTRLA is high level interval scale closure, disconnects during low level, and second switch control signal SW_CTRLB is identical with being provided with of the first switch controlling signal SW_CTRLA.
And when physical chip 1 was in the LINK state, the LINK signal among Fig. 6 was a low level, and NOT LINK is a high level.The LINK signal of this moment can control chip U1 4A-＞4Y passage conducting, NOT LINK signal can control chip U1 3A-＞not conducting of 3Y passage, this just makes control signal CTRL not change, therefore the first switch controlling signal SW_CTRLA and second switch control signal SW_CTRLB also just are in stable state thereupon, can not reverse.
The ethernet device port that the embodiment of the invention provides, by being connected control device being provided with one between physical chip and the isolating transformer, this connection control device can constantly switch annexation between physical chip and isolating transformer receiving terminal and the transmitting terminal according to the index signal of physical chip, so that this ethernet device port is being under the forced working pattern, still can force to intersect and reverse, and the successful link between the realization port.This programme has overcome direct-connected line and cross spider and used the problem that port can't link when wrong, and is simple, convenient, and effective save operation cost.
The embodiment of the invention also provides a kind of link method of ethernet device port, and be connected with each other by direct-connected line or cross spider, this method comprises: when the link of ethernet device port is unsuccessful, force the intersection counter-rotating by direct-connected line or cross spider that the connection control device that provides in the foregoing description will be connected between the ethernet device port, until linking successfully.
Be described in detail below in conjunction with the link method of accompanying drawing this ethernet device port, the link method flow chart of ethernet device port as shown in Figure 7, this method comprises:
701: when the opposite end ethernet device is connected to the local terminal ethernet device by direct-connected line or cross spider, the auto-negotiation functionality of local terminal ethernet device its enable port.
702: whether the link of local terminal ethernet device port test is successful.
If success, execution in step 704;
If unsuccessful, execution in step 703.
703: the ethernet device port is forced the intersection counter-rotating by connecting control device with cross spider or direct-connected line, and returns step 702.
Concrete inversion mode can be with reference to above-mentioned port embodiment.
704: judge whether successful port is consulted automatically.
If success finishes;
If unsuccessful, execution in step 705.
705: the mode of operation of port is set to full duplex.
706: periodic statistics port status information.
707: judge whether the ultrashort bag in the port status information surpasses first threshold value.
If not, execution in step 706;
If, execution in step 708.
Wherein, ultrashort bag can be the bag of length less than 64 bytes.
Here need to prove that first thresholding can be to obtain according to technical staff's empirical value or emulation rationally.When the quantity of ultrashort bag during, can think that port communication is normal less than first threshold value.When the quantity of ultrashort bag during greater than first threshold value, illustrate that the port arrangement at two ends may be inconsistent, the port of opposite end may be a semiduplex mode.This is because full duplex has the one-way line of monopolizing, and can send data at any time, and half-duplex port can frequently detect conflict because of circuit is always taken by full-duplex port when data volume increases, influence and the data transmission that may stop up half-duplex port.So, will receive the ultrashort bag of conflict that a lot of half duplex sides are sent at full-duplex port.So when the quantity of ultrashort bag during greater than first thresholding, the port that the opposite end is described probably is a semiduplex mode.In order to make the judgement whether the port duplex pattern of current opposite end is mated more accurate, execution in step 708.
Therefore, this step 707 is optional steps.That is to say, after execution in step 706, can carry out 707, also can skips steps 707 and direct execution in step 708.
708: judge whether the ultrashort bag in the port status information surpasses second threshold value.
If not, execution in step 706;
If, execution in step 709.
The main effect of step 708 is: reaching certain data traffic when above, if dual-mode does not match, an end of full duplex can send data at any time, and conflicts mutually with the data of half-duplex port transmission again and again.And half-duplex port can stop to send data when finding conflict, so can produce a large amount of incomplete packets in the line.But, when if incomplete packet does not reach second thresholding, illustrate that data do not reach certain flow, the erroneous packets that produce in the circuit this moment is not necessarily owing to detecting the ultrashort bag that conflict stops to send, may be that other factors cause in the network, the erroneous packets that when starting, produced of opposite equip. etc. for example.So whether the setting of second thresholding and judgement transmitting-receiving bag quantity can more exactly judge whether the port duplex pattern of opposite end mate greater than this second thresholding.
709: the mode of operation of port is set to half-duplex, finishes.
The link method of the ethernet device port that the embodiment of the invention provides, by using an ethernet device port that is connected control device is being set between physical chip and the isolating transformer, this connection control device can constantly switch annexation between physical chip and isolating transformer receiving terminal and the transmitting terminal according to the index signal of physical chip, so that this ethernet device port is being under the forced working pattern, still can force to intersect and reverse, and the successful link between the realization port.This programme has overcome direct-connected line and cross spider and used the problem that port can't link when wrong, and is simple, convenient, and effective save operation cost.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of program command, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (8)
1. an ethernet device port is characterized in that, comprising: physical chip, isolating transformer and be connected the control device that is connected between described physical chip and the described isolating transformer;
Described connection control device comprises: first group of switch, second group of switch and ON-OFF control circuit;
Described first group of switch is used for the receiving terminal of physical chip is linked to each other with the receiving terminal of isolating transformer, and the transmitting terminal of physical chip is linked to each other with the transmitting terminal of isolating transformer;
Described second group of switch is used for the receiving terminal of physical chip is linked to each other with the transmitting terminal of isolating transformer, and the transmitting terminal of physical chip is linked to each other with the receiving terminal of isolating transformer;
Described ON-OFF control circuit is used for the index signal according to described physical chip, controls the break-make of first group of switch and second group of switch; The status signal that can described index signal link for the described port of indication;
Wherein, described ON-OFF control circuit comprises: receiver module, control module, time delay module and output module;
Described receiver module is used to receive the index signal that described physical chip sends;
Described control module is used for obtaining control signal according to described index signal;
Described time delay module is used for described control signal is delayed time;
Described output module is used for the control signal after the time-delay is exported to first group of switch as first switch controlling signal, and the control signal after the described time-delay is carried out negate export to second group of switch as the second switch control signal.
2. ethernet device port according to claim 1 is characterized in that, described control module comprises: first gating unit and second gating unit;
Described first gating unit is used for gating when described index signal is first value, and control signal keeps initial value constant;
Described second gating unit is used for gating when described index signal is second value, and control signal is the second switch control signal.
3. ethernet device port according to claim 2 is characterized in that, described first value is high level, and described second value is low level; Perhaps, described first value is low level, and described second value is high level.
4. ethernet device port according to claim 1 is characterized in that, described time delay module is the RC resistance-capacitance circuit.
5. the link method of an ethernet device port as claimed in claim 1, Lian Jie ethernet device port is connected with each other by direct-connected line or cross spider each other, it is characterized in that, comprising:
When the link of ethernet device port is unsuccessful, force the intersection counter-rotating by direct-connected line or cross spider that described connection control device will be connected between the ethernet device port, until linking successfully.
6. the link method of ethernet device port according to claim 5 is characterized in that, also comprises after linking successfully: carry out auto-negotiation between described ethernet device port;
If auto-negotiation is unsuccessful, the operating state of described ethernet device port is set to full duplex, and statistics port status information;
When port status information was unusual, the operating state of described ethernet device port was set to half-duplex.
7. the link method of ethernet device port according to claim 6 is characterized in that, described port status information comprises unusually:
If the ultrashort bag of port surpasses second threshold value that sets in advance, then described port status is unusual.
8. the link method of ethernet device port according to claim 7 is characterized in that, the length of the ultrashort bag of described port is less than 64 bytes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010569161 CN102055810B (en) | 2010-11-26 | 2010-11-26 | Ethernet equipment port and link method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010569161 CN102055810B (en) | 2010-11-26 | 2010-11-26 | Ethernet equipment port and link method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN102055810A CN102055810A (en) | 2011-05-11 |
| CN102055810B true CN102055810B (en) | 2013-07-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201010569161 Expired - Fee Related CN102055810B (en) | 2010-11-26 | 2010-11-26 | Ethernet equipment port and link method thereof |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106528476A (en) * | 2016-11-24 | 2017-03-22 | 微鲸科技有限公司 | Circuit capable of automatically realizing cross and direct connection serial port switching |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1264236A (en) * | 1999-02-14 | 2000-08-23 | 友讯科技股份有限公司 | Method and circuit for detecting and switching load signal on twisted wire pairs of network |
| CN201114104Y (en) * | 2006-12-28 | 2008-09-10 | 四川微迪数字技术有限公司 | Network line sequence converter |
| CN101795119A (en) * | 2009-12-22 | 2010-08-04 | 福建星网锐捷网络有限公司 | Common-mode signal suppression circuit and switch |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7843670B2 (en) * | 2006-09-29 | 2010-11-30 | Agere Systems Inc. | Isolated switched maintain power signature (MPS) and fault monitoring for power over Ethernet |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1264236A (en) * | 1999-02-14 | 2000-08-23 | 友讯科技股份有限公司 | Method and circuit for detecting and switching load signal on twisted wire pairs of network |
| CN201114104Y (en) * | 2006-12-28 | 2008-09-10 | 四川微迪数字技术有限公司 | Network line sequence converter |
| CN101795119A (en) * | 2009-12-22 | 2010-08-04 | 福建星网锐捷网络有限公司 | Common-mode signal suppression circuit and switch |
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