CN102054844B - Nonvolatile memory and manufacturing method thereof - Google Patents
Nonvolatile memory and manufacturing method thereof Download PDFInfo
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- CN102054844B CN102054844B CN 200910212129 CN200910212129A CN102054844B CN 102054844 B CN102054844 B CN 102054844B CN 200910212129 CN200910212129 CN 200910212129 CN 200910212129 A CN200910212129 A CN 200910212129A CN 102054844 B CN102054844 B CN 102054844B
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Abstract
The utility mode discloses a nonvolatile memory and a manufacturing method thereof. The nonvolatile memory comprises a substrate, a dielectric layer, a floating grid, a source electrode, a drain electrode region, a channel region and a doped layer. The substrate comprises a first region and a second region; and the substrate of the second region is provided with a concave-convex surface. The dielectric layer is positioned on both the substrate of the first region and the substrate of the second region and covers the concave-convex surface. The floating grid is positioned on the dielectric layer of the first region and continuously extends to the dielectric layer of the second region. The source electrode and the drain electrode region are positioned in the substrate on two sides of the floating grid of the first region. The channel region is positioned in the substrate between the source electrode and the drain electrode region. The doped layer is positioned on the concave-convex surface of the second region or in the substrate of the second region to be taken as a control grid.
Description
Technical field
The present invention relates to a kind of memory and manufacture method thereof, and particularly relate to a kind of nonvolatile memory and manufacture method thereof.
Background technology
Nonvolatile memory can repeatedly carry out the actions such as depositing in, read, erase of data, and the data that deposit in also can not disappear after outage, is widely used on the electronic product.
Typical nonvolatile memory has stack grid structure, and it comprises and is positioned at suprabasil floating grid (Floating Gate) and control gate (Control Gate).Floating grid is in floating state between control gate and substrate, be not connected with any circuit, and the control grid then is positioned at the floating grid top, and (Word Line) joins with the word line.In addition, also comprise respectively dielectric layer (Inter-Gate DielectricLayer) between tunnel oxide (Tunneling Oxide Layer) and grid between substrate and the floating grid and between floating grid and the control gate.
In the nonvolatile memory, the coupling area between floating grid and the control gate is larger, and coupling ratio is higher, and the capacitance that can store is larger.Yet, along with the demand of the continuous miniaturization of element, the size of element is constantly dwindled, and the capacitance that memory can store diminishes relatively, therefore, need badly can provide a kind of can dwindle layout area and can promote the coupling usefulness nonvolatile memory and manufacture method thereof.
Summary of the invention
The invention provides a kind of non-volatile memory device, it can increase the coupling area between floating grid and the control gate, to promote the coupling usefulness of memory element.
The invention provides a kind of non-volatile memory device, it can under identical coupling area, dwindle layout area.
The invention provides a kind of manufacture method of non-volatile memory device, can increase coupling area between floating grid and the control gate with technique simply and cheaply, promote the coupling usefulness of memory element.
The manufacture method that the invention provides a kind of non-volatile memory device can be dwindled layout area and enough coupling areas can be provided.
The present invention proposes a kind of non-volatile memory device, comprises substrate, dielectric layer, floating grid, source electrode and drain region, channel region and doped layer.Substrate is included as the first district and Second Region, and the substrate of Second Region has convex-concave surface.Dielectric layer is positioned in the substrate in the first district, and is positioned in the substrate of Second Region, is covered on the convex-concave surface.Floating grid is positioned on the dielectric layer in the first district and extends to continuously on the dielectric layer of Second Region.Source electrode and drain region are positioned among the substrate of floating grid both sides in the first district.In the substrate of channel region between source electrode and drain region.Doped layer is arranged on the convex-concave surface of Second Region or substrate, as control gate.
In the described non-volatile memory device of the embodiment of the invention, above-mentioned substrate has a plurality of grooves, so that the above-mentioned substrate of above-mentioned Second Region has above-mentioned convex-concave surface.
In the described non-volatile memory device of the embodiment of the invention, above-mentioned doped layer comprises the selective epitaxial layer of doping, is positioned on the above-mentioned convex-concave surface.
In the described non-volatile memory device of the embodiment of the invention, the selective epitaxial layer of above-mentioned doping is the single-crystal Si epitaxial layers of doping or semispherical silicon crystal (Hemispherical SiliconGrains, the HSG) layer of doping.
In the described non-volatile memory device of the embodiment of the invention, above-mentioned doped layer comprises doped region, is arranged in the above-mentioned substrate of above-mentioned Second Region.
Also comprise isolation structure according to the described non-volatile memory device of the embodiment of the invention, in the above-mentioned substrate between above-mentioned the first district and above-mentioned Second Region.
In the described non-volatile memory device of the embodiment of the invention, above-mentioned isolation structure is fleet plough groove isolation structure or field oxide (FOX).
In the described non-volatile memory device of the embodiment of the invention, above-mentioned substrate is block substrate (Bulk Substrate) or silicon-on-insulator substrate (SOI).
In the described non-volatile memory device of the embodiment of the invention, the material of above-mentioned floating grid comprises polysilicon or the multi-crystal silicification metal level (Polycide Layer) of doping.
The present invention proposes again a kind of manufacture method of non-volatile memory device, and comprising provides substrate, and this substrate comprises the first district and Second Region.Then, the substrate at Second Region forms convex-concave surface.Afterwards, form doped layer in the substrate of Second Region, this doped layer is as control gate.Thereafter, in the substrate in the first district and the convex-concave surface of the substrate of Second Region form dielectric layer.Continue it, form floating grid at dielectric layer, floating grid extends to Second Region from the first district.Afterwards, among the substrate of the floating grid both sides in the first district, form two source electrodes and drain region.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the method that forms above-mentioned convex-concave surface is included in and forms a plurality of grooves in the above-mentioned substrate.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the method that forms above-mentioned groove is included in the above-mentioned substrate of above-mentioned the first district and above-mentioned Second Region and forms the first isolation structure, and in the above-mentioned substrate of above-mentioned Second Region, form a plurality of the second isolation structures, afterwards, remove the insulating material in each above-mentioned second isolation structure, to form above-mentioned groove.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the formation method of above-mentioned the first isolation structure and above-mentioned the second isolation structure comprises the shallow trench isolation method.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the formation method of above-mentioned the first isolation structure and above-mentioned the second isolation structure comprises an oxidizing process.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, before the insulating material in removing above-mentioned the second isolation structure, also be included in the above-mentioned substrate and form mask layer, this mask layer has opening, expose substrate and above-mentioned second isolation structure of above-mentioned Second Region, and after the insulating material in removing above-mentioned the second isolation structure, also comprise removing the aforementioned mask layer.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the step that forms above-mentioned doped layer is to carry out after forming the aforementioned mask layer and before removing the aforementioned mask layer.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the method that forms above-mentioned doped layer comprises take above-mentioned mask layer as mask, carry out original position (in-situ) doping and select regional epitaxial growth technique, form the single-crystal Si epitaxial layers of mixing with the substrate in above-mentioned the first district.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the method that forms above-mentioned doped layer comprises take above-mentioned mask layer as mask, carries out in-situ doped selective epitaxial growth technique, forms the semispherical silicon crystal floor that mixes with the substrate in above-mentioned the first district.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the method that forms above-mentioned doped layer comprises carries out ion implantation technology take above-mentioned mask layer as mask, forms doped region in the substrate in above-mentioned the first district.
Described according to the embodiment of the invention, in the manufacture method of above-mentioned non-volatile memory device, the material of above-mentioned floating grid comprises doped polycrystalline silicon or multi-crystal silicification metal level.
The formation that the present invention sees through convex-concave surface increases the coupling area between floating grid and the control gate, therefore, can promote the coupling usefulness of memory element by the method, and can under identical coupling area, dwindle layout area.In addition, because groove can form when making isolation structure simultaneously, and whole technique do not need additionally to increase photomask, and therefore, its technique is simple and cost is low.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate accompanying drawing to be described in detail below.
Description of drawings
Figure 1A to 1E is the generalized section of the manufacture method of a kind of non-volatile memory device of illustrating according to the embodiment of the invention.
Fig. 2 A to 2E is the generalized section of the manufacture method of the another kind of non-volatile memory device that illustrates according to the embodiment of the invention.
Description of reference numerals
10: substrate
12: pad oxide
14: silicon nitride layer
16: mask layer
18,19,20: groove
21: convex-concave surface
22: insulating barrier
24,25,26: isolation structure
28,40: mask layer
30: opening
32: doped layer
34: ion implantation technology
36: dielectric layer
38: conductive layer
39: floating grid
42,44: source electrode and drain region
46: channel region
100,200: the district
θ: angle
Embodiment
Fig. 1 E is the generalized section of a kind of non-volatile memory device of illustrating according to the embodiment of the invention.Fig. 2 E is the generalized section of a kind of non-volatile memory device of illustrating according to another embodiment of the present invention.
Please refer to Fig. 1 E and 2E, the non-volatile memory device of the embodiment of the invention comprises substrate 10, dielectric layer 36, floating grid 39, source electrode and drain region 42 and 44, channel region 46 and doped layer 32.Substrate 10 for example is block substrate such as silicon base, or for example is silicon-on-insulator substrate (SOI).Substrate 10 comprises the first district 100 and Second Region 200.Separate with isolation structure 24 between the first district 100 and the Second Region 200.Isolation structure 24 for example is that shallow trench isolation is from (STI) structure or field oxide (FOX).The first district 100 is for having the substrate 10 of flat surfaces; The substrate 10 of Second Region 200 has a plurality of grooves 19,20, so that the substrate 10 of Second Region 200 has convex-concave surface 21.Substrate 100 tools of Second Region 200 are irregular surperficial 21 in the present invention, can be so that have higher coupling area between the floating grid of memory element and the control gate.Therefore, if can reach can form concavo-convex surface purpose person all can, so groove 19,20 shape are not limited with diagram person, its bottom can be flat, round bottom, wedge angle, polygonal etc., sidewall can be vertical sidewall, inclination angle sidewall, arcuation sidewall etc.Dielectric layer 36 is positioned in the substrate 100 in the first district 100, and is positioned in the substrate 10 of this Second Region 200, is covered on the convex-concave surface 21.The material of dielectric layer 36 for example is silica or silicon oxide/silicon nitride/silicon oxide stack layer.Floating grid 39 is positioned on the dielectric layer 36 in the first district 100 and extends to continuously on the dielectric layer 36 of Second Region 200.That is, be electrically connected at the floating grid 39 in the first district 100 and the floating grid on the Second Region 200 39.The material of floating grid 39 for example is doped polycrystalline silicon or the multi-crystal silicification metal level that is made of doped polycrystalline silicon and metal silicide layer.The material of metal silicide layer for example is the silicide of heating resisting metal, and heating resisting metal for example is one of them of alloy of nickel, cobalt, titanium, copper, molybdenum, tantalum, tungsten, erbium, zirconium, platinum and those metals.Source electrode and drain region 42 and 44, it is positioned among the substrate 10 of floating grid 39 both sides in the first district 100.In an embodiment, substrate 10 is for having silicon base or the silicon-on-insulator substrate of P type dopant; Source electrode and drain region 42 and 44 are the N-type doped region.In another embodiment, substrate 10 is for having silicon base or the silicon-on-insulator substrate of N-type dopant, and source electrode and drain region 42 and 44 are P type doped region.Dopant in the P type doped region for example is boron.Dopant in the N-type doped region for example is phosphorus or arsenic.In the substrate 10 of channel region 46 between source electrode and drain region 42 and 44.Doped layer 32 is arranged on the convex-concave surface 21 of Second Region 200 or substrate 10, as control gate, with floating grid 39 couplings.Dopant in the doped layer 32 can be N-type or P type.The progression of the concentration of dopant of doped layer 32 for example is 10
19To 10
22/ cm
3Doped layer 32 can be doped region or the selective epitaxial layer of doping.Doped region is to be formed among the substrate 10 with convex-concave surface 21 with ion implantation technology, shown in Fig. 1 C.The selective epitaxial layer that mixes can be semispherical silicon crystal (HSG) layer of single-crystal Si epitaxial layers or doping, and it is that mode with epitaxial growth is formed on the substrate 10 with convex-concave surface 21, shown in Fig. 1 C-1.
Figure 1A to 1E is the generalized section of the manufacture method of a kind of non-volatile memory device of illustrating according to the embodiment of the invention.
Please refer to Figure 1A, substrate 10 comprises the first district 100 and Second Region 200.Substrate 10 for example is block substrate such as silicon base, or for example is the silicon-on-insulator substrate.The predetermined isolation structure that forms between the first district 100 and the Second Region 200.Form mask layer 16 in substrate 10.Mask layer 16 is made of pad oxide 12 and silicon nitride layer 14.Then, patterned mask layer 16, and in the substrate 10 of Second Region 200, form groove 18, in the substrate 100 of Second Region 200, form simultaneously groove 19 and 20.In an embodiment, groove 19 and 20 the degree of depth are about the 2500-3000 dust.Afterwards, among groove 18,19 and 20 and mask layer 16 form insulating barriers 22.The material of insulating barrier 22 for example is silica, the method that forms for example is chemical vapour deposition technique, such as modes such as plasma enhanced chemical vapor deposition method (PECVD), aumospheric pressure cvd method (APCVD) or high density plasma CVD techniques (HDPCVD).
Then, please refer to Figure 1B, remove the insulating barrier 22 on the mask layer 16, stay the insulating barrier among the groove 18,19,20, to form fleet plough groove isolation structure 24,25,26.The method that removes for example is chemical mechanical polishing method (CMP) or etch-back method (Etch Back).Afterwards, remove mask layer 16.The method that removes mask layer 16 for example is wet etching or dry etching method.In substrate 10 form another mask layer 28 thereafter.Mask layer 28 for example is the photoresist layer.Mask layer 28 has opening 30, exposes the fleet plough groove isolation structure 25,26 of Second Region.
, please refer to Fig. 1 C and 1C-1, remove fleet plough groove isolation structure 25,26 insulating barrier, expose groove 19,20 thereafter, groove 19,20 and substrate 10 form convex-concave surfaces 21.The method that removes fleet plough groove isolation structure 25,26 insulating barrier can adopt etching method, for example is wet etching or dry etching method.Afterwards, in the substrate 10 of Second Region 200, form doped layer 32, to reduce resistance, as control gate.Doped layer 32 for example is the single-crystal Si epitaxial layers of doped region, doping or the semispherical silicon crystal layer of doping.Dopant in the doped layer 32 can be N-type or P type.The N-type dopant for example is phosphorus or arsenic.P type dopant for example is boron.
In an embodiment, please refer to Fig. 1 C, doped layer 32 is doped region, and its formation method for example is take mask layer 28 as mask, carries out ion implantation technology 34, forms doped region in Second Region 200 has the substrate 10 of convex-concave surface 21.Ion implantation technology 34 can be the tilting ion implantation technology, and the angle theta between the normal of itself and substrate 10 for example is that 15 degree are to 60 degree.
In another embodiment, please refer to Fig. 1 C-1, doped layer 32 is the single-crystal Si epitaxial layers of doping or the semispherical silicon crystal layer of doping, its formation method for example is as mask take mask layer 28, select regional epitaxial growth technique (Selective Area Epitaxy Growth Process), to form the single-crystal Si epitaxial layers of doping or the semispherical silicon crystal layer of doping in the substrate 10 that has convex-concave surface 21 in Second Region 200.Dopant in single-crystal Si epitaxial layers or the semispherical silicon crystal layer can be in-situ doped when selecting regional epitaxial growth technique, or after selecting regional epitaxial growth technique, again via ion implantation technology to form.
Afterwards, please refer to Fig. 1 D, remove mask layer 28.Then, in the substrate 10 in the first district 100 and the convex-concave surface 21 of the substrate 10 of Second Region 200 form dielectric layers 36.The material of dielectric layer 36 for example is silica, and the method for formation for example is thermal oxidation method or chemical vapour deposition technique.The material of dielectric layer 32 also can be the silicon oxide/silicon nitride/silicon oxide stack layer.Then, the dielectric layer 36 formation conductive layers 38 with Second Region 200 in the first district 100.The material of conductive layer 38 for example is the polysilicon that mixes or the multi-crystal silicification metal level that is made of doped polycrystalline silicon and metal silicide layer, and the method for formation for example is chemical vapour deposition technique.Afterwards, form another layer mask layer 40 at conductive layer 38.Mask layer 40 covers the predetermined zone that forms floating grid.The material of mask layer 40 for example is photoresist.
Thereafter, please refer to Fig. 1 E, patterned conductive layer 38 is to form floating grid 39.The method of patterned conductive layer 38 for example is take mask layer 40 as mask, carries out etch process, removes the conductive layer 38 of not masked layer 40 covering and the dielectric layer 36 of below thereof, makes the conductive layer 38 that stays as floating grid 39.Floating grid 39 is positioned on the dielectric layer 36 in the first district 100, and extends to continuously on the dielectric layer 36 of Second Region 200.Afterwards, remove mask layer 40.Then, among the substrate 10 of floating grid 39 both sides in the first district 100, form source electrode and drain region 42 and 44.Between source electrode and drain region 42 and 44, it is channel region 46.Thereafter, form doped region 48 in the substrate 10 of Second Region 200, doped region 48 has identical conductivity type with doped layer 32 and is electrically connected with doped layer 32, as the contact of connective word line.
In above embodiment, the isolation structure 24,25, the 26th of Figure 1B forms with typical shallow trench isolation method, yet the present invention is not as limit, and isolation structure 24,25,26 can also adopt an oxidizing process to form.Be described in detail as follows.
Fig. 2 A to 2E is the generalized section of the manufacture method of a kind of non-volatile memory device of illustrating according to the embodiment of the invention.
Please refer to Fig. 2 A, form mask layer 16 according to said method in substrate 10, and with mask layer 16 patternings.Afterwards, carry out thermal oxidation technology, substrate 10 oxidations that mask layer 16 is exposed form field oxide (insulating barrier), as isolation structure 24,25,26.In an embodiment, the degree of depth of field oxide is about the 4000-5000 dust.
Afterwards, please refer to Fig. 2 B, remove mask layer 16., in substrate 10 form another mask layer 28, remove the field oxide (insulating barrier) in the isolation structure 25,26, form groove (or claiming groove) 19,20 thereafter.Because the isolation structure 24,25, the 26th of present embodiment is formed with the field oxidizing process, therefore, after isolation structure 25,26 field oxide (insulating barrier) remove, formed groove 19,20 roughly has the bottom of arcuation, though from the formed groove 19 of above-described embodiment, 20 slightly different, purpose all is to form convex-concave surface.Step afterwards is all identical with the described person of above embodiment, does not repeat them here.
Increase coupling area between floating grid and the control gate because the present invention sees through the formation of convex-concave surface, therefore, can promote the coupling usefulness of memory element by the method, and can dwindle layout area.In addition, because groove can form when making isolation structure simultaneously, and whole technique do not need additionally to increase photomask, and therefore, its technique is simple and cost is low.
Although the present invention discloses as above with embodiment; so it is not to limit the present invention; any the technical staff in the technical field; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim.
Claims (19)
1. non-volatile memory device comprises:
Substrate, this substrate comprises the first district and Second Region, this substrate of this Second Region has convex-concave surface;
Dielectric layer is positioned in this substrate in this first district, and is positioned in this substrate of this Second Region, is covered on this convex-concave surface;
Floating grid is positioned on this dielectric layer in this first district and extends to continuously on this dielectric layer of this Second Region;
Source area and drain region are positioned among this substrate of these floating grid both sides in this first district;
In channel region this substrate between described source electrode and drain region; And
Doped layer is arranged on this convex-concave surface of this Second Region or this substrate, as control gate.
2. non-volatile memory device as claimed in claim 1, wherein this substrate has a plurality of grooves, so that this substrate of this Second Region has this convex-concave surface.
3. non-volatile memory device as claimed in claim 1, wherein this doped layer comprises the selective epitaxial layer of doping, is positioned on this convex-concave surface.
4. non-volatile memory device as claimed in claim 3 wherein is somebody's turn to do the selective epitaxial layer that mixes and is the single-crystal Si epitaxial layers of doping or the semispherical silicon crystal layer of doping.
5. non-volatile memory device as claimed in claim 1, wherein this doped layer comprises doped region, is arranged in this substrate of this Second Region.
6. non-volatile memory device as claimed in claim 1 also comprises isolation structure, in this substrate between this first district and this Second Region.
7. non-volatile memory device as claimed in claim 1, wherein this isolation structure is fleet plough groove isolation structure or field oxide.
8. non-volatile memory device as claimed in claim 1, wherein this substrate is block substrate or silicon-on-insulator substrate.
9. non-volatile memory device as claimed in claim 1, wherein the material of this floating grid comprises polysilicon or the multi-crystal silicification metal level of doping.
10. the manufacture method of a non-volatile memory device comprises:
Substrate is provided, and this substrate comprises the first district and Second Region;
In this substrate of this Second Region, form convex-concave surface;
Form doped layer in this substrate of this Second Region, this doped layer is as control gate;
In forming dielectric layer in this substrate in this first district and on this convex-concave surface of this substrate of this Second Region;
Form floating grid on this dielectric layer, this floating grid extends to this Second Region from this first district; And
Among this substrate of this floating grid both sides in this first district, form two source electrodes and drain region.
11. the manufacture method of non-volatile memory device as claimed in claim 10, the method that wherein forms this convex-concave surface is included in and forms a plurality of grooves in this substrate.
12. the manufacture method of non-volatile memory device as claimed in claim 11, the method that wherein forms this groove comprises:
In this substrate of this first district and this Second Region, form the first isolation structure, and in this substrate of this Second Region, form a plurality of the second isolation structures; And
Remove the insulating material in this second isolation structure respectively, to form described groove.
13. the manufacture method of non-volatile memory device as claimed in claim 12, wherein the formation method of this first isolation structure and described the second isolation structure comprises the shallow trench isolation method.
14. the manufacture method of non-volatile memory device as claimed in claim 12, wherein the formation method of this first isolation structure and described the second isolation structure comprises an oxidizing process.
15. the manufacture method of non-volatile memory device as claimed in claim 12, wherein:
Before the insulating material in removing described the second isolation structure, also be included in this substrate and form mask layer, this mask layer has opening, exposes this substrate and described second isolation structure of this Second Region; And
After the insulating material in removing described the second isolation structure, also comprise removing this mask layer.
16. the manufacture method of non-volatile memory device as claimed in claim 15, the step that wherein forms this doped layer are to carry out after forming this mask layer and before removing this mask layer.
17. the manufacture method of non-volatile memory device as claimed in claim 16, the method that wherein forms this doped layer comprises take this mask layer as mask, carry out the regional epitaxial growth technique of in-situ doped selection, form the single-crystal Si epitaxial layers of mixing with this substrate in this first district.
18. the manufacture method of non-volatile memory device as claimed in claim 16, the method that wherein forms this doped layer comprises take this mask layer as mask, carry out in-situ doped selective epitaxial growth technique, form the semispherical silicon crystal floor that mixes with this substrate in this first district.
19. the manufacture method of non-volatile memory device as claimed in claim 16, the method that wherein forms this doped layer comprises carries out ion implantation technology take this mask layer as mask, forms doped region in this substrate in this first district.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768161B2 (en) * | 2001-06-01 | 2004-07-27 | Kabushiki Kaisha Toshiba | Semiconductor device having floating gate and method of producing the same |
| CN1542973A (en) * | 2003-04-29 | 2004-11-03 | 力晶半导体股份有限公司 | Separate grid flash memory cell and method for manufacturing the same |
| CN1909211A (en) * | 2005-08-04 | 2007-02-07 | 三星电子株式会社 | Nonvolatile memory devices and methods of fabricating the same |
| CN101515570A (en) * | 2008-02-22 | 2009-08-26 | 旺宏电子股份有限公司 | Inverted t-shaped floating gate memory and method for fabricating the same |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6768161B2 (en) * | 2001-06-01 | 2004-07-27 | Kabushiki Kaisha Toshiba | Semiconductor device having floating gate and method of producing the same |
| CN1542973A (en) * | 2003-04-29 | 2004-11-03 | 力晶半导体股份有限公司 | Separate grid flash memory cell and method for manufacturing the same |
| CN1909211A (en) * | 2005-08-04 | 2007-02-07 | 三星电子株式会社 | Nonvolatile memory devices and methods of fabricating the same |
| CN101515570A (en) * | 2008-02-22 | 2009-08-26 | 旺宏电子股份有限公司 | Inverted t-shaped floating gate memory and method for fabricating the same |
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Address after: Hsinchu Science Park, Taiwan, China Patentee after: Lijing Jicheng Electronic Manufacturing Co., Ltd. Address before: Hsinchu Science Park, Taiwan, China Patentee before: Maxchip Electronics Corp. |
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