CN102054742B - Semiconductor porefilling method for three-step power deposition aluminum - Google Patents
Semiconductor porefilling method for three-step power deposition aluminum Download PDFInfo
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- CN102054742B CN102054742B CN 200910110494 CN200910110494A CN102054742B CN 102054742 B CN102054742 B CN 102054742B CN 200910110494 CN200910110494 CN 200910110494 CN 200910110494 A CN200910110494 A CN 200910110494A CN 102054742 B CN102054742 B CN 102054742B
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Abstract
The invention relates to a method for manufacturing semiconductors, in particular to a semiconductor porefilling method, which comprises the following steps of: depositing a first layer of aluminum by adopting first power; depositing a second layer of aluminum on the first layer of aluminum by adopting second power less than the first power; and depositing a metal connection wire on the second layer of aluminum by adopting third power. Experiments indicate that the second layer of aluminum is deposited on the first layer of aluminum by adopting the second power less than the first power, so the defect of insufficient aluminum porefilling capacity in the conventional process is overcome, the capacity of depositing the aluminum on molding compound layers in the process of manufacturing the semiconductors is improved obviously, and the cost is reduced.
Description
[technical field]
The present invention relates to a kind of semiconductor making method, relate in particular to a kind of semiconductor filling perforation method.
[background technology]
In semiconductor product, mostly adopt tungsten as the material in hole, but in certain specific Product Process, in order to reduce contact hole resistance and to reduce technological process, reduce cost, can use aluminium substitution tungsten.But along with hole depth becomes large, during near 1 micron, utilize general al deposition effect meeting to cause aluminium in advance the opening in hole to be shut, thereby cause the porefilling capability of aluminium to become poorer, even produce cavity blemish (the as shown in Figure 1 black black patch directly over the label 4).
[summary of the invention]
In view of this, be necessary to provide a kind of method that can improve the aluminium porefilling capability.A kind of semiconductor filling perforation method comprises the steps: to adopt the first power deposition ground floor aluminium; Employing is lower than the second power of described the first power at described ground floor aluminium deposition second layer aluminium; Adopt the 3rd power plated metal line on described second layer aluminium; The THICKNESS CONTROL of described second layer aluminium is till filling up to the hole, and the second power of employing is 3kw～6kw, and the first power of employing is 8kw～10kw, and the 3rd power of employing is 10kw～13kw.
Preferably, described the second power is lower than the 3rd power.
Preferably, the THICKNESS CONTROL of described ground floor aluminium is less than 200 nanometers.
Preferably, described metal connecting line material is aluminium.
Preferably, the temperature that deposits described ground floor aluminium is room temperature.
Preferably, the temperature that deposits described second layer aluminium and metal connecting line is controlled at 250 ℃～400 ℃, and the mode of deposition is adopted the physics vapor phase deposition.
Preferably, the mode of deposition adopts sputtering method.
Experiment shows, adopts the second power that is lower than described the first power at described ground floor aluminium deposition second layer aluminium, has overcome aluminium porefilling capability deficiency in traditional technique, has improved significantly in the semiconductor manufacturing, and the ability of molding bed of material deposition of aluminum has reduced cost.
[description of drawings]
Fig. 1 is that aluminium is filled out generation cavity in the process of hole.
Fig. 2 is the design sketch of filling perforation in the embodiment of the invention.
[embodiment]
The method of filling perforation comprised the steps: to adopt the first power deposition ground floor aluminium during a kind of semiconductor was made; Employing is lower than the second power of described the first power at described ground floor aluminium deposition second layer aluminium; Adopt the 3rd power plated metal line on described second layer aluminium.
Utilize traditional al deposition effect deposition ground floor aluminium, the size of the first power of deposition ground floor aluminium is preferably 8kw～10kw.The THICKNESS CONTROL of ground floor aluminium is before having the trend of sealing, less than 200 nanometers.The temperature that deposits described ground floor aluminium is room temperature.
Utilize lower-wattage to deposit ground floor aluminium, the size of the second power of deposition second layer aluminium is preferably 3kw～6kw.With respect to producing the defectives such as mound, whisker and thermal stress be excessive in traditional technique, under this low-power sedimentary condition, deposition rate is very low, and porefilling capability is very strong, has well solved the problem of sealing.Till the thickness of second layer aluminium fills up to the hole.The temperature that deposits described second layer aluminium is controlled at 250 ℃～400 ℃.
The size of the 3rd power of plated metal line is preferably 10kw～13kw.Metal connecting line preferably adopts aluminium or copper, also can be other other metal materials that play electric action.The temperature that deposits described metal connecting line also is controlled at 250 ℃～400 ℃.
The mode of above-mentioned deposition is adopted the physics vapor phase deposition, considers that the sputter chemical composition in the physics vapor phase deposition is controlled easily, and the thin layer of deposit is good in the substrate tack, and present embodiment adopts sputtering method.
Experiment shows, as shown in Figure 2, employing is lower than the second power of described the first power at described ground floor aluminium deposition second layer aluminium, overcome aluminium porefilling capability deficiency in traditional technique, produce the defectives such as cavity, improved significantly in the semiconductor manufacturing, the ability of molding bed of material deposition of aluminum has reduced cost.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (7)
1. a semiconductor filling perforation method is characterized in that: comprise the steps:
Adopt the first power deposition ground floor aluminium;
Employing is lower than the second power of described the first power at described ground floor aluminium deposition second layer aluminium;
Adopt the 3rd power plated metal line on described second layer aluminium;
The THICKNESS CONTROL of described second layer aluminium is till filling up to the hole, and the second power of employing is 3kw～6kw, and the first power of employing is 8kw～10kw, and the 3rd power of employing is 10kw～13kw.
2. semiconductor filling perforation method as claimed in claim 1, it is characterized in that: described the second power is lower than the 3rd power.
3. semiconductor filling perforation method as claimed in claim 1, it is characterized in that: the thickness of described ground floor aluminium is less than 200 nanometers.
4. semiconductor filling perforation method as claimed in claim 1, it is characterized in that: described metal connecting line material is aluminium.
5. semiconductor filling perforation method as claimed in claim 1, it is characterized in that: the temperature that deposits described ground floor aluminium is room temperature.
6. semiconductor filling perforation method as claimed in claim 5, it is characterized in that: the temperature that deposits described second layer aluminium and metal connecting line is controlled at 250 ℃～400 ℃, and the mode of deposition is adopted the physics vapor phase deposition.
7. semiconductor filling perforation method as claimed in claim 6, it is characterized in that: the mode of deposition adopts sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910110494 CN102054742B (en) | 2009-11-05 | 2009-11-05 | Semiconductor porefilling method for three-step power deposition aluminum |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910110494 CN102054742B (en) | 2009-11-05 | 2009-11-05 | Semiconductor porefilling method for three-step power deposition aluminum |
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| CN102054742A CN102054742A (en) | 2011-05-11 |
| CN102054742B true CN102054742B (en) | 2013-01-30 |
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| CN 200910110494 Active CN102054742B (en) | 2009-11-05 | 2009-11-05 | Semiconductor porefilling method for three-step power deposition aluminum |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4994162A (en) * | 1989-09-29 | 1991-02-19 | Materials Research Corporation | Planarization method |
| CN101243202A (en) * | 2005-08-23 | 2008-08-13 | 应用材料股份有限公司 | Aluminum sputtering while biasing wafer |
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2009
- 2009-11-05 CN CN 200910110494 patent/CN102054742B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4994162A (en) * | 1989-09-29 | 1991-02-19 | Materials Research Corporation | Planarization method |
| CN101243202A (en) * | 2005-08-23 | 2008-08-13 | 应用材料股份有限公司 | Aluminum sputtering while biasing wafer |
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| CN102054742A (en) | 2011-05-11 |
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Effective date of registration: 20170930 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214000 No. 5 Hanjiang Road, national hi tech Industrial Development Zone, Wuxi, Jiangsu, China Co-patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |
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