CN102054523A

CN102054523A - Input/output (I/O) unit and integrated circuit chip

Info

Publication number: CN102054523A
Application number: CN2009101984628A
Authority: CN
Inventors: 单毅; 何军
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2009-11-04
Filing date: 2009-11-04
Publication date: 2011-05-11

Abstract

The invention discloses an input/output (I/O) unit and an integrated circuit chip. The I/O unit comprises an N type electrostatic discharge protection circuit, a P type electrostatic discharge protection circuit, a bonding pad and an I/O logic circuit which are distributed transversely, wherein the N type electrostatic discharge protection circuit is isolated from the P type electrostatic discharge protection circuit by the bonding pad; the N type electrostatic discharge protection circuit is connected with a ground wire; and the P type electrostatic discharge protection circuit is connected with a power wire. The area of the I/O unit is small and a larger layout wiring area is correspondingly provided for a core circuit region of the integrated circuit chip, so that the layout wiring difficulty of the core circuit region is lowered. Under the condition of certain core circuit area, the integrated circuit chip which comprises the I/O unit has a smaller area.

Description

I/O unit and integrated circuit (IC) chip

Technical field

The present invention relates to the SIC (semiconductor integrated circuit) design field, particularly I/O unit and integrated circuit (IC) chip.

Background technology

Along with reducing day by day of the increasingly sophisticated and size of semiconductor devices function, the higher limit of its static discharge that can bear (ESD, Electro Static Discharge) voltage also constantly reduces.Thereby, when SIC (semiconductor integrated circuit) designs, often adopt various electrostatic discharge (ESD) protection designs to protect for the semiconductor devices of integrated circuit (IC) chip inside.

At present, a kind of electrostatic discharge (ESD) protection design relatively commonly used is an integrated electrostatic discharge protection circuit in I/O (I/O) unit in integrated circuit (IC) chip, and described ESD protection circuit is linked to each other with respective pad (PAD) in the I/O unit.Fig. 1 is the structural representation of a kind of I/O unit of prior art.With reference to shown in Figure 1, described I/O unit comprises: pad 10, N type ESD protection circuit 20, P type ESD protection circuit 30 and the I/O logical circuit 40 of vertical adjacent distributions.Wherein, the ESD protection circuit that N type ESD protection circuit 20 fingers are made of the NMOS pipe; P type ESD protection circuit 30 refers to the ESD protection circuit that is made of the PMOS pipe, and I/O logical circuit 40 generally includes the interface circuit of some I/O, for example voltage pump etc.Described N type ESD protection circuit 20 place's layouts have ground wire 50, and described P type ESD protection circuit 30 place's layouts have power lead 60.Described N type ESD protection circuit 20 and described P type ESD protection circuit 30 can be selected one according to the electrostatic discharge (ESD) protection demand of reality and link to each other with pad, or link to each other with pad jointly.

Described I/O unit is very suitable for adopting the integrated circuit (IC) chip of this I/O unit to carry out automatic placement and routing owing to its vertical adjacent distributions has layout symmetry preferably.Figure 2 shows that a kind of integrated circuit chip structure synoptic diagram with above-mentioned I/O unit.With reference to shown in Figure 2, by described I/O unit is added in the cell library of automatic placement and routing's software, then but automatic placement and routing's software just can be according to the position and the remaining placement-and-routing area of core circuit in the integrated circuit (IC) chip 1, position to described I/O unit is distributed automatically, and carries out self routing according to design.

Yet; from Fig. 2, also can see; though vertical adjacent distributions structure of described I/O unit has layout symmetry preferably, based on the design rule of avoiding producing latch-up, the very big spacing of essential reservation between P type ESD protection circuit and the N type ESD protection circuit.So, I/O unit area occupied is very big, make integrated circuit (IC) chip 1 core circuit zone (frame of broken lines scope among Fig. 2) but placement-and-routing's area very little, increased placement-and-routing's difficulty in described core circuit zone greatly, therefore when placement-and-routing, can produce a large amount of space wastes.Simultaneously, because the area occupied very big area of integrated circuit (IC) chip 1 corner waste that caused in I/O unit is also very big, therefore the area of whole integrated circuit (IC) chip 1 can increase greatly.

Summary of the invention

The present invention solves prior art, and to comprise the I/O cellar area of ESD protection circuit bigger, but make the problem that placement-and-routing's area is very little and integrated circuit chip area is very big in core circuit zone in the integrated circuit (IC) chip.

For addressing the above problem; the invention provides a kind of I/O unit; comprise: the N type ESD protection circuit of cross direction profiles, P type ESD protection circuit, pad and I/O logical circuit; wherein N type ESD protection circuit and P type ESD protection circuit are isolated by pad; N type ESD protection circuit links to each other with ground wire, and P type ESD protection circuit links to each other with power lead.

Correspondingly, the present invention also provides a kind of integrated circuit (IC) chip that comprises above-mentioned I/O unit, and wherein, adjacent part is a circuit of the same type in each adjacent I/O unit.

Compared with prior art, above-mentioned I/O unit and integrated circuit (IC) chip have the following advantages: the pad of applying in a flexible way has been isolated N type electrostatic discharge circuit and P type electrostatic discharge circuit, satisfied the design rule of avoiding producing latch-up, then the area of I/O unit just can reduce a lot.Correspondingly, but also can provide the bigger placement-and-routing's area in core circuit zone in the integrated circuit (IC) chip, reduce the difficulty of the placement-and-routing in described core circuit zone.

And owing to reducing of I/O cellar area, under the certain situation of core circuit zone area, described integrated circuit (IC) chip has littler area.

Description of drawings

Fig. 1 is the structural representation of a kind of I/O unit of prior art;

Fig. 2 is the structural representation with a kind of integrated circuit (IC) chip of I/O shown in Figure 1 unit;

Fig. 3 is the structural representation of a kind of embodiment of I/O of the present invention unit;

Fig. 4 is a kind of embodiment synoptic diagram of I/O unit application shown in Figure 3 in integrated circuit (IC) chip.

Embodiment

With reference to shown in Figure 3, a kind of embodiment of I/O of the present invention unit comprises: N type ESD protection circuit 200, pad 100, P type ESD protection circuit 300 and the I/O logical circuit 400 of horizontal adjacent distributions.Wherein, the ESD protection circuit that N type ESD protection circuit 200 fingers are made of the NMOS pipe; P type ESD protection circuit 300 refers to the ESD protection circuit that is made of the PMOS pipe, and I/O logical circuit 400 generally includes the interface circuit of some I/O, for example voltage pump etc.Described N type ESD protection circuit 200 is connected with ground wire.Specifically, described ground wire comprises first ground wire 501 and second ground wire 502, and described first ground wire 501 vertically links to each other with second ground wire 502, and described N type ESD protection circuit 200 links to each other with described first ground wire 501.Described P type ESD protection circuit 300 is connected with power lead.Specifically, described power lead comprises first power lead 601 and second source line 602, and described first power lead 601 vertically links to each other with second source line 602, and described P type ESD protection circuit 300 links to each other with described first power lead 601.Described first ground wire 501 and the connected mode of N type ESD protection circuit 200 and the connected mode of first power lead 601 and P type ESD protection circuit 300; can be the mode that first ground wire 501 shown in Figure 3 covers described N type ESD protection circuit 200, the described P type ESD protection circuit 300 of first power lead, 601 coverings, also can be the connected mode (Fig. 3 does not show) by the non-covering of lead connection.In addition, the upper-lower position of second ground wire 502 and second source line 602 can be adjusted according to the actual design demand.

In the foregoing description, N type ESD protection circuit 200 and P type ESD protection circuit 300 are isolated by pad 100, therefore can use pad size and satisfy the design rule of avoiding producing latch-up.Thus, N type ESD protection circuit 200, pad 100, P type ESD protection circuit 300 and the I/O logical circuit 400 in the described I/O unit all can keep less spacing.For example, under the prerequisite that can allow, make each several part all keep technologic minimum spacing in the designing requirement of integrated circuit (IC) chip.Thereby the area of described I/O unit just can reduce largely.

Below further specify in the example of integrated circuit (IC) chip by I/O unit application shown in Figure 3.

With reference to shown in Figure 4, integrated circuit (IC) chip 2 has 6 pins, and described 6 pins are drawn by the pad in 6 I/O unit in the integrated circuit (IC) chip 2 separately.Shown in 6 I/O cell distribution in the periphery of described integrated circuit (IC) chip 2, one of them I/O unit also is distributed in the corner of integrated circuit (IC) chip 2, second ground wire 502 in each I/O unit links to each other separately with second source line 602.And adjacent part is circuit of the same type in the adjacent I/O unit.For example, in two adjacent I/O unit of core circuit zone (frame of broken lines scope) top, adjacent part all is the I/O logical circuit.And in three adjacent I/O unit of below, core circuit zone, two adjacent parts all are I/O logical circuit and N type ESD protection circuit respectively.

Comparison diagram 2 and Fig. 4 can find, for the integrated circuit (IC) chip that is 6 pins equally, the I/O unit of the embodiment of the invention is with respect to the I/O unit of prior art, not only at the periphery of integrated circuit (IC) chip 2, and in the corner of integrated circuit (IC) chip 2, its area has all had bigger reducing.

Specifically, the I/O cellular construction that is different from prior art, the I/O unit of present embodiment can laterally be placed in the integrated circuit (IC) chip 2, reduced the shared area in I/O unit greatly, the feasible zone that can be used for core circuit placement-and-routing that reduces of I/O unit area occupied more is tending towards square, when reducing placement-and-routing's difficulty, can also just reduce the area of core circuit so that the utilization factor in these wiring zones maximizes.Simultaneously I/O unit area occupied reduce make the corner area of using up also than reducing greatly in the past in integrated circuit (IC) chip 2 corners.

And second ground wire 502 and second source line 602 all have separately independently wiring space among Fig. 4, do not comprise any circuit therebetween, correspondingly select more metal level to constitute second ground wire 502 and second source line 602.Thereby, also more favourable for the allotment of interconnection resource.

From another point of view, for same core circuit area, because the area of the I/O unit of the embodiment of the invention much smaller than the area of the I/O unit of prior art, therefore adopts the area of integrated circuit (IC) chip of the I/O unit of the embodiment of the invention also will be much smaller than the area of the integrated circuit (IC) chip of the I/O unit that adopts prior art.

Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.

Claims

1. I/O unit; it is characterized in that; comprise: the N type ESD protection circuit of cross direction profiles, P type ESD protection circuit, pad and I/O logical circuit; wherein N type ESD protection circuit and P type ESD protection circuit are isolated by pad; N type ESD protection circuit links to each other with ground wire, and P type ESD protection circuit links to each other with power lead.

2. I/O as claimed in claim 1 unit is characterized in that, described ground wire comprises first ground wire and second ground wire, and described first ground wire vertically links to each other with second ground wire, and described first ground wire links to each other with N type ESD protection circuit.

3. I/O as claimed in claim 2 unit is characterized in that, described first ground wire covers N type ESD protection circuit.

4. I/O as claimed in claim 2 unit is characterized in that, described power lead comprises first power lead and second source line, and described first power lead vertically links to each other with the second source line, and described first power lead links to each other with P type ESD protection circuit.

5. I/O as claimed in claim 4 unit is characterized in that, described first power lead covers P type ESD protection circuit.

6. integrated circuit (IC) chip that comprises each described I/O unit of claim 1 to 5, wherein, adjacent part is a circuit of the same type in each adjacent I/O unit.

7. integrated circuit (IC) chip that comprises the described I/O of claim 4 unit, wherein, second ground wire in each adjacent I/O unit, second source line link to each other separately.