CN102054444A - Display device and driving method thereof - Google Patents

Display device and driving method thereof Download PDF

Info

Publication number
CN102054444A
CN102054444A CN2009102067575A CN200910206757A CN102054444A CN 102054444 A CN102054444 A CN 102054444A CN 2009102067575 A CN2009102067575 A CN 2009102067575A CN 200910206757 A CN200910206757 A CN 200910206757A CN 102054444 A CN102054444 A CN 102054444A
Authority
CN
China
Prior art keywords
pulse
rising edge
edge
negative edge
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2009102067575A
Other languages
Chinese (zh)
Inventor
陈昱丞
王士豪
王参群
罗婉瑜
陈茂松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AU Optronics Corp
Original Assignee
AU Optronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AU Optronics Corp filed Critical AU Optronics Corp
Priority to CN2009102067575A priority Critical patent/CN102054444A/en
Publication of CN102054444A publication Critical patent/CN102054444A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention provides a display device and a driving method thereof. The display device comprises a first scanning line, a second scanning line, a signal line, a first sub-pixel, a second sub-pixel, a first transistor, a second transistor and a gate driver, wherein a gate of the first transistor is coupled with the second scanning line; one source/drain of the first transistor is coupled with the signal line, and the other source/drain of the first transistor is coupled with the first sub-pixel; a gate of the second transistor is coupled with the first scanning line; one source/drain of the second transistor is coupled with the other source/drain of the first transistor, and the other source/drain of the second transistor is coupled with the second sub-pixel; the gate driver is coupled with the first scanning line and the second scanning line, is used for providing the first pulse, the second pulse and the third pulse to the first scanning line in sequence and is also used for providing the fourth pulse, the fifth pulse and the sixth pulse to the second scanning line in sequence; at least parts of the fifth pulse and third pulse overlap during the enabling period; and at least parts of the fourth pulse and second pulse overlap during the enabling period.

Description

Display device and driving method thereof
Technical field
The present invention relates to a kind of display device, relate in particular to the sufficient relatively display device and the driving method thereof of duration of charging of a sub pixel.
Background technology
Continuous development along with display technique, at present, LCD (Liquid Crystl Display, LCD) because have the little and lightweight advantage of volume, gradually, replace traditional cathode-ray tube (Cathode Ray Tube, CRT), and then used by society at large, be widely used in electronic products such as monitor, notebook computer, digital camera and projector especially.And because electronic product all has towards light, thin, short, little development trend, so industry develops a kind of half data driving (HSD2) technology that is applied to display panels again, further to dwindle the volume of LCD.So-called half data Driving technique is a kind of design that utilizes a signal line video data to be write in regular turn contiguous two sub-pixels (sub-pixel).
Fig. 1 promptly illustrates the sub-pixel that designs according to the half data Driving technique and couples relation.As shown in Figure 1, the grid electric property coupling sweep trace Gb of transistor 12, and a wherein source of transistor 12/drain electrode electric property coupling signal wire S0, and another source/drain electrode electric property coupling sub-pixel 10.The grid of transistor 22 couples sweep trace Ga, and another source/drain electrode of a wherein source/drain electrode electric property coupling transistor 12 of transistor 22, and another source of transistor 22/drain electrode electric property coupling sub-pixel 20.
Fig. 2 illustrates the pulse sequence that designs according to the half data Driving technique in the prior art.In Fig. 2, the signal that provides to sweep trace Ga is provided SGa, and the signal that provides to sweep trace Gb is provided SGb, and P1, P2, P3 and P4 all are expressed as pulse.Please be simultaneously with reference to Fig. 1 and Fig. 2, during the pulse activation of pulse P3, because this section period also belongs to during the pulse activation of pulse P2, therefore transistor 12 and 22 all be unlocked (that is sub-pixel 10 and 20 all is unlocked), so can see through signal wire S0 sub-pixel 10 and 20 is charged, further sub-pixel 20 required video datas are loaded sub-pixel 20.And at the negative edge of pulse P3 during this section of the negative edge of pulse P2 owing to have only transistor 22 to be unlocked, and transistor 12 is for closing (that is sub-pixel 10 is for closing), so can't charge to sub-pixel 10 and 20 through signal wire S0.As for during the pulse activation of pulse P4, owing to have only transistor 12 to be unlocked, and transistor 22 charges to sub-pixel 10 so can see through signal wire S0 for closing, so that sub-pixel 10 required video datas are loaded sub-pixel 10.
By aforesaid operations explanation as can be known, during a frame updating in, sub-pixel 10 can carry out twice charging, and sub-pixel 20 charging set meeting for once.Because the duration of charging of sub-pixel 20 is shorter, therefore the situation of undercharge appears easily.And experiment also proves, operates under high frequency, and the situation of brightness slump of disastrous proportions can appear in sub-pixel 20.Therefore, although adopt the half data Driving technique can reduce half signal wire cabling space of display panels, and improve the aperture opening ratio of display panels, yet display panels has the situation that undercharge can appear in the sub-pixel of half.
Summary of the invention
The objective of the invention is to, a kind of display device is provided, it does not have the problem of sub-pixel undercharge.
In addition, the present invention also provides a kind of driving method of display device, and it can make display device the problem of sub-pixel undercharge can not occur.
The object of the invention to solve the technical problems is to adopt following technical scheme to realize.
The present invention proposes a kind of display device, and it includes display panel and gate drivers.This display panel includes first sweep trace, second sweep trace, signal wire, first sub-pixel, second sub-pixel, the first transistor and transistor seconds.The first transistor has first grid, first source/drain electrode and second source/drain electrode, and first grid electric property coupling second sweep trace, first source/drain electrode electric property coupling signal wire, and second source/drain electrode electric property coupling first sub-pixel.Transistor seconds has second grid, the 3rd source/drain electrode and the 4th source/drain electrode, and second grid electric property coupling first sweep trace, the 3rd source/drain electrode electric property coupling second source/drain electrode, and the 4th source/drain electrode electric property coupling second sub-pixel.As for gate drivers, its electric property coupling first sweep trace and second sweep trace in order to first pulse, second pulse and the 3rd pulse to the first sweep trace to be provided in regular turn, are further opened second sub-pixel so that see through first pulse, second pulse and the 3rd pulse.Gate drivers also in order to the 4th pulse, the 5th pulse and the 6th pulse to the second sweep trace to be provided in regular turn, is further opened first sub-pixel so that see through the 4th pulse, the 5th pulse and the 6th pulse.Wherein, have at least part to overlap during the pulse activation of the 5th pulse and the 3rd pulse, and have at least part to overlap during the pulse activation of the 4th pulse and second pulse.
The present invention also proposes a kind of driving method of display device, described display device includes display panel, and this display panel includes first sweep trace, second sweep trace, signal wire, first sub-pixel, second sub-pixel, the first transistor and transistor seconds.The first transistor has first grid, first source/drain electrode and second source/drain electrode, and first grid electric property coupling second sweep trace, first source/drain electrode electric property coupling signal wire, and second source/drain electrode electric property coupling first sub-pixel.Transistor seconds has second grid, the 3rd source/drain electrode and the 4th source/drain electrode, and second grid electric property coupling first sweep trace, the 3rd source/drain electrode electric property coupling second source/drain electrode, and the 4th source/drain electrode electric property coupling second sub-pixel.Described driving method comprises the steps: to provide in regular turn first pulse, second pulse and the 3rd pulse to the first sweep trace, further opens second sub-pixel so that see through first pulse, second pulse and the 3rd pulse; And provide the 4th pulse, the 5th pulse and the 6th pulse to the second sweep trace in regular turn, further open first sub-pixel so that see through the 4th pulse, the 5th pulse and the 6th pulse, wherein have at least part to overlap during the pulse activation of the 5th pulse and the 3rd pulse, and have at least part to overlap during the pulse activation of the 4th pulse and second pulse.
The present invention mainly is in the prior art the pulse sequence, before original pulse, increase a pulse (for example first pulse and the 4th pulse) again, and make the pulse activation time of the pulse increased overlap with the pulse activation time portion to second pulse of last sweep trace is provided.Thus, just can increase the charging times of second sub-pixel, and then improve the problem of the second sub-pixel undercharge.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above and other objects of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 illustrates the sub-pixel that designs according to the half data Driving technique and couples relation.
Fig. 2 illustrates the known pulse sequence that designs according to the half data Driving technique.
Fig. 3 is the key diagram according to the display device of one embodiment of the invention.
Fig. 4 illustrates the pulse sequence according to one embodiment of the invention.
Fig. 5 is the driving method according to the display device of one embodiment of the invention.
10,20: sub-pixel 12,22: transistor
100: display device 110: time schedule controller
112: source electrode driver 114: gate drivers
116: display panel Ga, Gb: sweep trace
S0: signal wire SGa, SGb: signal
P1~P6: pulse S502, S504: step
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, module backlight that foundation the present invention is proposed and the liquid crystal display systems that uses this module backlight, its embodiment, structure, feature and effect thereof, describe in detail as after.
First embodiment:
See also Fig. 3, it is the key diagram according to the display device of one embodiment of the invention.As shown in the figure, display device 100 of the present invention includes time schedule controller 110, source electrode driver 112, gate drivers 114 and display panel 116.Time schedule controller 110 electric property coupling source electrode drivers 112 and gate drivers 114, and source electrode driver 112 and gate drivers 114 electric property coupling display panel 116 all.Time schedule controller 110 is in order to the operation of Controlling Source driver 112 and gate drivers 114, so that control the required picture of display panel 116 demonstrations through source electrode driver 112 and gate drivers 114.Above-mentioned display panel 116 includes sweep trace Ga, sweep trace Gb, signal wire S0, sub-pixel 10, sub-pixel 20, transistor 12 and transistor 22 again.The grid of transistor 12 sees through sweep trace Gb electric property coupling gate drivers 114, and a wherein source/drain electrode of transistor 12 sees through signal wire S0 electric property coupling source electrode driver 112, and another source of transistor 12/drain electrode electric property coupling sub-pixel 10.The grid of transistor 22 sees through sweep trace Ga electric property coupling gate drivers 114, another source/drain electrode of a wherein source/drain electrode electric property coupling transistor 12 of transistor 22, and another source of transistor 22/drain electrode electric property coupling sub-pixel 20.
Fig. 4 illustrates the pulse sequence according to one embodiment of the invention.In Fig. 4, SGa is expressed as gate drivers 114 and provides to the signal of sweep trace Ga, and SGb is expressed as gate drivers 114 and provides to the signal of sweep trace Gb, and P1, P2, P3, P4, P5 and P6 all are expressed as pulse.Wherein, the rising edge of pulse P4 and negative edge are between the rising edge and negative edge of pulse P2, and the rising edge of the rising edge of pulse P5 and pulse P3 is point at one time, and the negative edge of pulse P5 is between the rising edge and negative edge of pulse P3.As for pulse P6, the negative edge of its rising edge and pulse P3 is point at one time.
Please be simultaneously with reference to Fig. 3 and Fig. 4, during the pulse activation of pulse P4, because this section period also belongs to during the pulse activation of pulse P2, therefore transistor 12 and 22 all be unlocked (that is sub-pixel 10 and 20 all is unlocked), so source electrode driver 112 can see through signal wire S0 sub-pixel 10 and 20 is charged, further sub-pixel 20 required video datas are loaded sub-pixel 20.During this section of the negative edge of pulse P2, owing to have only transistor 22 to be unlocked, and transistor 12 is for closing (that is sub-pixel 10 is for closing), so source electrode driver 112 can't charge to sub-pixel 10 and 20 through signal wire S0 at the negative edge of pulse P4.During this section of the rising edge of pulse P5, transistor 12 and 22 is all closes, so source electrode driver 112 also can't charge to sub-pixel 10 and 20 through signal wire S0 at the negative edge of pulse P2.During the pulse activation of pulse P5, because this section period also belongs to during the pulse activation of pulse P3, therefore transistor 12 and 22 all is unlocked, so source electrode driver 112 can see through signal wire S0 sub-pixel 10 and 20 is charged, again sub-pixel 20 required video datas are loaded sub-pixel 20.And at the negative edge of pulse P5 during this section of the negative edge of pulse P3 owing to have only transistor 22 to be unlocked, and transistor 12 is for closing, so source electrode driver 112 can't charge to sub-pixel 10 and 20 through signal wire S0.As for during the pulse activation of pulse P6, owing to have only transistor 12 to be unlocked, and transistor 22 charges to sub-pixel 10 so can see through signal wire S0 for closing, so that sub-pixel 10 required video datas are loaded sub-pixel 10.
By above-mentioned operation instructions as can be known, during a frame updating in, the charging times of sub-pixel 10 increases to three times by secondary originally, and the charging times of sub-pixel 20 is also by once increasing to twice originally.In other words, as long as in known pulse sequence shown in Figure 2, before original pulse, increase a pulse (for example pulse P1 and the P4 among Fig. 4) again, and make the pulse (for example pulse P4 among Fig. 4) increased the pulse activation time and provide to the pulse activation time portion overlapping of second pulse (for example pulse P2 among Fig. 4) of last sweep trace (for example sweep trace Ga among Fig. 3), just can increase the charging times of sub-pixel 20 thus, solve sub-pixel 20 because of the short undercharge problem that causes of duration of charging.In addition, when adopting this mode of operation also can improve display panel 116 under high frequency, to operate, can make sub-pixel 20 situation of brightness slump of disastrous proportions occur.
Second embodiment:
By Fig. 4 and corresponding the explanation as can be known thereof, as long as have at least part to overlap during the pulse activation of pulse P4 and P2, and have at least part to overlap during the pulse activation of pulse P5 and pulse P3, just can make sub-pixel 20 obtain the recharging chance.Therefore, in this second embodiment, be the rising edge point at one time that makes the rising edge of pulse P4 and pulse P2, and the negative edge of the negative edge of pulse P4 and pulse P2 point at one time.
The 3rd embodiment:
According to the argumentation of second embodiment, in this embodiment, be make Fig. 4 the rising edge of pulse P4 between the rising edge of the negative edge of pulse P1 and pulse P2, and the negative edge of pulse P4 is between the rising edge of the negative edge of pulse P2 and pulse P3.
The 4th embodiment:
According to the argumentation of second embodiment, in this embodiment, be make Fig. 4 the rising edge of pulse P4 between the rising edge of the negative edge of pulse P1 and pulse P2, and the negative edge of the negative edge of pulse P4 and pulse P2 point at one time.
The 5th embodiment:
According to the argumentation of second embodiment, in this embodiment, be make Fig. 4 the rising edge of pulse P4 between the rising edge of the negative edge of pulse P1 and pulse P2, and the negative edge of pulse P4 is between the rising edge and negative edge of pulse P2.
The 6th embodiment:
According to the argumentation of second embodiment, in this embodiment, be the rising edge point at one time that makes the rising edge of pulse P4 of Fig. 4 and pulse P2, and the negative edge of pulse P4 is between the rising edge of the negative edge of pulse P2 and pulse P3.
The 7th embodiment:
According to the argumentation of second embodiment, in this embodiment, be make Fig. 4 the rising edge of pulse P4 between the rising edge and negative edge of pulse P2, and the negative edge of pulse P4 is between the rising edge of the negative edge of pulse P2 and pulse P3.
The 8th embodiment:
According to the argumentation of second embodiment, in this embodiment, be make Fig. 4 the rising edge of pulse P5 between the rising edge of the negative edge of pulse P2 and pulse P3, and the negative edge of pulse P5 is between the rising edge and negative edge of pulse P3.
The 9th embodiment:
According to the argumentation of second embodiment, in this embodiment, be to make the rising edge of pulse P5 of Fig. 4 and negative edge between the rising edge and negative edge of pulse P3.
Although each embodiment in second embodiment to the, nine embodiment, be only to do variation at waveform and the sequential of pulse P4 or pulse P5, yet having, this field knows that usually the knowledgeable should know, the deviser of pulse sequence also can select any two embodiment and arrange in pairs or groups from second embodiment to the, nine embodiment, to derive other embodiment.Certainly, first embodiment to the, nine embodiment only are in order to illustrate, and are not the embodiment in order to restriction the present invention.
What deserves to be mentioned is that display device of the present invention can be applicable to mobile phone, digital camera, personal digital assistant, notebook computer, TV, vehicle-mounted screen and portable media player ... wait in the electronic installation.
According to the teaching of the various embodiments described above, can summarize some basic operation stepss, as shown in Figure 5.Fig. 5 is the driving method according to the display device of one embodiment of the invention.Described display device includes display panel, and this display panel includes first sweep trace, second sweep trace, signal wire, first sub-pixel, second sub-pixel, the first transistor and transistor seconds.The first transistor has first grid, first source/drain electrode and second source/drain electrode, and first grid electric property coupling second sweep trace, first source/drain electrode electric property coupling signal wire, and second source/drain electrode electric property coupling first sub-pixel.Transistor seconds has second grid, the 3rd source/drain electrode and the 4th source/drain electrode, and second grid electric property coupling first sweep trace, the 3rd source/drain electrode electric property coupling second source/drain electrode, and the 4th source/drain electrode electric property coupling second sub-pixel.The implementation step of described driving method includes: first pulse, second pulse and the 3rd pulse to the first sweep trace are provided in regular turn, further open second sub-pixel (shown in step S502) so that see through first pulse, second pulse and the 3rd pulse; And provide the 4th pulse, the 5th pulse and the 6th pulse to the second sweep trace in regular turn, further open first sub-pixel so that see through the 4th pulse, the 5th pulse and the 6th pulse, wherein have at least part to overlap during the pulse activation of the 5th pulse and the 3rd pulse, and have part overlapping (shown in step S504) during the pulse activation of the 4th pulse and second pulse at least.
In sum, the present invention mainly is in known pulse sequence, increases a pulse before original pulse again, and make the pulse that increased the pulse activation time and provide to the pulse activation time portion overlapping of second pulse of last sweep trace.Thus, just can increase the charging times of second sub-pixel, and then improve the problem of the second sub-pixel undercharge.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be not break away from the technical solution of the present invention content, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims (22)

1. display device is characterized in that it comprises:
One display panel comprises:
One first sweep trace;
One second sweep trace;
One signal wire;
One first sub-pixel;
One second sub-pixel;
One the first transistor has a first grid, one first source/drain electrode and one second source/drain electrode, and this second sweep trace of this first grid electric property coupling, this first source/this signal wire of drain electrode electric property coupling, and this this first sub-pixel of second source/drain electrode electric property coupling;
One transistor seconds, have a second grid, one the 3rd source/drain electrode and one the 4th source/drain electrode, and this first sweep trace of this second grid electric property coupling, this second source/drain electrode of the 3rd source/drain electrode electric property coupling, and this second sub-pixel of the 4th source/drain electrode electric property coupling; And
One gate drivers, this first sweep trace of electric property coupling and this second sweep trace, in order to one first pulse to be provided in regular turn, one second pulse and one the 3rd pulse are to this first sweep trace, so that see through this first pulse, this second sub-pixel is further opened in this second pulse and the 3rd pulse, this gate drivers is also in order to provide one the 4th pulse in regular turn, one the 5th pulse and one the 6th pulse are to this second sweep trace, so that see through the 4th pulse, this first sub-pixel is further opened in the 5th pulse and the 6th pulse, wherein have at least part to overlap during the pulse activation of the 5th pulse and the 3rd pulse, and have at least part to overlap during the pulse activation of the 4th pulse and this second pulse.
2. display device according to claim 1 is characterized in that: the rising edge of the 4th pulse and negative edge are between the rising edge and negative edge of this second pulse.
3. display device according to claim 1 is characterized in that: the rising edge of the rising edge of the 4th pulse and this second pulse is point at one time, and the negative edge of the negative edge of the 4th pulse and this second pulse point at one time.
4. display device according to claim 1, it is characterized in that: the rising edge of the 4th pulse is between the rising edge of the negative edge of this first pulse and this second pulse, and the negative edge of the 4th pulse is between the rising edge of the negative edge of this second pulse and the 3rd pulse.
5. display device according to claim 1 is characterized in that: the rising edge of the 4th pulse is between the rising edge of the negative edge of this first pulse and this second pulse, and the negative edge of the negative edge of the 4th pulse and this second pulse point at one time.
6. display device according to claim 1 is characterized in that: the rising edge of the 4th pulse is between the rising edge of the negative edge of this first pulse and this second pulse, and the negative edge of the 4th pulse is between the rising edge and negative edge of this second pulse.
7. display device according to claim 1 is characterized in that: the rising edge of the rising edge of the 4th pulse and this second pulse is point at one time, and the negative edge of the 4th pulse is between the rising edge of the negative edge of this second pulse and the 3rd pulse.
8. display device according to claim 1 is characterized in that: the rising edge of the 4th pulse is between the rising edge and negative edge of this second pulse, and the negative edge of the 4th pulse is between the rising edge of the negative edge of this second pulse and the 3rd pulse.
9. display device according to claim 1 is characterized in that: the rising edge of the rising edge of the 5th pulse and the 3rd pulse is point at one time, and the negative edge of the 5th pulse is between the rising edge and negative edge of the 3rd pulse.
10. display device according to claim 1, it is characterized in that: the rising edge of the 5th pulse is between the rising edge of the negative edge of this second pulse and the 3rd pulse, and the negative edge of the 5th pulse is between the rising edge and negative edge of the 3rd pulse.
11. display device according to claim 1 is characterized in that: the rising edge of the 5th pulse and negative edge are between the rising edge and negative edge of the 3rd pulse.
12. the driving method of a display device, described display device includes a display panel, this display panel includes one first sweep trace again, one second sweep trace, one signal wire, one first sub-pixel, one second sub-pixel, one the first transistor and a transistor seconds, this the first transistor has a first grid, one first source/drain electrode and one second source/drain electrode, and this second sweep trace of this first grid electric property coupling, this first source/this signal wire of drain electrode electric property coupling, this this first sub-pixel of second source/drain electrode electric property coupling, and this transistor seconds has a second grid, one the 3rd source/drain electrode and one the 4th source/drain electrode, and this first sweep trace of this second grid electric property coupling, this the second source/drain electrode of the 3rd source/drain electrode electric property coupling, this second sub-pixel of the 4th source/drain electrode electric property coupling, this driving method is characterised in that implementation step comprises:
Provide one first pulse, one second pulse and one the 3rd pulse to this first sweep trace in regular turn, further open this second sub-pixel so that see through this first pulse, this second pulse and the 3rd pulse; And
Provide one the 4th pulse, one the 5th pulse and one the 6th pulse to this second sweep trace in regular turn, further open this first sub-pixel so that see through the 4th pulse, the 5th pulse and the 6th pulse,
Wherein have at least part to overlap during the pulse activation of the 5th pulse and the 3rd pulse, and have at least part to overlap during the pulse activation of the 4th pulse and this second pulse.
13. driving method according to claim 12 is characterized in that: the rising edge of the 4th pulse and negative edge are between the rising edge and negative edge of this second pulse.
14. driving method according to claim 12 is characterized in that: the rising edge of the rising edge of the 4th pulse and this second pulse is point at one time, and the negative edge of the negative edge of the 4th pulse and this second pulse point at one time.
15. driving method according to claim 12, it is characterized in that: the rising edge of the 4th pulse is between the rising edge of the negative edge of this first pulse and this second pulse, and the negative edge of the 4th pulse is between the rising edge of the negative edge of this second pulse and the 3rd pulse.
16. driving method according to claim 12, it is characterized in that: the rising edge of the 4th pulse is between the rising edge of the negative edge of this first pulse and this second pulse, and the negative edge of the negative edge of the 4th pulse and this second pulse point at one time.
17. driving method according to claim 12, it is characterized in that: the rising edge of the 4th pulse is between the rising edge of the negative edge of this first pulse and this second pulse, and the negative edge of the 4th pulse is between the rising edge and negative edge of this second pulse.
18. driving method according to claim 12, it is characterized in that: the rising edge of the rising edge of the 4th pulse and this second pulse is point at one time, and the negative edge of the 4th pulse is between the rising edge of the negative edge of this second pulse and the 3rd pulse.
19. driving method according to claim 12, it is characterized in that: the rising edge of the 4th pulse is between the rising edge and negative edge of this second pulse, and the negative edge of the 4th pulse is between the rising edge of the negative edge of this second pulse and the 3rd pulse.
20. driving method according to claim 12 is characterized in that: the rising edge of the rising edge of the 5th pulse and the 3rd pulse is point at one time, and the negative edge of the 5th pulse is between the rising edge and negative edge of the 3rd pulse.
21. driving method according to claim 12, it is characterized in that: the rising edge of the 5th pulse is between the rising edge of the negative edge of this second pulse and the 3rd pulse, and the negative edge of the 5th pulse is between the rising edge and negative edge of the 3rd pulse.
22. driving method according to claim 12 is characterized in that: the rising edge of the 5th pulse and negative edge are between the rising edge and negative edge of the 3rd pulse.
CN2009102067575A 2009-11-09 2009-11-09 Display device and driving method thereof Pending CN102054444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009102067575A CN102054444A (en) 2009-11-09 2009-11-09 Display device and driving method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009102067575A CN102054444A (en) 2009-11-09 2009-11-09 Display device and driving method thereof

Publications (1)

Publication Number Publication Date
CN102054444A true CN102054444A (en) 2011-05-11

Family

ID=43958706

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009102067575A Pending CN102054444A (en) 2009-11-09 2009-11-09 Display device and driving method thereof

Country Status (1)

Country Link
CN (1) CN102054444A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102592537A (en) * 2011-12-16 2012-07-18 友达光电股份有限公司 Driving method of pixel circuit
CN102956217A (en) * 2012-11-30 2013-03-06 深圳市华星光电技术有限公司 Driving method and driving circuit of liquid crystal panel and liquid crystal display device
US9111502B2 (en) 2012-11-30 2015-08-18 Shenzhen China Star Optoelectronics Technology Co., Ltd Driving circuit and LCD device having data monitoring module
CN106205476A (en) * 2014-10-23 2016-12-07 三星显示有限公司 Display device and the electronic equipment with display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102592537A (en) * 2011-12-16 2012-07-18 友达光电股份有限公司 Driving method of pixel circuit
CN102956217A (en) * 2012-11-30 2013-03-06 深圳市华星光电技术有限公司 Driving method and driving circuit of liquid crystal panel and liquid crystal display device
CN102956217B (en) * 2012-11-30 2015-04-22 深圳市华星光电技术有限公司 Driving method and driving circuit of liquid crystal panel and liquid crystal display device
US9111502B2 (en) 2012-11-30 2015-08-18 Shenzhen China Star Optoelectronics Technology Co., Ltd Driving circuit and LCD device having data monitoring module
CN106205476A (en) * 2014-10-23 2016-12-07 三星显示有限公司 Display device and the electronic equipment with display device
CN106205476B (en) * 2014-10-23 2019-10-29 三星显示有限公司 Show equipment and the electronic equipment with display equipment

Similar Documents

Publication Publication Date Title
CN100576304C (en) LCD and pulse driving device thereof
US8711132B2 (en) Display panel and gate driving circuit and driving method for gate driving circuit
US8928703B2 (en) Pixel structure
US20160247426A1 (en) Display panel, pixel structure and driving method thereof
CN104167171B (en) A kind of image element circuit and display device
US20220036847A1 (en) Circuit for driving gate, display module, and display device
CN109300445B (en) Array substrate row driving circuit and display device
CN101814273A (en) Liquid crystal display device
US20210012730A1 (en) Driving method and device of display panel, and display apparatus
US20130093734A1 (en) Liquid display device and driving method thereof
US20130127796A1 (en) Array substrate and driving method thereof
US20120229723A1 (en) Substrate for liquid crystal display device, liquid crystal display device, and method for driving liquid crystal display device
US9741313B2 (en) Gate driving circuit with an auxiliary circuit for stabilizing gate signals
US7868866B2 (en) Liquid crystal display having OCB mode dummy liquid crystal cells and driving method thereof
US20110221729A1 (en) Double-gate liquid crystal display device and related driving method
CN102054444A (en) Display device and driving method thereof
CN113393790A (en) Display panel driving method and device and display device
CN104537978A (en) Display panel, drive method of display panel, and display device
US10102820B2 (en) GOA circuit
US9424787B2 (en) Liquid crystal display device and driving method thereof
CN101846859A (en) Liquid crystal display device
US10297216B2 (en) Gate driving circuit and array substrate using the same
US20210027729A1 (en) Driving method and driving device of display panel
CN112992094A (en) GIP circuit driving method and display device
CN112735322A (en) GIP circuit and driving method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20110511