CN102047558A - Method for determining the offset of a periodic signal - Google Patents
Method for determining the offset of a periodic signal Download PDFInfo
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Abstract
Method for determining the offset of a periodic signal, wherein an offset value that is caused by a level change of the signal is suppressed.
Description
Technical field
The present invention relates to a kind of method that is used for the DC component of definite cyclical signal.
Background technology
The DC component of cyclical signal u
(D. C. value) according to following formula as signal u in the scope of period T integration and calculated:
Therefore, when the positive signal-time and area in the cycle duration scope and negative signal time-area were cancelled out each other, signal did not comprise DC component.This is the situation of so-called alternating voltage.
In technology was used, determining of the D. C. value of signal was common task.This task usually is alternative in integration by use and addition is used for the method that D. C. value determines solves.
Therefore, DC component
Determine by following formula:
Wherein the continuous integral of signal u in cycle duration T scope changes signal-incremental time area into
On summation.
The accuracy of determining according to the D. C. value of this method especially with incremental time
Size relevant, wherein seek as far as possible little incremental time
The method that usually is used to determine DC component by means of integrator with the scope integrates (addition) of input signal at duration T complete cycle.The value that duration T is stored in later in the integrator in complete cycle is the DC component in this cycle.Along with the time of following one-period, integrator is reset (value of being stored is eliminated), and measures and restart.Utilize this method, the DC component in each independent cycle is determined.
But the amplitude of determining signal without direct current component if desired changes (rising or reduction) during determining, then this DC component determines that method shows DC component during amplitude changes, because in this case, each follow in time after half-wave all have the amplitude of bigger (or littler) than the half-wave with opposite polarity of front.Each is unequal during amplitude changes for positive half wave and negative half-wave, makes to determine that by this DC component method is according to the rising of level or descend and begin and determine negative DC component and determine positive DC component under the situation that amplitude raises under the situation that amplitude reduces in the moment of which half period (just still negative).This DC component that only occurs during direct current changes may cause adverse effect to the application in certain adjusting, the especially inverter technology.In inverter technology, regulating circuit especially is used to influence the DC component of output signal, wherein the governing speed height of regulating circuit must make the D. C. value that occurs during a few cycle duration (being generally 50Hz or 60Hz line voltage) only just trigger adjustment process, and described adjustment process may cause the fluctuation of not expecting of regulating loop.
Summary of the invention
Therefore, the present invention based on task be, a kind of method that is used for determining the DC component of cyclical signal is described, this method compensation the amplitude of cyclical signal change during the DC component that occurred.
The method of the feature of this task by having claim 1 solves.Favourable expansion scheme is the theme of dependent claims.
According to main thought of the present invention, by the output signal phase Calais of two integrators being determined the DC component of signal, the two all handles described integrator and will determine signal without direct current component, and one of them integrator carries out integration and second integral device respectively carry out integration in by the scope of the complete cycle of offset half period in the scope of complete cycle.
For this reason, determine that signal without direct current component not only is directed into the input of two integrators but also be directed into periodically recognition device.This periodicity recognition device is determined each monocyclic beginning and finish time of signal, and with one of two integrators be controlled to be make this integrator respectively in the scope of the complete cycle of signal (from the finish time in the zero hour to cycle in cycle) signal is carried out integration.Periodically recognition device is controlled to be the second integral device and makes this second integral device be offset half rolling land in the scope of complete cycle but on the time signal is carried out integration.In order to carry out periodicity identification, for example can use so-called zero crossing identification.
The advantage that therefore can realize is, the DC component that is occurred under the situation that signal amplitude changes is compensated, and only has under the situation of constant amplitude and also be determined by the determined signal DC component of integration method.The significant advantage of the inventive method is, no longer impels the manipulated variable of unnecessary and fluctuation that may cause regulating loop to change in the adjusting of carrying out with the DC component value of passing through short-term appearance when amplitude changes that is defined as the basis of DC component (especially in rectifier or inverter applications).
Application advantageous particularly under the situation of the inventive method offset of sinusoidal signal because under the situation of sinusoidal signal, can carry out especially simply to the identification of cycle duration (and the cycle begins and finishes).
The inventive method can be used for cyclical signal arbitrarily, can make equally the periodic identification of signal is coordinated mutually with corresponding signal.
The inventive method is suitable for constructing particularly by means of discrete electronic device the electronic circuit of this method of enforcement on the one hand, also is suitable for the implementation by means of software on the other hand, and wherein continuous integral changes the processing to time-discrete signal value naturally into.By suitably selecting sample frequency, also can realize solution under by means of the implementation of software with discrete execution mode equivalence.Any mixed form of discrete electrons device and software is possible equally.
Except described parts (integrator, periodicity recognition device, summing unit), the concrete structure of implementing the circuit of the inventive method also must comprise following assembly: it makes integrator reset once more later on respectively and (the maintenance ﹠amp of storage in short time at integral process; Sampling) integrator result (generally being expressed as voltage level).
The inventive method produces the output signal of the DC component of expression input signal, does not wherein show because described amplitude changes the DC component that causes under the situation of the rising of input signal or fall.But the inventive method causes when amplitude changes beginning and shows DC component in the time in the half period, because the second integral device is worked in the mode of the half period that staggers in time.
Therefore, another expansion scheme regulation of the present invention: following of situation about changing in the amplitude that identifies is stored in the storage device by the signal without direct current component with the formed expression input signal of output signal addition of two integrators, and continues this signal is used as effective output signal in certain duration.For this reason, the output signal of being stored of two integrators (respectively after a complete cycle) by means of comparison means (comparator) by compared to each other.If it is poor to exist, the amplitude that has then occurred input signal in a last Measuring Time (cycle duration) changes.Under the situation that the amplitude that identifies changes, comparison means control timing element (monostable flipflop).This timing element is controlled to be storage device the value that makes this storage device make to be stored in this storage device (it is the value of the DC component of the input signal determined recently) and keeps constant as output valve in this duration in by the determined duration of this timing element.The advantage that can realize is thus, and the fluctuation that occurs mistakenly of determined DC component is conditioned circuit and stops, and therefore this regulating circuit is not impelled and carry out unnecessary manipulated variable and change.
The known other method (half-wave integration) that has regulation only to use an integrator from prior art, wherein two half-waves (positive half wave and negative half-wave) are by this integrator integration dividually, and first half-wave (for example positive half wave) was stored in storage device (sampling ﹠amp always before the result of second half-wave has been determined and has been stored in equally in another storage device; Keep) in.Then, be stored in two results in the storage device by addition each other, and therefore the DC component in whole cycle is determined.This method Billy determines DC component longways when using the whole cycle being carried out the fast half period of method of integrator of integration.This method demonstrates D. C. value alternately equally during amplitude changes.Another execution mode of the inventive method improves this half-wave integration method, wherein is provided with two additional memory devices (sampling ﹠amp; Keep), described additional memory devices obtains the output signal of half-wave integration method as input signal, and one of described storage device with 0 to cycle duration 1/4th between delay obtain and the storage input signal, another among the described storage device obtains and the storage input signal to the delay between half with 1/4th of cycle duration.The output signal that expression waits to study the DC component of signal is formed by the output signal of two (adding) storage devices is sued for peace.
The advantage that can realize is thus, can use the half-wave integration method of determining DC component more quickly on the one hand, and under the situation that amplitude changes, do not demonstrate DC component alternately, and do not impel unnecessary manipulated variable to change based on the adjusting of this measured value.
But this improved half-wave integration method causes demonstrating DC component in the time in the half period when amplitude changes beginning.Therefore, stipulate in another expansion scheme of the present invention: following of the situation that the amplitude that identifying changes is stored in another storage device by the signal without direct current component with the formed expression input signal of output signal addition of two (adding) storage devices, and continuation is used as effective output signal with this signal in certain duration.For this reason, the output signal of being stored of two storage devices (respectively after a complete cycle) by means of comparison means (comparator) by compared to each other.If it is poor to exist, the amplitude that has then occurred input signal in a last Measuring Time (cycle duration) changes.Under the situation that the amplitude that identifies changes, comparison means control timing element (monostable flipflop).This timing element is controlled to be storage device the value that makes this storage device make to be stored in this storage device (it is the value of the DC component of the input signal determined recently) and keeps constant as output valve in this duration in by the determined duration of this timing element.The advantage that can realize is thus, and the fluctuation that occurs mistakenly of determined DC component is conditioned circuit and stops, and therefore this regulating circuit do not impelled and carry out unnecessary manipulated variable and change, and wherein keeps the advantage of the half-wave integration method of reaction rapidly.
In addition advantageously, by means of computer, especially implement the inventive method by means of so-called microcontroller.The assembly of implementing this method is suitable for implementing by means of microcontroller well, because in this embodiment, and especially employed integrator and storage device (sampling ﹠amp; Keep) do not have otherwise the inevitably tolerance and the loss of signal.
Description of drawings
Fig. 1 exemplarily shows the block diagram of determining circuit according to the DC component of integration method.
Fig. 2 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal that does not have DC component according to the DC component of integration method.
Fig. 3 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with DC component according to the DC component of integration method.
Fig. 4 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with ascensional range according to the DC component of integration method.
Fig. 5 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with fall according to the DC component of integration method.
Fig. 6 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with ascensional range and DC component according to the DC component of integration method.
Fig. 7 exemplarily shows the block diagram that the DC component with integrator of two half period work of staggering separately from each other in time according to the present invention is determined circuit.
Fig. 8 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with ascensional range according to the DC component of method shown in Figure 7.
Fig. 9 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with fall according to the DC component of method shown in Figure 7.
Figure 10 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal of 10% DC component with ascensional range and this amplitude according to the DC component of method shown in Figure 7.
Figure 11 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal of 10% DC component with fall and this amplitude according to the DC component of method shown in Figure 7.
Figure 12 exemplarily shows such block diagram of determining circuit for the DC component of the present invention with the device that is used to suppress ringing pulse (Einschwingimpuls) that is expanded among Fig. 7.
Figure 13 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal of 10% DC component with ascensional range and this amplitude according to the DC component of method shown in Figure 7.
Figure 14 exemplarily shows the block diagram of determining circuit according to the DC component of half-wave integration method.
Figure 15 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal that does not have DC component according to the DC component of half-wave integration method.
Figure 16 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with ascensional range that does not have DC component according to the DC component of half-wave integration method.
Figure 17 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with fall that does not have DC component according to the DC component of half-wave integration method.
Figure 18 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal of 10% DC component with ascensional range and this amplitude according to the DC component of half-wave integration method.
Figure 19 exemplarily shows the block diagram of determining circuit according to the DC component of the present invention with two additional memory devices of half-wave integration method.
Figure 20 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with ascensional range according to the DC component of the present invention with two additional memory devices of half-wave integration method.
Figure 21 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal with fall according to the DC component of the present invention with two additional memory devices of half-wave integration method.
Figure 22 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the input signal of 10% DC component with ascensional range and this amplitude according to the DC component of the present invention with two additional memory devices of half-wave integration method.
Figure 23 exemplarily shows the emulation of determining the signal change curve in the circuit under the situation of the input signal of 10% DC component with fall and this amplitude according to the DC component of the present invention with two additional memory devices of half-wave integration method.
Figure 24 exemplarily illustrates the block diagram of determining circuit for the DC component of the present invention with the device that is used to suppress ringing pulse that is expanded as among Figure 19.
Figure 25 exemplarily shows the emulation that under the situation of the input signal of 10% DC component with ascensional range and this amplitude DC component of the present invention as among Figure 24 is determined the signal change curve in the circuit.
Embodiment
Signal change curve shown in the accompanying drawing exemplarily is used to set forth the inventive method, and particularly illustrated magnitude of voltage only is used to set forth clearlyer in signal curve.In institute's drawings attached of signal change curve was shown, trunnion axis is express time all.The inventive method is applicable to any level and the frequency of input signal.
Fig. 1 is exemplary and schematically show according to determine the block diagram of circuit from the DC component of integration method commonly known in the art.Input signal ES is directed into the input of integrator 100 and periodicity recognition device 200.The periodically beginning in each independent cycle of recognition device 200 identification input signal ES, and the moment that begins in each cycle is by means of impulser 400 control store devices 300,300 storages of described storage device this time be engraved in integrator 100 the output of output place level and this level kept as output signal DC, wherein said level was represented the DC component in cycle in the last past of input signal ES.
Impulser 400 is at each of control lag circuit 500 zero hour complete cycle, and described delay circuit 500 directly makes integrator 100 reset (removing) in time by means of circuits for triggering 600 after the output level of integrator 100 is stored in the storage device 300.Therefore, being used for the pulse of control store device 300 and being used to makes pulse that integrator 100 resets in time directly each other in succession.
Fig. 2 is exemplary and schematically show the emulation of determining the signal change curve in the circuit according to the DC component of Fig. 1.Do not have the sinusoidal signal ES of DC component to form the input signal of integrator 100, and by this integrator 100 respectively in the scope integrates of one-period.The output signal of integrator 100 forms the input signal of storage device 300, described storage device 300 the output signal of the moment storage integrator of determining by the signal sampling pulse 100 and from one side as output signal DC(sampling ﹠amp; Maintenance) provides this output signal.In addition, figure 2 illustrates the signal (sampling pulse) that is used for control store device 300 and be used to signal (RESET pulse) that integrator 100 is resetted.In an example shown, the output signal DC(of the DC component of the expression input signal of storage device sampling ﹠amp; Keep) all be present worth 0 constantly at each.
Fig. 3 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the sinusoidal input signal ES with positive direct-current component according to the DC component of Fig. 1.In an example shown, in the moment of each end cycle of input signal, the output of integrator 100 exist on the occasion of, described on the occasion of being stored device 300 storages.
Fig. 4 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the sinusoidal input signal ES with ascensional range that does not have DC component according to the DC component of Fig. 1.Show sinusoidal input signal ES, this sinusoidal input signal E is from having the level that rises with constant speed sometime.Thus from this constantly, each half period all has the absolute value of the amplitude bigger than the half period of front.Therefore, signal with absolute value littler than second half period with opposite polarity carries out integration integrator 100 pairs first half periods.Thus in concrete example, at the output of integrator 100 negative value appears from moment of the electrical level rising of input signal.For simplicity, be used for the signal of control store device 300 and the signal that is used to integrator 100 is resetted no longer is illustrated.
Fig. 5 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the sinusoidal input signal ES with fall that does not have DC component according to the DC component of Fig. 1.Thus in this case, from moment that the level of input signal ES descends the output of integrator 100 and thus as D. C. value DC occur on the occasion of.
Fig. 6 is exemplary and schematically show and have DC component and having the emulation of determining the signal change curve in the circuit under the situation of sinusoidal input signal ES of ascensional range according to the DC component of Fig. 1.Show input signal ES, this input signal ES has 10% DC component of amplitude, and from having the level that rises with constant speed sometime.Utilize this input signal ES, determine that according to the DC component of Fig. 1 circuit produces output signal DC, described output signal DC till the moment of electrical level rising corresponding to the DC component of input signal ES.In an example shown, in the zero hour of electrical level rising, output signal DC drops to negative value and rises after each complete cycle after this.
Fig. 7 DC component exemplary and that schematically show the integrator with two half period work of staggering is separately from each other in time determined the block diagram of circuit.
The input signal ES that should be determined DC component will be directed into the input and the periodicity recognition device 200 of two integrators 101,102.This is the zero hour and the finish time in each independent cycle of recognition device 200 definite input signal ES periodically, and by means of two impulsers 401,402 with two integrators 101,102 and two storage devices 301,302 are controlled to be and make these integrators 101, one of 102 respectively in the scope of the complete cycle of input signal ES (from the finish time in the zero hour to this cycle in this cycle) to input signal ES integration, and described two integrators 101, among 102 another is equally in the scope of the complete cycle of this signal, but the half period that staggers in time ground is to input signal ES integration.
Two level that storage device 301,302 is exported in the output place that is assigned to the integrator 101,102 of described storage device by the moment storage given in advance complete cycles 401,402 of corresponding impulser.Described two level that are stored in the storage device 301,302 are added by means of summing circuit S and are somebody's turn to do and level is the DC component DC of input signal ES.
Reset (removing) of two integrators 301,302 carried out in circuit as shown in FIG. 1 like that.
Fig. 8 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the sinusoidal input signal ES with ascensional range that does not have DC component according to the DC component of Fig. 7.
The output signal of two integrators 301,302 demonstrates identical signal change curve, but offset half period and being reversed each other.Two Xin Haocaiyang ﹠amp; Maintenance 1 and sampling ﹠amp; Keep 2 to be added and to form output signal DC in summing circuit S, described output signal DC also no longer has DC component after transition time (Einschwingszeit) under the situation of the input signal ES with ascensional range.
Fig. 9 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the sinusoidal input signal ES with fall that does not have DC component according to the DC component of Fig. 7.
In this case, the same output signal DC that does not have DC component that after transition time, produces.
Determine the emulation of the signal change curve in the circuit under the situation of the exemplary and input signal ES that schematically shows in 10% DC component of Figure 10 according to the DC component of Fig. 7 with ascensional range and this amplitude.Show following input signal ES: it has 10% DC component of amplitude, and from having the level that rises with constant speed sometime.Determine that according to the DC component of Fig. 7 circuit is as output signal DC(memory circuitry 301, the 302(﹠amp that samples; Maintenance 1 and sampling ﹠amp; Keep 2) in the level stored and) and provide following signal: this signal till the moment of the electrical level rising of input signal ES corresponding to the DC component of input signal ES, and from moment of the electrical level rising of input signal ES after transition time equally corresponding to the DC component DC of input signal ES.In Figure 10, the change curve of the DC component (amplitude 10%) of input signal has been shown in the diagram of this output signal.Except the time interval of transient process, the output signal of circuit of the present invention is all corresponding to this DC component.
Determine the emulation of the signal change curve in the circuit under the situation of the exemplary and input signal ES that schematically shows in 10% DC component of Figure 11 according to the DC component of Fig. 7 with fall and this amplitude.Show following input signal: it has 10% DC component of amplitude and from having the level that descends with constant speed sometime.In this case, demonstrate the suitable characteristic of the situation with shown in Figure 10 of output signal.
Figure 12 is exemplary and schematically show the integrator with two half period work of staggering separately from each other in time and have the block diagram of the DC component of the inhibition of transient phase being determined circuit.
Circuit shown in Figure 12 is corresponding to the circuit shown in Fig. 7, and is expanded the device that is used to suppress transient phase (ringing pulse) for having.For this reason, under the situation that the amplitude that identifies changes, be stored in another storage device 303(sampling ﹠amp by signal without direct current component with the formed expression input signal of output signal addition of two integrators 301,302; Keep 3) in, and in the time interval of transient process, continue to be output as the output signal DC of the DC component of representing input signal.Comparison means 700 with the output level of two storage devices 301,302 compared to each other and under the situation that has difference control timing element 800(monostable flipflop (Mono Flip Flop)), described monostable flipflop 800 impels the 3rd storage device 303 to continue output in these timing element 800 determined durations to be stored in value in the 3rd storage device 303 as output signal DC.
Determine the emulation of the signal change curve in the circuit under the situation of the exemplary and input signal ES that schematically shows in 10% DC component of Figure 13 according to the DC component of Figure 12 with ascensional range and this amplitude.Show following input signal ES: it has 10% DC component of amplitude and from having the level that rises with constant speed sometime.Timing element 800(monostable flipflop) output signal shows value all constant when the beginning of the electrical level rising of input signal, and the electrical level rising of input signal ES the time be engraved in by this timing element 800 determined durations in the value of getting back to 0.Thus in by timing element 800 determined these durations, the employing and the storage of 300 pairs of new incoming levels of the 3rd storage device get clogged, and the output signal DC of the DC component of the expression input signal ES that is output constantly up to the electrical level rising of input signal ES is continued output in by timing element 800 determined these durations.
Figure 14 is exemplary and schematically show the block diagram of determining circuit according to the DC component of half-wave integration method.
Input signal ES is directed into the input of integrator 103 and periodicity recognition device 200.Integrator 103 carries out integration to input signal ES respectively in the half period of input signal ES, and directly be reset after each half period finishes (removing).The output signal of integrator 103 is directed into two storage devices 301,302, and by these storage device 301,302 storages, wherein storage device 302 is in storage integrator 103 the output signal zero hour of each complete cycle, and second storage device 301 in each of input signal ES by storage integrator 103 the output signal zero hour of the complete cycle of offset half period.The level that is stored in two storage devices 301,302 is added in summing circuit S, should represent the DC component of input signal ES with signal DC.Control to storage device 301,302 is carried out by means of two impulsers 401,402, wherein impulser 401 when begin each complete cycle of input signal ES at every turn, control storage device 302, the second impulsers 402 that are assigned to it each in time when beginning the complete cycle of its offset half period control be assigned to its storage device 301.Impulser 403 directly makes integrator 103 reset (removing is stored in the level in the integrator 103) by means of delay circuit 500 and reset pulse transmitter 600 after each half period finishes.
Figure 15 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the input signal ES that does not have DC component according to the DC component according to the half-wave integration method of Figure 14.
The output signal of integrator 103 is integrations of input signal ES, and wherein integrator 103 was reset after each half period.The accordingly result of the integral process of two 301,302 two half periods of storage of storage device.Under the concrete condition of the sinusoidal input signal ES that does not have DC component, but two integral results of two half periods have identical absolute value opposite polarity.Thus, the expression DC component with signal DC(sampling ﹠amp; Keep 1+ sampling ﹠amp; Keep 2) have value 0, wherein occur because the minimal ripple of this signal that the storage moment of integrator 103 and the inevitable time delay between the removing constantly cause.
Figure 16 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the input signal ES that does not have DC component with ascensional range according to the DC component according to the half-wave integration method of Figure 14.
Show from having the input signal ES of the level that rises with constant speed sometime.
In this case, the DC component of expression input signal with signal DC(sampling ﹠amp; Keep 1+ sampling ﹠amp; Keep 2) have the rectangle change curve from zero hour of the electrical level rising of input signal ES, this rectangle change curve has the frequency of input signal ES.
Figure 17 is exemplary and schematically show the emulation of determining the signal change curve in the circuit under the situation of the input signal ES that does not have DC component with fall according to the DC component according to the half-wave integration method of Figure 14.
Show from having the input signal ES of the level that descends with constant speed sometime.
In this case, the DC component of expression input signal with signal DC(sampling ﹠amp; Keep 1+ sampling ﹠amp; Keep 2) have the rectangle change curve from zero hour of the electrical level rising of input signal ES, this rectangle change curve has the frequency of input signal ES.The phase place of this rectangular signal is compared with the signal change curve shown in Figure 16 by the half period duration of skew input signal ES.
Determine the emulation of the signal change curve in the circuit under the situation of the exemplary and input signal ES that schematically shows in 10% DC component of Figure 18 according to the DC component of Figure 14 according to the half-wave integration method with ascensional range and this amplitude.
Show following input signal ES: it has 10% DC component of amplitude and from having the level that rises with constant speed sometime.
In this case, the DC component of expression input signal with signal DC(sampling ﹠amp; Keep 1+ sampling ﹠amp; Keep 2) demonstrate the rectangle change curve, this rectangle change curve has been offset the analog value of the DC component of input signal ES aspect level.
Figure 19 is exemplary and schematically show the block diagram of determining circuit according to the DC component of the present invention with two additional memory devices of half-wave integration method.
In Figure 19, the circuit according to the half-wave integration method shown in Figure 14 is expanded to having 303,304, two delay circuits 501,502 of two other storage devices and summing circuit S2.The output signal DC of the DC component of expression input signal ES by means of described other summing circuit S2 from described other storage device 303, the 304(﹠amp that samples; Keep 3+ sampling ﹠amp; Maintenance 4) is formed in the output signal.Described two other storage devices 303, the 304(﹠amp that samples; Keep 3+ sampling ﹠amp; Maintenance 4) input signal forms by ﹠amp that two storage devices 301,302(are sampled; Keep 1+ sampling ﹠amp; Keep 2) the output signal formed signal of suing for peace.Determine in each cycle of input signal ES of circuit in DC component, the any time Be Controlled of one of described other storage device 304 in DC component is determined first half period of input signal ES of circuit, and store the input signal that is assigned to this storage device constantly at this.Another 303 moment (in second half period) Be Controlled of half period of determining the input signal ES of circuit in time with its offset straight flow component among described two other storage devices, and store the input signal that is assigned to this storage device constantly at this.To described other storage device 303, the 304(﹠amp that samples; Keep 3+ sampling ﹠amp; Maintenance 4) control is undertaken by two delay circuits 501,502, and wherein said delay circuit 501,502 is controlled by one of impulser 401,402 respectively.
Figure 20 is exemplary and schematically show under the situation of the input signal ES with ascensional range and to determine the emulation of the signal change curve in the circuit according to Figure 19 according to the DC component of the present invention with two additional memory devices of half-wave integration method.
Show from having the periodicity sinusoidal input signal ES of the level that rises with constant rate of speed sometime.
As about according in the signal change curve shown in the circuit of Figure 14 like that, by ﹠amp that two storage devices 301,302(are sampled; Keep 1+ sampling ﹠amp; Keep 2) the output signal formed signal of suing for peace demonstrate the rectangle change curve.The output signal DC that determines circuit according to the DC component with two additional memory devices of half-wave integration method value of demonstrating 0 all except short transient phase, wherein this output signal DC passes through the ﹠amp that samples to described two other storage devices 303,304(; Keep 3+ sampling ﹠amp; Keep 4) summation and being formed.
Figure 21 is exemplary and schematically show under the situation of the input signal ES with fall and to determine the emulation of the signal change curve in the circuit according to Figure 19 according to the DC component of the present invention with two additional memory devices of half-wave integration method.Show from having the periodicity sinusoidal input signal ES of the level that descends with constant rate of speed sometime.In this case, the output signal DC that determines circuit according to the DC component with two additional memory devices of half-wave integration method value of demonstrating 0 all except short transient phase, wherein this output signal DC passes through the ﹠amp that samples to described two other storage devices 303,304(; Keep 3+ sampling ﹠amp; Keep 4) summation and being formed.
Determine the emulation of the signal change curve in the circuit according to Figure 19 under the situation of the exemplary and input signal ES that schematically shows in 10% DC component of Figure 22 according to the DC component of the present invention with two additional memory devices of half-wave integration method with ascensional range and this amplitude.
By ﹠amp that described two other storage devices 303,304(are sampled; Keep 3+ sampling ﹠amp; Maintenance 4) the formed output signal DC of summation follows the value of the DC component of input signal ES except short transient phase.
Determine the emulation of the signal change curve in the circuit according to Figure 19 under the situation of the exemplary and input signal ES that schematically shows in 10% DC component of Figure 23 according to the DC component of the present invention with two additional memory devices of half-wave integration method with fall and this amplitude.
By ﹠amp that described two other storage devices 303,304(are sampled; Keep 3+ sampling ﹠amp; Maintenance 4) the formed output signal DC of summation follows the value of the DC component of input signal ES except short transient phase.
Figure 24 is exemplary and schematically illustratedly determine the block diagram of circuit according to the DC component of the present invention with two additional memory devices of half-wave integration method as among Figure 19, and wherein this DC component determines that circuit is expanded the device that is used to suppress ringing pulse for having.
Determine the emulation of the signal change curve of circuit according to Figure 19 under the situation of the exemplary and input signal ES that schematically shows in 10% DC component of Figure 25 according to the DC component of the present invention that has two additional memory devices and be used for suppressing the device of ringing pulse of half-wave integration method with ascensional range and this amplitude.
Reference numerals list
The ES input signal
The DC D. C. value
The S summing unit
S1 first summing unit
S2 second summing unit
100 integrator complete cycles
200 periodicity recognition devices
300 storage devices
400 impulser complete cycles
500 delay circuit resets integrators
501 delay circuit storage devices 1
502 delay circuit storage devices 2
600 reset pulse transmitters
101 integrator complete cycles 1
102 integrator complete cycles 2
103 integrator half periods
301 storage devices 1
302 storage devices 2
303 storage devices 3
304 storage devices 4
305 storage devices 5
401 impulser complete cycles 1
402 impulser complete cycles 2
403 impulser half periods
700 comparison circuits (comparator)
800 timing elements (monostable flipflop)
Claims (4)
1. method that is used for determining the DC component of cyclical signal (ES), it is characterized in that, described cyclical signal is fed to two integrators (101,102) recognition device (200) and periodically, first integrator (101) is carried out integration respectively in the scope of complete cycle, and second integral device (102) carries out integration in the scope of the complete cycle of the half period that staggers, and controlled by periodicity recognition device (200) zero hour of integration, and two integrators (101,102) output signal is stored in the storage device (301 that is assigned with respectively later at the one-period duration respectively, 302) in, and described value of storing is summed in summing unit (S), and DC component described and signal (DC) indication cycle's property signal (ES).
2. the method that is used for the DC component of definite cyclical signal (ES) according to claim 1, this method has the inhibition to transient phase, it is characterized in that, two are assigned to integrator (101 respectively, 102) one of storage device (301,302) output signal is fed to comparison circuit (700), and storage device (301,302) being stored in another storage device (303) and as output signal (DC) with signal of output signal is held, comparison circuit (700) impels storage device (303) to continue the value that output is stored in the output signal (DC) in the described storage device (303) in certain duration by means of timing element (800) under the situation of the different absolute value of the output signal appearance of two storage devices (301,302).
3. half-wave method that is used for determining the DC component of periodic input signal (ES), wherein periodic input signal (ES) is fed to integrator (103) and periodicity recognition device (200), integrator (103) carries out integration to periodic input signal (ES) respectively in the scope of half period, this method has the following step:
-when begin each complete cycle of cyclical signal (ES), the output signal of integrator (103) is flowed to sampling ﹠amp; Keep storage device (302) and described signal value is stored in the described storage device (302);
-when begin the complete cycle of each offset half period duration of cyclical signal (ES), the output signal of integrator (103) is flowed to sampling ﹠amp; Keep storage device (301) and described signal value is stored in the described storage device (301);
-in first summing unit (S1), the signal value that is obtained in aforementioned two method steps is sued for peace;
-when begin each complete cycle by the time interval of skew between 0 to the half period duration of cyclical signal (ES), will described first and signal value flow to the ﹠amp that samples; Keep storage device (304) and with described first and signal value be stored in the described storage device (304);
-when begin each complete cycle of being grown to the time interval between duration complete cycle by skew during the half period of cyclical signal (ES), with described first and signal value flow to sampling; Keep storage device (303) and with described first and signal value store in the described storage device (303);
-in second summing unit (S2) in aforementioned two method steps, obtained with signal value summation, and will be described and signal value export as the D. C. value of periodic input signal (ES).
4. half-wave method that is used for determining the DC component of periodic input signal (ES), this method has the inhibition to transient phase, wherein periodic input signal (ES) is fed to integrator (103) and periodicity recognition device (200), integrator (103) carries out integration to periodic input signal (ES) respectively in the scope of half period, this method has the following step:
-when begin each complete cycle of cyclical signal (ES), the output signal of integrator (103) is flowed to sampling ﹠amp; Keep storage device (302) and described signal value is stored in the described storage device (302);
-when begin the complete cycle of each offset half period duration of cyclical signal (ES), the output signal of integrator (103) is flowed to sampling ﹠amp; Keep storage device (301) and described signal value is stored in the described storage device (301);
-in first summing unit (S1), the signal value of being stored in aforementioned two method steps is sued for peace;
-when begin each complete cycle by the time interval of skew between 0 to the half period duration of cyclical signal (ES), will described first and signal value flow to the ﹠amp that samples; Keep storage device (304) and will describedly be stored in the described storage device (304) with signal value;
-when begin each complete cycle of being grown to the time interval between duration complete cycle by skew during the half period of cyclical signal (ES), with described first and signal value flow to sampling; Keep storage device (303) and will describedly be stored in the described storage device (303) with signal value;
-in second summing unit (S2) to the summation of the signal value in aforementioned two method steps, stored, and will described second and signal value flow to another ﹠amp that samples; Keep storage device (305) and described signal value is stored in described sampling ﹠amp; Keep in the storage device (305);
The signal value of-storage in storage device (303,304) is under the situation of varying level, and the signal value that will be stored in the storage device (303,304) flows to comparison circuit (700), and triggers timing element (800) by comparison circuit (700);
-D. C. value (DC) as periodic input signal (ES) in storage device (305) is exported, wherein in that the storage in storage device (305) suppresses to new signal value during the running time of timing element (800), and the nearest signal value of storing continues in the running time at described timing element to be output as the D. C. value (DC) of periodic input signal (ES) before beginning the running time of timing element (800).
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AT0087808A AT506857B1 (en) | 2008-05-30 | 2008-05-30 | METHOD FOR DETERMINING THE EQUALITY OF A PERIODIC SIGNAL |
| ATA878/2008 | 2008-05-30 | ||
| PCT/EP2009/055636 WO2009144129A2 (en) | 2008-05-30 | 2009-05-11 | Method for determining the offset of a periodic signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102047558A true CN102047558A (en) | 2011-05-04 |
| CN102047558B CN102047558B (en) | 2013-11-06 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200980119723.0A Expired - Fee Related CN102047558B (en) | 2008-05-30 | 2009-05-11 | Method for determining the offset of a periodic signal |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8587289B2 (en) |
| EP (1) | EP2286512B1 (en) |
| CN (1) | CN102047558B (en) |
| AT (2) | AT506857B1 (en) |
| WO (1) | WO2009144129A2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101087890B1 (en) * | 2010-01-27 | 2011-11-30 | 엘에스산전 주식회사 | Device and method for processing input data of protective relay |
| TWI449338B (en) * | 2012-04-18 | 2014-08-11 | Univ Nat Sun Yat Sen | Peak detector with digital calibration |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4109308A (en) * | 1976-06-16 | 1978-08-22 | Bodenseewerk Perkin-Elmer & Co., Gmbh | Circuit for converting a.c. voltage into a d.c. voltage |
| JPS5748826A (en) * | 1980-09-08 | 1982-03-20 | Japan Electronic Control Syst Co Ltd | Circuit for converting input pulse duty ratio into analog voltage |
| DE3900796A1 (en) * | 1989-01-12 | 1990-07-19 | Asea Brown Boveri | Arrangement for avoiding transformer saturation when operating a voltage converter |
| US5452198A (en) * | 1994-02-09 | 1995-09-19 | Sundstrand Corporation | Apparatus and method for A/C voltage sensing |
| CN1625833A (en) * | 2002-02-01 | 2005-06-08 | 皇家飞利浦电子股份有限公司 | Additive DC component detection included in an input burst signal |
| US20050271163A1 (en) * | 2004-06-04 | 2005-12-08 | Infineon Technologies Ag | Analog DC compensation |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2454601C3 (en) * | 1974-11-18 | 1979-02-08 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Device for determining the mean value of an electrical variable |
| CA1175919A (en) * | 1980-02-20 | 1984-10-09 | Toshitaka Tsuda | Device for discriminating between two values of a signal with dc offset compensation |
| FR2609552B1 (en) * | 1987-01-09 | 1990-11-30 | Merlin Gerin | CIRCUIT FOR MEASURING THE CONTINUOUS COMPONENT OF THE CURRENT THROUGH THE PRIMARY WINDING OF THE OUTPUT TRANSFORMER OF AN INVERTER |
| US6282228B1 (en) * | 1997-03-20 | 2001-08-28 | Xircom, Inc. | Spread spectrum codes for use in communication |
| AT408393B (en) | 1998-10-14 | 2001-11-26 | Johann W Dipl Ing Kolar | Method and apparatuses for detecting and regulating a DC component of the magnetization current of high-frequency power transformers in converter circuits |
| CN1853336A (en) | 2003-09-19 | 2006-10-25 | 株式会社荏原电产 | Circuit and system for detecting DC component in inverter device for grid-connection |
-
2008
- 2008-05-30 AT AT0087808A patent/AT506857B1/en not_active IP Right Cessation
-
2009
- 2009-05-11 EP EP09753784A patent/EP2286512B1/en not_active Not-in-force
- 2009-05-11 AT AT09753784T patent/ATE552653T1/en active
- 2009-05-11 CN CN200980119723.0A patent/CN102047558B/en not_active Expired - Fee Related
- 2009-05-11 US US12/993,286 patent/US8587289B2/en not_active Expired - Fee Related
- 2009-05-11 WO PCT/EP2009/055636 patent/WO2009144129A2/en active Application Filing
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4109308A (en) * | 1976-06-16 | 1978-08-22 | Bodenseewerk Perkin-Elmer & Co., Gmbh | Circuit for converting a.c. voltage into a d.c. voltage |
| JPS5748826A (en) * | 1980-09-08 | 1982-03-20 | Japan Electronic Control Syst Co Ltd | Circuit for converting input pulse duty ratio into analog voltage |
| DE3900796A1 (en) * | 1989-01-12 | 1990-07-19 | Asea Brown Boveri | Arrangement for avoiding transformer saturation when operating a voltage converter |
| US5452198A (en) * | 1994-02-09 | 1995-09-19 | Sundstrand Corporation | Apparatus and method for A/C voltage sensing |
| CN1625833A (en) * | 2002-02-01 | 2005-06-08 | 皇家飞利浦电子股份有限公司 | Additive DC component detection included in an input burst signal |
| US20050271163A1 (en) * | 2004-06-04 | 2005-12-08 | Infineon Technologies Ag | Analog DC compensation |
Also Published As
| Publication number | Publication date |
|---|---|
| AT506857B1 (en) | 2010-02-15 |
| WO2009144129A2 (en) | 2009-12-03 |
| US8587289B2 (en) | 2013-11-19 |
| US20110068770A1 (en) | 2011-03-24 |
| EP2286512A2 (en) | 2011-02-23 |
| CN102047558B (en) | 2013-11-06 |
| AT506857A1 (en) | 2009-12-15 |
| WO2009144129A3 (en) | 2010-01-28 |
| ATE552653T1 (en) | 2012-04-15 |
| EP2286512B1 (en) | 2012-04-04 |
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