CN102045056A - Level shifter with original components - Google Patents

Level shifter with original components Download PDF

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Publication number
CN102045056A
CN102045056A CN2009102051933A CN200910205193A CN102045056A CN 102045056 A CN102045056 A CN 102045056A CN 2009102051933 A CN2009102051933 A CN 2009102051933A CN 200910205193 A CN200910205193 A CN 200910205193A CN 102045056 A CN102045056 A CN 102045056A
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China
Prior art keywords
transistor
coupled
primary type
type assembly
inverter
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Pending
Application number
CN2009102051933A
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Chinese (zh)
Inventor
黄厚颖
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN2009102051933A priority Critical patent/CN102045056A/en
Publication of CN102045056A publication Critical patent/CN102045056A/en
Pending legal-status Critical Current

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Abstract

The invention provides a level shifter with original components, comprising a phase inverter, a first original component, a second original component, a first transistor and a second transistor, wherein the first ends of the first and the second transistors are coupled with a first voltage; the second end of the first transistor and a control end are respectively coupled with the first ends of the first and the second original components; the second end of the second transistor and the control end are respectively coupled with the first ends of the second and the first original components; the second end of the first original component and the control end are respectively coupled with the output end and the input end of the phase inverter; and the second end of the second original component and the control end are respectively coupled with the input end and the output end of the phase inverter.

Description

Level shifter with primary type assembly
Technical field
The present invention relates to a kind of level shifter, particularly relate to a kind of level shifter with primary type assembly.
Background technology
All dispose one or more integrated circuits (Integrated Circuit) in electronic product inside now.Along with the progress of science and technology, (core voltage) is also more and more lower for the employed core voltage of IC interior.Yet the operating voltage of integrated circuit outside (or be called output go into voltage) normally is different from its inner core voltage, therefore needs level shifter to go into the function that level conversion is provided between voltage and the core voltage in output.
Fig. 1 is existing voltage level converting 100.Please refer to Fig. 1, it comprises inverter 150, N NMOS N-channel MOS N (N channel metal oxide semiconductor, NMOS) transistor 130, nmos pass transistor 140, P-channel metal-oxide-semiconductor (P channel metal oxide semiconductor, PMOS) transistor 110 and PMOS transistor 120.Inverter 150 is powered by core voltage VDD.The input receiving inputted signal V of inverter 150 INThe grid of nmos pass transistor 130 is coupled to the input of inverter 150, and the drain electrode of nmos pass transistor 130 is coupled to the drain electrode of PMOS transistor 110, and the source electrode of nmos pass transistor 130 is ground connection then.The grid of nmos pass transistor 140 is coupled to the output of inverter 150, and the drain electrode of nmos pass transistor 140 is coupled to the drain electrode of PMOS transistor 120, and source electrode is ground connection then.The source electrode of PMOS transistor 110 couples output and goes into voltage VDDIO, and the grid of PMOS transistor 110 is coupled to the drain electrode of PMOS transistor 120.The source electrode of PMOS transistor 120 couples output and goes into voltage VDDIO, and the grid of PMOS transistor 120 is coupled to the drain electrode of PMOS transistor 110.Wherein, the drain electrode of PMOS transistor 120 provides output signal V OUTAs input signal V INDuring for logic high, can make nmos pass transistor 130 conductings (turn on) and nmos pass transistor 140 by (turn off).Nmos pass transistor 130 conducting meetings make its drain electrode be pulled to logic low.Therefore, PMOS transistor 120 conductings and make that its drain electrode (is output signal V OUT) be pulled to logic high, finish from core voltage VDD and be converted to the transposition conversion that voltage VDDIO is gone in output.Otherwise, as input signal V INDuring for logic low, PMOS transistor 110 and nmos pass transistor 140 conductings, and PMOS transistor 120 ends with nmos pass transistor 130, so output signal V OUTBe pulled to logic low.
Yet, as input signal V INBy the logic high transition during to logic low, the grid of PMOS transistor 120 still is maintained at logic low and makes PMOS transistor 120 be in conducting state, exceed (pull up) ability of pulling on of PMOS transistor 120 up to (pull down) ability of leaving behind of nmos pass transistor 140, just can conducting PMOS transistor 110 and make output signal V OUTBe pulled to logic low.The electric current of nmos pass transistor (ability of leaving behind) is to be positively correlated with Vgs-Vt, and wherein Vgs represents the grid-source voltage of nmos pass transistor, and Vt represents the critical voltage (threshold voltage) of nmos pass transistor.Therefore advanced more when technology, core voltage VDD is low more, and when using core voltage VDD operation nmos pass transistor 140 (or 130), Vgs can be very little, causes the nmos pass transistor 140 (or 130) can't be with output signal V OUTLeave behind.
Summary of the invention
The present invention proposes a kind of level shifter, comprises first inverter, the first primary type assembly, the second primary type assembly, the first transistor and transistor seconds.The first primary type assembly has first end, second end and control end, and wherein second end and control end are coupled to the output and the input of first inverter respectively.The second primary type assembly has first end, second end and control end, and wherein second end and control end are coupled to the input and the output of first inverter respectively.The first transistor has first end, second end and control end, and wherein second end and control end are coupled to first end of first and second primary type assembly respectively.Transistor seconds has first end, second end and control end, and wherein second end and control end are coupled to first end of the second and first primary type assembly respectively.Aforementioned first and second transistorized first end is coupled to first voltage.
In one embodiment of this invention, above-mentioned level shifter also comprises the 3rd transistor and the 4th transistor.The 3rd transistor is coupled between the first transistor and the first primary type assembly, wherein the 3rd transistorized first end is coupled to second end of the first transistor, the 3rd transistorized second end is coupled to first end of the first primary type assembly, and the 3rd transistorized control end is coupled to the input of first inverter.The 4th transistor is coupled between the transistor seconds and the second primary type assembly, wherein the 4th transistorized first end is coupled to second end of transistor seconds, the 4th transistorized second end is coupled to first end of the second primary type assembly, and the 4th transistorized control end is coupled to the output of first inverter.
In one embodiment of this invention, described level shifter also comprises second inverter, and wherein the output of this second inverter is coupled to the input of first inverter.
Based on above-mentioned, even if core voltage is very low, the embodiment of the invention is conducting primary type assembly and make the output voltage transition really still.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 is existing voltage level converting.
Fig. 2 is the circuit diagram that a kind of level shifter is described according to the embodiment of the invention.
Fig. 3 is the circuit diagram that a kind of level shifter is described according to another embodiment of the present invention.
Fig. 4 is the circuit diagram that a kind of level shifter is described according to further embodiment of this invention.
The reference numeral explanation
100: the conventional voltage level shifting circuit
110,120:PMOS transistor
130,140:NMOS transistor
150: inverter
200,300,400: level shifter
210: the first transistor
220: transistor seconds
230: the first primary type assemblies
240: the second primary type assemblies
250: the first inverters
360: the second inverters
470: the three transistors
480: the four transistors
VDD: core voltage
VDDIO: voltage is gone in output
V IN: input signal
V IN': anti-phase input signal
V OUT: output signal
V OUT': anti-phase output signal
Embodiment
Fig. 2 is the circuit diagram that a kind of level shifter is described according to the embodiment of the invention.Please refer to Fig. 2, level shifter 200 comprises the first transistor 210, transistor seconds 220, the first primary type assembly 230, the second primary type assembly 240 and first inverter 250.In present embodiment, the first transistor 210 is PMOS transistors with transistor seconds 220, and the first primary type assembly 230 and the second primary type assembly 240 then are primary type N NMOS N-channel MOS N (native NMOS) transistors.In any case the implementation of transistor 210,220 and primary type assembly 230,240 is not limited thereto.
First inverter 250 is powered by second voltage (for example core voltage VDD).The input receiving inputted signal V of first inverter 250 IN, its output then provides signal V IN', signal V wherein IN' be input signal V INInversion signal.First end of the first transistor 210 (for example source electrode) is coupled to first voltage (for example voltage VDDIO is gone in output), second end of the first transistor 210 (for example drain electrode) is coupled to first end (for example drain electrode) of the first primary type assembly 230, and the control end of the first transistor 210 (for example grid) is coupled to first end (for example drain electrode) of the second primary type assembly 240.First end of transistor seconds 220 (for example source electrode) is coupled to output and goes into voltage VDDIO, second end of transistor seconds 220 (for example drain electrode) is coupled to the drain electrode of the second primary type assembly 240, and the control end of transistor seconds 220 (for example grid) is coupled to the drain electrode of the first primary type assembly 230.Second end of the first primary type assembly 230 (for example source electrode) and control end (for example grid) are coupled to the output and the input of first inverter 250 respectively.Second end of the second primary type assembly 240 (for example source electrode) and control end (for example grid) are coupled to the input and the output of first inverter 250 respectively.The drain voltage of transistor seconds 220 is as the output signal V of level shifter 200 OUT, and the drain voltage of the first transistor 210 can be as anti-phase output signal V OUT'.Above-mentioned output is gone into voltage VDDIO and is higher than core voltage VDD.
In the present embodiment, primary type assembly the 230, the 240th has the primary type nmos pass transistor of negative critical voltage.The electric current (ability of leaving behind) of primary type assembly 230,240 of flowing through be positively correlated with Vgs-(Vt), wherein Vgs represents the grid-source voltage of primary type assembly 230,240, and-Vt represents the critical voltage of primary type assembly 230,240.Therefore, when using core voltage VDD operation primary type assembly 230 (or 240), cause Vgs very little even core voltage VDD is very low, the electric current of primary type assembly 240 (or 230) (ability of leaving behind) is enough with output signal V OUT(or reversed-phase output signal V OUT') leave behind.
In the present embodiment, primary type assembly 230,240 has initial conducting (already-on) characteristic, and needing that therefore primary type assembly 230,240 is applied negative Vgs voltage could end really.Therefore, the grid of the first primary type assembly 230, source electrode are coupled to the input and the output of first inverter 250 respectively in the present embodiment, and the grid of the second primary type assembly 240, source electrode are coupled to the output and the input of first inverter 250 respectively.When the grid of the second primary type assembly 240 is logic low (for example earth level), the source electrode of the second primary type assembly 240 must be logic high (for example core voltage VDD), therefore forms negative Vgs voltage between the gate-to-source of the second primary type assembly 240 and comes by the second primary type assembly 240.The class of operation of the first primary type assembly 230 is similar to the second primary type assembly 240, so will not give unnecessary details.
Those skilled in the art can realize the present invention with reference to the foregoing description.Yet implementation of the present invention should be therefore not limited.Those skilled in the art can change the foregoing description according to its design requirement.For example, Fig. 3 is the circuit diagram that a kind of level shifter 300 is described according to another embodiment of the present invention.Level shifter 300 is similar in appearance to level shifter shown in Figure 2 200, and the implementation of the two can cross-reference.The two difference is that level shifter 300 has also disposed second inverter 360, and with the drain voltage of the first transistor 210 output signal V as level shifter 300 OUTThe drain voltage of transistor seconds 220 is anti-phase output signal V OUT'.
Please refer to Fig. 3, the input receiving inputted signal V of second inverter 360 IN, and its output is coupled to the input of first inverter 250.Wherein, first inverter 250 and second inverter 360 are powered by core voltage VDD.
Fig. 4 is the circuit diagram that a kind of level shifter 400 is described according to further embodiment of this invention.Level shifter 400 is similar in appearance to level shifter shown in Figure 2 200 and level shifter 300 shown in Figure 3, and three's implementation can cross-reference.Level shifter 400 is different from level shifter 200,300 parts, is that level shifter 400 has also disposed second inverter 360, the 3rd transistor 470 and the 4th transistor 480.In present embodiment, the 3rd transistor 470 and the 4th transistor 480 are PMOS transistors, but not as limit.
The 3rd transistor 470 is coupled between the first transistor 210 and the first primary type assembly 230, wherein first end of the 3rd transistor 470 (for example source electrode) is coupled to the drain electrode of the first transistor 210, second end of the 3rd transistor 470 (for example drain electrode) is coupled to the drain electrode of the first primary type assembly 230, and the control end of the 3rd transistor 470 (for example grid) is coupled to the input of first inverter 250.The 4th transistor 480 is coupled between the transistor seconds 220 and the second primary type assembly 240, wherein first end of the 4th transistor 480 (for example source electrode) is coupled to the drain electrode of transistor seconds 220, second end of the 4th transistor 480 (for example drain electrode) is coupled to the drain electrode of the second primary type assembly 240, and the control end of the 4th transistor 480 (for example grid) is coupled to the output of first inverter 250.Level shifter 400 is as output signal V with the drain voltage of the 3rd transistor 470 (drain voltage of the first primary type assembly 230 just) OUTThe drain voltage of the 4th transistor 480 is anti-phase output signal V OUT'.
In sum, utilize primary type assembly 230,240 to have the characteristic of low critical voltage or negative critical voltage, promote output signal V OUT(or reversed-phase output signal V OUT) the ability of leaving behind.Therefore, even make above-mentioned all embodiment with the advanced process of low core voltage, the level shifter of the embodiment of the invention still can regular event and make the output voltage transition.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.

Claims (10)

1. level shifter comprises:
One first inverter;
One first primary type assembly, it has one first end, be coupled to one second end of output of this first inverter and a control end that is coupled to the input of this first inverter;
One second primary type assembly, it has one first end, be coupled to one second end of input of this first inverter and a control end that is coupled to the output of this first inverter;
One the first transistor, one second end of first end that it has one first end that is coupled to one first voltage, be coupled to this first primary type assembly and a control end that is coupled to first end of this second primary type assembly; And
One transistor seconds, one second end of first end that it has one first end that is coupled to this first voltage, be coupled to this second primary type assembly and a control end that is coupled to first end of this first primary type assembly.
2. level shifter as claimed in claim 1, wherein this first inverter is powered by one second voltage.
3. level shifter as claimed in claim 2, wherein this first voltage is that voltage is gone in an output, and this second voltage is a core voltage.
4. level shifter as claimed in claim 3, wherein this is exported into voltage and is higher than this core voltage.
5. level shifter as claimed in claim 1, wherein this first transistor and this transistor seconds are the P-channel metal-oxide-semiconductor transistors.
6. level shifter as claimed in claim 1, wherein this first primary type assembly and this second primary type assembly are primary type N channel metal oxide semiconductor transistors.
7. level shifter as claimed in claim 1 also comprises:
One the 3rd transistor, be coupled between this first transistor and this first primary type assembly, wherein the 3rd transistorized first end is coupled to second end of this first transistor, the 3rd transistorized second end is coupled to first end of this first primary type assembly, and the 3rd transistorized control end is coupled to the input of this first inverter; And
One the 4th transistor, be coupled between this transistor seconds and this second primary type assembly, wherein the 4th transistorized first end is coupled to second end of this transistor seconds, the 4th transistorized second end is coupled to first end of this second primary type assembly, and the 4th transistorized control end is coupled to the output of this first inverter.
8. level shifter as claimed in claim 7, wherein this first transistor, this transistor seconds, the 3rd transistor AND gate the 4th transistor are the P-channel metal-oxide-semiconductor transistors.
9. level shifter as claimed in claim 1 also comprises one second inverter, and wherein the output of this second inverter is coupled to the input of this first inverter.
10. level shifter as claimed in claim 9, wherein this first inverter and this second inverter are powered by one second voltage.
CN2009102051933A 2009-10-16 2009-10-16 Level shifter with original components Pending CN102045056A (en)

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CN2009102051933A CN102045056A (en) 2009-10-16 2009-10-16 Level shifter with original components

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108736878A (en) * 2017-04-13 2018-11-02 华邦电子股份有限公司 Voltage level shifter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108736878A (en) * 2017-04-13 2018-11-02 华邦电子股份有限公司 Voltage level shifter

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Application publication date: 20110504