CN102035778A - Digital baseband processor used for wideband wireless communication - Google Patents
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Abstract
The invention provides a digital baseband processor, which comprises an uplink transmitter, a downlink receiver, a centralized storage and an access concentrator, wherein the uplink transmitter comprises an uplink processing first part comprising channel coding, quadrature amplitude modulation (QAM) and inverse discrete Fourier transform (IDFT), and an uplink processing second part used for performing CP insertion, shaping filter and timing transmission operation; the downlink receiver comprises a downlink processing first part used for frame synchronization processing, a downlink processing second part used for performing CP removal, orthogonal frequency division multiplexing (OFDM) demodulation, synchronization, multiple input multiple output (MIMO) decoding, QAM soft demodulation and rate de-matching operation on data, and a downlink processing third part used for performing channel decoding and check operation; and the access concentrator comprises a first access port connected with the downlink processing first part and a downlink processing second part, a third access port connected with the downlink processing third part, and a second access port connected with the uplink processing first part and the uplink processing second part.
Description
Technical field
The present invention relates to wireless communication field, particularly be used for the digital baseband processor of broadband wireless communications.
Background technology
Along with people's vigorous day by day to high-speed radio multi-medium data business demand, industry also is devoted to the research and development of high-speed radiocommunication system always.The hardware circuit solution of existing 2G (GSM) data in mobile phone is 9.6kbps, the hardware circuit solution of 3G (CDMA2000/WCDMA/TD-SCDMA) data in mobile phone also only is 2Mbps, be difficult to satisfy user's actual demand, therefore also do not have under the situation of large scale investment commercialization in the 3G system, the expert of moving communicating field has begun to carry out 4G (or B3G) systematic research and development both at home and abroad.Advanced at present broadband wireless communications agreement is mainly LTE and LTE+ and the agreements such as IEEE 802.16e, 802.16m of 3GPP.In above-mentioned communication protocol, the transmission rate of data communication protocol more in the past has great raising, and the peak rate of descending 100Mbps, up 50Mbps can be provided under the 20MHz spectral bandwidth as 3GPP LTE; The peak rate of the another one standard 802.16e/WiMAX of 3G is 40Mbps nearly also.Just because of above-mentioned communication system need realize high message transmission rate, corresponding communication terminal must possess high data throughput capabilities.
Digital baseband processor is the important component part of communication terminal.With the user terminal in the communication terminal is example, user terminal mainly comprises digital baseband processor, radio-frequency module, protocol stack processor etc., digital baseband processor is handled accordingly to data, finish operations such as digital-to-analogue conversion, frequency inverted by radio-frequency module, final realization is communicated by letter with communication base station.Just as mentioned before, system of broadband wireless communication requires communication terminal that high data throughput capabilities is arranged, and also just correspondingly requires the digital baseband processor in the communication terminal to preserve and read lot of data in the process that base band data is handled.A plurality of jumbo buffer memorys should be arranged in the digital baseband processor.According to the existing chip processing technology, the buffer memory that is added in the chip generally all adopts static random-access memory (SRAM), and SRAM exists storage density low at present, the defective that unit are is big.Therefore, when needing a plurality of jumbo buffer memory in the digital baseband processor, if in digital baseband processor the SRAM memory of integrated several bulks, can increase chip area, improve chip cost, and the integrated a plurality of SRAM of chip internal can make also the chip back end design very complicated.These shortcomings all are unfavorable for business development and use.
Summary of the invention
The digital baseband processor cost height, the chip area that the objective of the invention is to overcome the integrated large capacity cache of existing needs are big, be unfavorable for the defective of business development and use, thereby a kind of low-cost digital baseband processor that does not influence handling property is provided.
The invention provides a kind of digital baseband processor, comprise the LAC of upstream transmitter, downlink receiver, pooled storage and this pooled storage; Wherein,
Described upstream transmitter comprises up the processings first that is used for chnnel coding, QAM modulation and IDFT conversion, and is used for the resulting symbol of described up processing first done and inserts the up processing second portion that CP, shaping filter, timed sending operate;
Described downlink receiver comprises the downlink processing first that is used for the frame synchronization pre-treatment, be used for to data be CP, OFDM demodulation, synchronously, MIMO decoding, the soft demodulation of QAM, separate the downlink processing second portion of rate adaptation operating, and the downlink processing third part that is used to do channel decoding and verification operation;
Described LAC comprises first access port that is connected with the input interface of the output interface of described downlink processing first and described downlink processing second portion, the 3rd access port that is connected with the output interface of the input interface of described downlink processing third part and described downlink processing third part, second access port that is connected with the input interface of the output interface of described up processing first and up processing second portion; Described first access port, second access port, the 3rd access port are used to visit described pooled storage.
In the technique scheme, described LAC also comprises access interface that described pooled storage is correlated with and the moderator that the access order of described pooled storage is controlled, and described first access port, second access port, the 3rd access port are visited described pooled storage by described access interface under the control of described moderator.
In the technique scheme, described first access port, second access port and the 3rd access port all comprise and write register and readout register; Wherein, when carrying out write operation, earlier data are write readout register, write when full, data are write described pooled storage by the said write register when described readout register; Elder generation is from described readout register sense data, when described readout register is sky, from described pooled storage reading of data when carrying out read operation.
In the technique scheme, for realizing writing the real-time operation of data, the register that writes of described access port is two and writes register and be used alternatingly; For realizing the real-time operation of sense data, the readout register of described access port is that two readout registers are used alternatingly.
In the technique scheme, described pooled storage realizes on phy chip that during fabrication or directly described phy chip is the chip that is used to realize described upstream transmitter, downlink receiver and LAC.
In the technique scheme, described pooled storage is independent of phy chip during fabrication but together encapsulates with phy chip, and described phy chip is the chip that is used to realize described upstream transmitter, downlink receiver and LAC.
In the technique scheme, described pooled storage is independent of phy chip during fabrication and does not together encapsulate with phy chip, and described phy chip is the chip that is used to realize described upstream transmitter, downlink receiver and LAC.
In the technique scheme, when described pooled storage was independent of described phy chip, it adopted any one realization in DDR SDRAM, DDR2SDRAM, DDR3SDRAM or the FCRAM memory etc.
In the technique scheme, described moderator is that first access port is write the write order of described pooled storage and second access port is read the upstream that will send from described pooled storage the highest priority of read command setting with the downstream data flow that is received, and set these two orders with limit priority and can not take place simultaneously, for other read write command is set priority according to the time order and function order.
In the technique scheme, described first access port, second access port all carry out in strict accordance with the mode of first-in first-out the reading and writing data of pooled storage, the 3rd access port is unit to the reading and writing data of pooled storage to mix automatic retransmission processes, and each retransmission processes carries out reading and writing data to the address space that is assigned with in the pooled storage in strict accordance with the mode of first-in first-out.
Digital baseband processor of the present invention is compared than the chip of existing techniques in realizing, and chip area is littler, and chip cost is lower.
Description of drawings
Fig. 1 is the schematic diagram of the storage of each access port in the digital baseband processor of the present invention;
Fig. 2 is the structure chart of digital baseband processor of the present invention.
Embodiment
The present invention will be described below in conjunction with the drawings and specific embodiments.
For the ease of understanding, in one embodiment of the invention, be example with the user terminal that adopts the TD-LTE standard among the 3GPP LTE, the structure and the course of work of the digital baseband processor in this user terminal is illustrated.But those of ordinary skill in the art should understand, and digital baseband processor of the present invention can be used for adopting the user terminal of other standards equally.
Because in the present embodiment, digital baseband processor is arranged in user terminal, the therefore up communication of being mentioned hereinafter that is meant the user terminal to base station direction, and the communication of user terminal direction is arrived in the descending base station that is meant.Digital baseband processor has comprised upstream transmitter and downlink receiver.
According to the TD-LTE standard, downlink receiver should comprise following operation to the processing of downlink data: filtering, OFDM demodulation, the soft mediation channel decoding etc. of separating of QAM.According to above-mentioned functions, the functional module of downlink receiver can be further divided into three parts, represents with downlink processing first, downlink processing second portion and downlink processing third part respectively.Downlink processing first is as the processing procedure that receives before digital front-end is mainly finished frame synchronization, and in the related TD-LTE standard of present embodiment, this processing procedure can comprise interpolation, time-domain filtering and the removal of carrier residual frequency etc.The downlink processing second portion then mainly finish to the input data go CP, OFDM demodulation, synchronously, MIMO decoding, the soft demodulation of QAM, separate operation such as rate-matched.The downlink processing third part is mainly finished channel decoding and verification, uploads (giving protocol stack processor) or is abandoned operation, in addition, if the data of importing are data retransmission, the downlink processing third part then also needs the data of previous redundancy versions are done merging, decoding, verification with this data retransmission, operation such as uploaded or abandon.
According to the TD-LTE standard, upstream transmitter should comprise following operation to the processing of upstream data: chnnel coding, QAM modulation, DFT, SC-FDM modulation etc.According to above-mentioned functions, the functional module of upstream transmitter can be further divided into two parts, represents with up processing first and up processing second portion respectively.Up processing first is used for the data that will send are done chnnel coding, QAM modulation, DFT and SC-FDM modulation etc.Up processing second portion is used for that up first is handled the resulting SC-FDM symbol in back and inserts CP, shaping filter, and timed sending data.
The data volume of the result of downlink processing first, downlink processing second portion and up processing first is very big, needs special-purpose large capacity cache and is stored.With in the prior art common in each functional module of digital baseband processor, add special buffer memory different be, the present invention is used for data cached pooled storage for these functional modules in the digital baseband processor provide one, and the access port of reading and writing this pooled storage, these access ports are included in the digital baseband processor.
Fig. 2 has provided the schematic diagram of the digital baseband processor that is adopted in the present embodiment.As can be seen from the figure, between downlink processing first and downlink processing second portion, include access port A, what be connected with the downlink processing third part has an access port C, includes access port B between up processing first and up processing second portion.Above-mentioned access port both can be done read operation, also can do write operation.Described access port by the access interface relevant with type of memory come with described pooled storage in the appropriate address space communicate in first-in first-out (FIFO) mode.As a kind of preferred implementation, present embodiment not be for the accessing operation that guarantees a plurality of access ports can clash each other, also includes to be used for moderator that the priority of read write command is judged.Three above-mentioned access ports, moderator and the access interface of described pooled storage formed LAC jointly.Realize communicating by letter between upstream transmitter, downlink receiver and pooled storage by this LAC.
Though described pooled storage logically is regarded as the part of whole digital baseband processor, but with regard to physical structure, it and be used to realize relation between the phy chip of described upstream transmitter, downlink receiver and LAC have multiple may.For example, described pooled storage directly realizes on described phy chip, also can be independent of phy chip, but together encapsulates with phy chip; Also can be independent of phy chip, and together not encapsulate with this chip.In the present invention, because described pooled storage can be made in outside the described phy chip during fabrication, therefore except can adopting the realization of SRAM memory, also can adopt any one realization in DDR SDRAM, DDR2SDRAM, DDR3SDRAM or the FCRAM memories such as (Fast Cycle RAM).Even pooled storage is made on the described phy chip, also can improve storage density by the read-write parts that merge a plurality of SRAM, reduce the work difficulty of chip back end design.
After the overall structure of pooled storage was done above-mentioned explanation, the structure that each access port in the pooled storage is embodied in a preferred embodiment below with reference to Fig. 1 was formed and the operation that will finish in the read-write process describes.
In access port A, be built-in with: pooled storage base address (BaseAddreA), maximum visit storage depth (Max_DepthA), data width (Bit_WidthA), two write register (WR_regA0 and WR_regA1) and a readout register (RD_regA), two memory access pointers (write pointer WR_ptA and read pointer RD_ptA), FIFO sky indicated value (Empty_FlagA) and current data degree of depth indicated value (Cur_DepthA).Writing with the length of readout register wherein represented with Reg_SizeA, and the maximal bit capacity is represented with Bit_WidthA * Reg_SizeA.
BaseAddreA is the initial starting position of data in pooled storage of port A.During initial condition, WR_regA0, WR_regA1 and RD_regA are sky, and Empty_FlagA is 1, and Cur_DepthA is 0, and WR_ptA and RD_ptA are equal to 0.During data, data write RD_regA earlier as input, and Empty_FlagA is clear 0, and Cur_DepthA increases Reg_SizeA.When RD_regA when full, data write WR_regA0, the data of WR_regA0 are write when full, data write and switch to WR_regA1, start the write operation of a pooled storage simultaneously, all data that WR_regA0 is current write the space of pooled storage address from (BaseAddreA+WR_ptA) to (BaseAddreA+WR_ptA+Reg_SizeA-1) in proper order by the access port of pooled storage, and WR_ptA is increased Reg_SizeA, and Cur_DepthA increases Reg_SizeA.When WR_ptA reached Max_DepthA, WR_ptA put 0, continued the write operation process.
When the data of WR_regA1 are write when full, data write and switch to WR_regA0, start the write operation of a pooled storage simultaneously, all data that WR_regA1 is current write the space of pooled storage address from (BaseAddreA+WR_ptA) to (BaseAddreA+WR_ptA+Reg_SizeA-1) in proper order by the access port of pooled storage, and WR_ptA increased Reg_SizeA, Cur_DepthA increases Reg_SizeA.As above repeat to be used alternatingly WR_regA0 and WR_regA1 buffer memory input data.
When needs during sense data, are checked Empty_FlagA from access port A, if 1, wait for that the Empty_FlagA state changes; If 0, from RD_regA, read earlier, and Cur_DepthA is reduced Reg_SizeA.If Cur_DepthA is 0, then Empty_FlagA puts 1, otherwise whether checks Cur_DepthA less than Reg_SizeA, if Cur_DepthA less than Reg_SizeA, waits for that then Cur_DepthA occurs more than or equal to the Reg_SizeA state; If Cur_DepthA is more than or equal to Reg_SizeA, then start read operation, access port by pooled storage from pooled storage address (BaseAddreA+RD_ptA) to (BaseAddreA+RD_ptA+Reg_SizeA-1) reading of data, and RD_ptA increased Reg_SizeA, Cur_DepthA reduces Reg_SizeA.When RD_ptA reached Max_DepthA, RD_ptA put 0, continued the read operation process.
In access port B, be built-in with: pooled storage base address (BaseAddreB) and maximum visit storage depth (Max_DepthB), data width (Bit_WidthB), one write register (WR_regB) and two readout registers (RD_regB0 and RD_regB1), two memory access pointers (write pointer WR_ptB and read pointer RD_ptB), FIFO sky indicated value (Empty_FlagB) and current data degree of depth indicated value (Cur_DepthB).Writing with the length of readout register wherein represented with Reg_SizeB, and the maximal bit capacity is represented with Bit_WidthB * Reg_SizeB.
During initial condition, WR_regB and RD_regB0, RD_regB1 are sky, and Empty_FlagB is 1, and Cur_DepthB is 0, and WR_ptB and RD_ptB are equal to 0.During data, data write RD_regB0 earlier as input, and RD_regB0 is when full, and Empty_FlagB is clear 0, and Cur_DepthB increases Reg_SizeB.Switching simultaneously writes RD_regB1, and when RD_regB1 was full, Cur_DepthB increased Reg_SizeB.Data write WR_regB, when WR_regB when full, start the write operation of a pooled storage, all data that WR_regB is current write the space of pooled storage address from (BaseAddreB+WR_ptB) to (BaseAddreB+WR_ptB+Reg_SizeB-1) in proper order, and WR_ptB increased Reg_SizeB, Cur_DepthB increases Reg_SizeB.When WR_ptB reached Max_DepthB, WR_ptB put 0, continued the write operation process.
When needs during sense data, are checked Empty_FlagB from access port B, if 1, wait for that the Empty_FlagA state changes; If 0, from RD_regB0, read earlier, and Cur_DepthB is reduced Reg_SizeB.If Cur_DepthB is 0, then Empty_FlagB puts 1, otherwise whether checks Cur_DepthB less than Reg_SizeB, if Cur_DepthB less than Reg_SizeB, waits for that then Cur_DepthB occurs more than or equal to the Reg_SizeB state; If Cur_DepthB is more than or equal to Reg_SizeB, then from RD_regB1, read, start a read operation simultaneously, access port by pooled storage from pooled storage address (BaseAddreB+RD_ptB) to (BaseAddreB+RD_ptB+Reg_SizeB-1) reading of data to RD_regB0, and RD_ptB increased Reg_SizeB, Cur_DepthB reduces Reg_SizeB.When RD_ptB reached Max_DepthB, RD_ptB put 0, continued the read operation process.
If Cur_DepthB is 0, then Empty_FlagB puts 1, otherwise whether checks Cur_DepthB less than Reg_SizeB, if Cur_DepthB less than Reg_SizeB, waits for that then Cur_DepthB occurs more than or equal to the Reg_SizeB state; If Cur_DepthB is more than or equal to Reg_SizeB, then from RD_regB0, read, start a read operation simultaneously, access port by pooled storage from pooled storage address (BaseAddreB+RD_ptB) to (BaseAddreB+RD_ptB+Reg_SizeB-1) reading of data to RD_regB1, and RD_ptB increased Reg_SizeB, Cur_DepthB reduces Reg_SizeB.As above repeat to be used alternatingly RD_regB0 and RD_regB1 buffer memory dateout.
In access port C, be built-in with: pooled storage base address (BaseAddreC) and maximum visit storage depth (Max_DepthC), data width (Bit_WidthC), one writes a register (WR_regC) and a readout register (RD_regC), for each HARQ process two memory access pointers (write pointer WR_ptC_process_m and read pointer RD_ptC_process_m) are arranged all, corresponding to the side-play amount (Addre_process_m) of pooled storage base address with and the maximum visit degree of depth (Max_DepthC_process_m), empty indicated value (Empty_FlagC_process_m) of FIFO and current data degree of depth indicated value (Cur_DepthC_process_m).Wherein the Addre_process_m of each HARQ process and Max_DepthC_process_m parameter can be fixed, and also can be to redistribute in a period of time.Write and the length of readout register of access port C are represented with Reg_SizeC, and the maximal bit capacity is represented with Bit_WidthC * Reg_SizeC.It is as follows to be with the data read-write operation of HARQ process m that example describes:
During initial condition, WR_regC and RD_regC are sky, Empty_FlagC_process_m is 1, and CurDepthC_process_m is 0, and WR_ptC_process_m and RD_ptC_process_m are equal to the pairing base address offset amount Addre_process_m of HARQ process m.During data, data write RD_regC earlier as input, and RD_regC is when full, and Empty_FlagC_process_m is clear 0, and Cur_DepthC_process_m increases Reg_SizeC.Data write WR_regC, when WR_regC when full, start the write operation of a pooled storage, all data that WR_regC is current write the space of pooled storage address from (BaseAddreC+WR_ptC_process_m) to (BaseAddreC+WR_ptC_process_m+Reg_SizeC-1) in proper order, and WR_ptC_process_m increased Reg_SizeC, Cur_DepthC_process_m increases Reg_SizeC.When WR_ptC_process_m reached Max_DepthC_process_m, WR_ptC_process_m put 0, continued the write operation process.
When needs during sense data, are checked Empty_FlagC_process_m from access port C, if 1, wait for that the Empty_FlagC_process_m state changes; If 0, from RD_regC, read earlier, and Cur_DepthC_process_m is reduced Reg_SizeC.If Cur_DepthC_process_m is 0, then Empty_FlagC_process_m puts 1, otherwise check that whether Cur_DepthC_process_m is less than Reg_SizeC, if Cur_DepthC_process_m less than Reg_SizeC, waits for that then Cur_DepthC_process_m occurs more than or equal to the Reg_SizeC state; If Cur_DepthC_process_m is more than or equal to Reg_SizeC, then start read operation, access port by pooled storage from pooled storage address (BaseAddreC+RD_ptC_process_m) to (BaseAddreC+RD_ptC_process_m+Reg_SizeC-1) reading of data, and RD_ptC_process_m increased Reg_SizeC, Cur_DepthC_process_m reduces Reg_SizeC.When RD_ptC_process_m reached Max_DepthC_process_m, RD_ptC_process_m put 0, continued the read operation process.
Foregoing description is to the structure of access port A, access port B, access port C and in the read-write process and the explanation done of the reciprocal process between described pooled storage.Those of ordinary skill in the art should understand, the composition of access port and be not limited to content in the foregoing description with the read-write process of pooled storage, those skilled in the art can do corresponding change to the composition of access port and with the read-write process of pooled storage in conjunction with actual conditions and prior art on the basis of the above description.
Below in conjunction with the processing procedure of digital baseband processor, above-mentioned access port role in data handling procedure is described upstream data and downlink data.
In the process of data downstream, the data flow that the base station sends arrives user terminal via wireless channel, and after doing analog-to-digital conversion via the radio-frequency module in the user terminal, digital signal enters downlink processing first, the processing do frame synchronization in this module before.The dateout of handling via downlink processing first is written to described access port A, as long as there is downlink data to arrive user terminal, the write operation of realizing via access port A will carry out always so.The storage order of access port A when doing write operation had detailed description in preamble, therefore do not repeat herein.If represent access port A with #A, the related write operation of being realized by access port A can be designated as #A W in this process so.
The downlink processing second portion will to downlink processing first data processed further do the input data go CP, OFDM demodulation, synchronously, MIMO decoding, the soft demodulation of QAM, separate operation such as rate-matched, therefore need pass through access port A reading of data.The data that read from access port A are unit with the OFDM symbol.Data read order when access port A does the read data operation has also had corresponding description in preamble.Data after processing via the downlink processing second portion, with the data after handling directly as the input data of downlink processing third part.If represent access port A with #A, the related read operation that is realized by access port A can be designated as #AR in this process so.
The downlink processing third part is done channel decoding and error checking to data.The dateout of downlink processing second portion can be that control information also can be a data message.Because there is not the re-transmission situation in control information, therefore below explanation is not done in the processing of control information, only the processing to data message is illustrated.Before data message is done channel decoding, whether the input data of at first judging the downlink processing third part are transmission for the first time, if, after then doing channel decoding by the downlink processing third part, further judge whether decode results is correct, if decoding is correct, the data block after the decoding is directly uploaded the MAC layer, does not also just need access port C is conducted interviews; If decoding error then will be written to the data before the channel decoding of downlink processing third part access port C.If the input data information of downlink processing third part is not the data of transmitting for the first time (data retransmission just), the downlink processing third part need be read original old redundancy versions from access port C before channel decoding so, itself and data retransmission are merged, carry out channel decoding again.If this time decoding still makes mistakes again, then need the version write-access port C after the aforementioned merging is waited for the arrival of data retransmission next time, correct up to decoding, or abandon the relevant data piece, no longer need to do retransmission operation.If represent access port C with #C, the related reading and writing operation that is realized by access port C can be designated as #C R, #C W respectively in this process so.
In the process that data uplink is handled, after chnnel coding, QAM modulation, DFT and SC-FDM modulation are done with want data block transmitted by up processing first, do write operation to realize the storage of result via access port B, up processing second portion is then read the transmission data of each SC-FDM symbol successively by access port B, insert CP then, and the timed sending data.If represent access port B with #B, the related reading and writing operation that is realized by access port B can be designated as #B R, #B W respectively in this process so.
In superincumbent data uplink, the data downstream processing procedure, exist many read write commands, should have priority between the different read write commands, to guarantee effective operation of digital baseband processor.Priority between different read write commands is judged and can be realized by aforesaid moderator.In the present embodiment, described priority judgment principle is specific as follows: #A W is a downlink data receiving stream, #B R is for sending upstream, these two orders all are subjected to constraint regularly, therefore priority is the highest, and when having many read write commands at the same time, #A W and #B R can interrupt other any read-write operations, and according to regularly requirement of TDD system up-downgoing, the storage request of pooled storage can not take place in #A W and #B R simultaneously; Cannot interrupt mutually between other read-write operations, need carry out according to the sequencing of time.
In the above-described embodiments, provided a kind of implementation of digital baseband processor of the present invention, in other embodiments, the implementation of digital baseband processor can have certain variation.For example, with the buffer memory set-point of described access port A in advance, as be positioned over before the carrier residual frequency removes, perhaps before the time-domain filtering, perhaps initial data with clock information is put etc.
Above embodiment is an example with the TD-LTE standard, in other standard, in the WiMAX standard, can adopt digital baseband processor of the present invention equally.Because the up SC-FDM modulation (the SC-FDM modulation is all used the IDFT conversion with the OFDM modulation) of having adopted the OFDM modulation to replace TD-LTE of WiMAX, therefore when digital baseband processor of the present invention is applied in the WiMAX standard, the output of up processing first and the input of up processing second portion all become the OFDM symbol, and no longer be the SC-FDM symbol, but can not impact for the 26S Proteasome Structure and Function of digital baseband processor itself.Same, digital baseband processor of the present invention is also applicable to semiduplex FDD system of broadband wireless communication.
The present invention is with a plurality of data cached being stored in the pooled storage in the broadband wireless communications baseband processor, and pooled storage can be independent of chip, with chip in same encapsulation or in the different encapsulation; Also can place chip internal.If pooled storage is independent of chip exterior, then can reduce chip area, reduce chip cost; If place chip internal, also can improve storage density by effective processing method, by merging the read-write parts of a plurality of SRAM, reduce the work difficulty of chip back end design.
It should be noted last that above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention is had been described in detail with reference to embodiment, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1. a digital baseband processor is characterized in that, comprises the LAC of upstream transmitter, downlink receiver, pooled storage and this pooled storage; Wherein,
Described upstream transmitter comprises up the processings first that is used for chnnel coding, QAM modulation and IDFT conversion, and is used for the resulting symbol of described up processing first done and inserts the up processing second portion that CP, shaping filter, timed sending operate;
Described downlink receiver comprises the downlink processing first that is used for the frame synchronization pre-treatment, be used for to data be CP, OFDM demodulation, synchronously, MIMO decoding, the soft demodulation of QAM, separate the downlink processing second portion of rate adaptation operating, and the downlink processing third part that is used to do channel decoding and verification operation;
Described LAC comprises first access port that is connected with the input interface of the output interface of described downlink processing first and described downlink processing second portion, the 3rd access port that is connected with the output interface of the input interface of described downlink processing third part and described downlink processing third part, second access port that is connected with the input interface of the output interface of described up processing first and up processing second portion; Described first access port, second access port, the 3rd access port are used to visit described pooled storage.
2. digital baseband processor according to claim 1, it is characterized in that, described LAC also comprises access interface that described pooled storage is correlated with and the moderator that the access order of described pooled storage is controlled, and described first access port, second access port, the 3rd access port are visited described pooled storage by described access interface under the control of described moderator.
3. digital baseband processor according to claim 1 and 2 is characterized in that, described first access port, second access port and the 3rd access port all comprise and write register and readout register; Wherein, when carrying out write operation, earlier data are write readout register, write when full, data are write described pooled storage by the said write register when described readout register; Elder generation is from described readout register sense data, when described readout register is sky, from described pooled storage reading of data when carrying out read operation.
4. digital baseband processor according to claim 3 is characterized in that, for realizing writing the real-time operation of data, the register that writes of described access port is two and is used alternatingly; For realizing the real-time operation of sense data, the readout register of described access port is two and is used alternatingly.
5. digital baseband processor according to claim 1 and 2, it is characterized in that, described pooled storage realizes on phy chip directly that during fabrication described phy chip is the chip that is used to realize described upstream transmitter, downlink receiver and LAC.
6. digital baseband processor according to claim 1 and 2, it is characterized in that, described pooled storage is independent of phy chip during fabrication but together encapsulates with phy chip, and described phy chip is the chip that is used to realize described upstream transmitter, downlink receiver and LAC.
7. digital baseband processor according to claim 1 and 2, it is characterized in that, described pooled storage is independent of phy chip during fabrication and does not together encapsulate with phy chip, and described phy chip is the chip that is used to realize described upstream transmitter, downlink receiver and LAC.
8. according to claim 6 or 7 described digital baseband processors, it is characterized in that when described pooled storage was independent of described phy chip, it adopted any one realization in DDR SDRAM, DDR2SDRAM, DDR3SDRAM or the FCRAM memory etc.
9. digital baseband processor according to claim 2, it is characterized in that, described moderator is that first access port is write the write order of described pooled storage and second access port is read the upstream that will send from described pooled storage the highest priority of read command setting with the downstream data flow that is received, and set these two orders with limit priority and can not take place simultaneously, for other read write command is set priority according to the time order and function order.
10. digital baseband processor according to claim 1 and 2, it is characterized in that, described first access port, second access port all carry out in strict accordance with the mode of first-in first-out the reading and writing data of pooled storage, the 3rd access port is unit to the reading and writing data of pooled storage to mix automatic retransmission processes, and each retransmission processes carries out reading and writing data to the address space that is assigned with in the pooled storage in strict accordance with the mode of first-in first-out.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103916337A (en) * | 2013-01-06 | 2014-07-09 | 中兴通讯股份有限公司 | Device and method for processing uplink base band data in long-term evolution process |
| CN108293027A (en) * | 2015-12-03 | 2018-07-17 | 华为技术有限公司 | The method that data stream unit and stream unit for operation data |
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| US8095699B2 (en) * | 2006-09-29 | 2012-01-10 | Mediatek Inc. | Methods and apparatus for interfacing between a host processor and a coprocessor |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103916337A (en) * | 2013-01-06 | 2014-07-09 | 中兴通讯股份有限公司 | Device and method for processing uplink base band data in long-term evolution process |
| WO2014106426A1 (en) * | 2013-01-06 | 2014-07-10 | 中兴通讯股份有限公司 | Method and device for processing uplink base band data in lte, and computer storage medium |
| CN103916337B (en) * | 2013-01-06 | 2019-04-23 | 中兴通讯股份有限公司 | Upstream baseband data processing unit and method in a kind of long term evolution |
| CN108293027A (en) * | 2015-12-03 | 2018-07-17 | 华为技术有限公司 | The method that data stream unit and stream unit for operation data |
| CN108293027B (en) * | 2015-12-03 | 2020-10-09 | 华为技术有限公司 | Data streaming unit and method for operating a data streaming unit |
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Assignee: Beijing Zhongke Jingshang Technology Co., Ltd. Assignor: Institute of Computing Technology, Chinese Academy of Sciences Contract record no.: 2011110000143 Denomination of invention: Digital baseband processor used for wideband wireless communication License type: Exclusive License Open date: 20110427 Record date: 20110823 |
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