CN102035550A - Circuit and method for solving instable power-on process of sigma-delta analog-to-digital conversion circuit - Google Patents
Circuit and method for solving instable power-on process of sigma-delta analog-to-digital conversion circuit Download PDFInfo
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Abstract
The invention provides a circuit and a method for solving the instable power-on process of a sigma-delta analog-to-digital conversion circuit. The circuit comprises controlled devices and a power supply detection circuit, wherein the controlled devices are connected with integrators of the sigma-delta analog-to-digital conversion circuit to be controlled, the power supply detection circuit provides control signals to the controlled devices according to the detected power supply condition of the power supply and can adopt a power-on reset circuit, and the existing power-on reset circuit of an SOC (System On Chip) with the sigma-delta analog-to-digital conversion circuit can be directly utilized to greatly lessen the circuit complexity of the SOC and effectively save the cost. In addition, the invention also provides the SOC of the power-on reset circuit shared by the sigma-delta analog-to-digital conversion circuit and other functional devices.
Description
Technical field
The present invention relates to a kind of unsettled circuit of control sigma-delta analog to digital conversion circuit and method, particularly a kind of solution ∑-unsettled circuit of Δ analog to digital conversion circuit power up and method.
Background technology
At the numerous areas of electron trade, especially in digital speech, audio frequency and detection metering device field, SOC (system on a chip) (being SOC, System On Chip) is widely used.What is called SOC system integrates the chip of multiple common function (handling, reach power management or the like as Audio Processing, Video processing, USB/DDR) exactly.And sigma-delta analog to digital conversion circuit (being Sigma-delta ADC) owing to have the conversion accuracy height, advantage becomes one of requisite member of each SOC (system on a chip) to the performance of analog circuit and device matching requirement be lower etc.
Existing sigma-delta ADC mainly is made of two parts, and one is simulation sigma-delta modulator, and another is a decimation filter of digital.The Sigma-delta modulator generally is made of one or more integrators, comparator and the DAC (analog to digital converter) that is on the feedback control loop; And decimation filter of digital is mainly used in outer spurious signal of the above quantizing noise of decay base band, restriction input signal bandwidth, inhibition zone and circuit noise etc., therefore, not only consumed power is big for it, and area occupied also can be more than the sigma-delta modulator on chip.For sigma-delta ADC, in order to reduce quantizing noise, the sigma-delta modulator all can be to noise shaping, and it realizes that the mode of noise shaping generally all is to adopt the sigma-delta modulator (circuit that promptly comprises a plurality of integration stages) of high-order.Yet, no matter be low order or higher order modulator, when input signal was imported the scope that is allowed greater than sigma-delta ADC, the saturated labile state of modulator all can appear.In case the modulator instability, even input signal changes over to normally, modulator can not got back to normal operating conditions automatically yet usually.
The modulator instability shows integrator non-linear (be integrator cause to plus or minus level direction integral for a long time saturated) or quantizer long term overloading (being that output signal is long-time for the highest or minimum) usually.When sigma-delta ADC powers on, the often the easiest modulator instability that occurs.No matter to low-order-modulated device (exponent number≤2) and higher order modulator (exponent number 〉=3), in power up, the saturated problem of unstable of modulator appears in the capital, for example, when input is that a large-signal (this large-signal is in the input signal allowed band) and the quantification reference voltage of ADC be not when also setting up fully, input signal will occur greater than the quantification reference voltage, thereby cause modulator saturated.In addition in power up, because the residing nondeterministic statement of integrator also may make modulator be in labile state.Therefore, in a single day sigma delta ADC need adopt auxiliary circuit to make modulator occur the saturated state that can return to operate as normal in power up.
In order to make the modulator working stability, the research staff has proposed several different methods, wherein comparatively is typically the integrator in the modulator is resetted.Promptly by the output signal of integrator or output state are detected to judge whether modulator is stable, if find unstablely, integrator is resetted, just make the input and output short circuit of integrator.As shown in Figure 1, it is the modulator circuit schematic diagram of a sigma-delta adc circuit.This modulator has 4 integrators, it is integrator 10,12,14, with 16, wherein, the input of each integrator and input are connected with a controlled switch respectively, promptly be connected controlled switch SW1 with input in integrator 10 inputs, be connected controlled switch SW2 with input in integrator 12 inputs, be connected controlled switch SW3 with input in integrator 14 inputs, be connected controlled switch SW4 with input in integrator 16 inputs, each controlled switch is by the output signal control of oscillation test comparator 20, oscillation test comparator 20 with the output of integrator 12 with compare with reference to thresholding, when the output of integrator 12 surpasses with reference to thresholding, then oscillation test comparator 20 output control signals make each controlled switch closure, thereby make each integrator input and output short circuit, realize thus resetting.
Though this kind control mode is simple, is difficult to accurately detect unsettled generation, because there is the certain precision deviation in the reference thresholding of comparator; And its unstable situation that can detect is also very limited, that is: only just 12 outputs surpass with reference to a kind of like this situation of thresholding at integrator.And in fact, the sigma-delta adc circuit power on or during power down the work of easier initiation integrator uncertain, for this situation, this kind method but is powerless.What is more important, the existing SOC (system on a chip) that disposes the sigma-delta adc circuit, its chip area is very limited, and this method need be set up oscillation test comparator 20 especially again in the limited space of SOC (system on a chip), so cause the interference between the device first easily, moreover unavoidably can increase the complexity of SOC (system on a chip) circuit, therefore, the utmost point is necessary to seek a kind of new method and solves sigma-delta ADC problem of unstable.
Summary of the invention
The object of the present invention is to provide a kind of solution sigma-delta unsettled circuit of analog to digital conversion circuit power up and method.
Another object of the present invention is to provide the SOC (system on a chip) that a kind of circuit is simple, cost is low.
Reach other purposes in order to achieve the above object, the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up provided by the invention, comprise: at least one controlled device is connected with an integration of sigma-delta analog to digital conversion circuit to be controlled separately; And power sense circuit, be connected with each controlled device, be used to detect the power supply situation of the power supply that offers described sigma-delta analog to digital conversion circuit to be controlled, and when detecting power supply instability, provide first control signal to each controlled device, each integrator is resetted, and after the detection power supply is stable, provide second control signal to each controlled device, make each integrator enter the integration operating state, thereby make the working stability of described sigma-delta analog to digital conversion circuit to be controlled.
The unsettled method of solution sigma-delta analog to digital conversion circuit power up of the present invention, comprise step: 1) when a power sense circuit detects the power supply that offers sigma-delta analog to digital conversion circuit to be controlled and is in the power supply instability state, described power sense circuit sends first control signal to each controlled device of each modulator that is connected described sigma-delta analog to digital conversion circuit to be controlled, so that each integrator resets; 2) when described power sense circuit detect the power supply power supply that offers sigma-delta analog to digital conversion circuit to be controlled stable after, described power sense circuit sends second control signal to each controlled device, so that each integrator is in the integration operating state, realize the working stability of described sigma-delta analog to digital conversion circuit to be controlled thus.
Wherein, described power supply instability state comprises the labile state that the power on labile state that causes and power down cause.
Preferable, described power sense circuit can be an electrify restoration circuit, especially can be low consumption circuit.Be to lower circuit complexity, the electrify restoration circuit that it also can directly adopt the SOC (system on a chip) self at described sigma-delta analog to digital conversion circuit place to be controlled to have.
Preferable, controlled device can be connected on the integrator in the modulator, for example, is connected between the input and output of integrator, and it can be a controlled switch, for example is relay, regular tap or metal-oxide-semiconductor etc.
Preferable, sigma-delta analog to digital conversion circuit to be controlled can be the low order sigma-delta analog to digital conversion circuit of exponent number≤2, cascade 2-1sigma-delta analog to digital conversion circuit or cascade 2-2sigma-delta analog to digital conversion circuit or the like.
SOC (system on a chip) of the present invention comprises at least: the sigma-delta analog to digital conversion circuit; Be connected each controlled device of described each integrator of sigma-delta analog to digital conversion circuit; At least one function element; And electrify restoration circuit, be used to detect the power supply situation of the power supply of access, and when detecting power supply instability, provide first control signal to each controlled device and described at least one function element, each integrator and at least one function element are resetted, and after the detection power supply is stable, provide second control signal to each controlled device and at least one function element, make each integrator enter the integration operating state, make at least one function element enter normal operating conditions simultaneously.
In addition, described function element can be: the oscillator in trigger, latch, register, counter, the analog circuit, comparator etc.
In sum, the unsettled Method and circuits of solution sigma-delta analog to digital conversion circuit power up of the present invention adopts direct working condition to power supply to detect, control the controlled device that respectively is connected between integrator input and the output, and then control resetting of each integrator, avoid the generation of the situation of the sigma-delta analog to digital conversion circuit job insecurity that brings because of power supply electrifying or power down.
Description of drawings
Fig. 1 is the existing circuit diagram that solves the integrator job insecurity of sigma-delta analog to digital conversion circuit.
Fig. 2 is the basic framework schematic diagram of the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention.
Fig. 3 is the embodiment schematic diagram of the workflow of the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention.
Fig. 4 is the specific embodiment schematic diagram of the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention.
The sequential relationship schematic diagram of each voltage of sigma-delta analog to digital conversion circuit that Fig. 5 is controlled for the unsettled circuit of solution of the present invention sigma-delta analog to digital conversion circuit power up.
The circuit diagram of the electrify restoration circuit that Fig. 6 is adopted for the unsettled circuit of solution of the present invention sigma-delta analog to digital conversion circuit power up.
Fig. 7 is a SOC (system on a chip) basic framework schematic diagram of the present invention.
Embodiment
The present invention is described in detail below with reference to accompanying drawing.
See also Fig. 2, it is the basic framework schematic diagram of the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention.Described circuit is used for control and comprises a plurality of integrators (for example integrator 1, integrator 2 ... integrator n, n is the integer more than or equal to 1) the sigma-delta analog to digital conversion circuit, the unsettled circuit of described solution sigma-delta analog to digital conversion circuit power up comprises: a plurality of controlled device and a power sense circuit.
Described a plurality of controlled device is connected with an integrator of described sigma-delta analog to digital conversion circuit separately, for example, controlled device 1 connects integrator 1, and controlled device 2 connects integrator 2 ... controlled device n connects integrator n, obviously, the number of controlled device is decided according to the number of integrator.One integrator can only be connected with a controlled device, for example, connects a controlled device between integrator input and output; In addition, an integrator also can be connected with a plurality of controlled device, for example, is connecting a controlled device respectively between the input of integrator and the electronegative potential and between the output of integrator and the electronegative potential.And each controlled device can be a controlled switch, includes but not limited to: 1) relay; 2) transistor, for example, metal-oxide-semiconductor etc.; 3) regular tap etc.
Described power sense circuit and each controlled device (are controlled device 1, controlled device 2 ... controlled device n) is connected, be used to detect the power supply situation of the power supply that offers described sigma-delta analog to digital conversion circuit to be controlled, so that provide control signal corresponding to each controlled device, make the working stability of described sigma-delta analog to digital conversion circuit to be controlled according to the result who is detected.As a preferred version, described power sense circuit can adopt electrify restoration circuit to detect the situation of power supply, but those skilled in the art should understand that, power sense circuit is not as limit, anyly can detect circuit that whether power supply be in firm unlatching or positive power down and all can be used as power sense circuit among the present invention.
Foregoing circuit avoids the unsettled method of sigma-delta analog to digital conversion circuit power up to be: when power sense circuit detects the power supply that offers sigma-delta analog to digital conversion circuit to be controlled and is in the power supply instability state, described power sense circuit is to controlled device 1, controlled device 2 ... controlled device n sends first control signal, so that integrator 1, integrator 2 ... integrator n resets; And when described power sense circuit detect the power supply power supply that offers sigma-delta analog to digital conversion circuit to be controlled stable after, described power sense circuit is to controlled device 1, controlled device 2 ... controlled device n sends second control signal, so that integrator 1, integrator 2 ... integrator n is in the integration operating state, realizes the working stability of described sigma-delta analog to digital conversion circuit to be controlled thus.
Say it more in detail, as shown in Figure 3, detect power supply by power sense circuit and whether rigidly connect logical (being whether power supply powers on), if, then described power sense circuit (for example sends first control signal to each controlled device, switch closure signals), make each controlled switch closure, each integrator that is connected with each controlled switch resets thus; And if power sense circuit does not detect the signal of power connection, promptly power supply is in disconnection, and then power sense circuit continues to wait for.
Then, behind power supply electrifying, whether power sense circuit detects power supply stable, if then send second control signal (for example, switch cut-off signal) to each controlled device, each controlled switch is disconnected, and each integrator that is connected with each controlled switch enters normal integration state thus; And if power supply is also unstable, then each controlled switch continues closure, and each integrator continues hold reset state.
Then, after power supply is stable, for a certain reason, suddenly power down, after then described power sense circuit detects this power loss event, then send first control signal (for example, switch closure signals) to each controlled device, make each integrator be returned to reset mode, after power supply is stable, enter the integration state again.And if do not have power loss event to take place, then each integrator is proceeded proper integral.
To be that example is more specifically described the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up of the present invention below with a cascade (mash) 2-2sigma-delta analog to digital conversion circuit.
As shown in Figure 4, mash 2-2sigma-delta analog to digital conversion circuit comprises: first order second order sigma-delta modulator, summing circuit 112, second level second order sigma-delta modulator, and described first order second order sigma-delta modulator and second level second order sigma-delta modulator output signal are carried out the noise cancellation logical block (being Noise cancel) of noise cancellation, it has the stability advantage of second-order modulator, can realize the noise shaping effect of fourth-order modulator of Figure simultaneously again.Wherein, first order second order sigma-delta modulator comprises: first single order integrating circuit, second single order integrating circuit and quantizer 107 serial connections form series circuit, and the output of quantizer 107 are carried out feeding back to after the digital-to-analogue conversion digital to analog converter (being DAC) 133 of first single order integrating circuit, and first single order integrating circuit comprises: integrator 103 and summing circuit 102 etc.; Second single order integrating circuit comprises: integrator 106 and summing circuit 105 etc.Quantizer 107 is actual to be exactly a simple comparator, generally speaking, in the sigma-delta modulator, does not have the strict design requirement usually for comparator, because the non-ideal characteristic of comparator all can be by loop filter noise shaping in addition.So a simple comparator that does not comprise preamplifier or imbalance bucking circuit just can meet the demands, and just relatively is fit to this application as latched comparator.Integrator 103, integrator 106 are all realized by the switching capacity method.Summing circuit 102 is sending into integrator 103 through scaler 101 (gain coefficient is a1) scaled input signals Vin and quantizer 107 through the difference of the signal of digital to analog converter (DAC) 133 and feedback path 108 (feedback factor is b1); Summing circuit 105 is sent into integrator 106 to the output signal and the quantizer 107 of the integrator 103 of process scaler 105 (gain coefficient is a2) convergent-divergent through the difference of the signal of digital to analog converter (DAC) 133 and feedback path 109 (feedback factor is b2), when integrator 106 is output as timing, it is negative for integrator is output as, positive reference signal of quantizer 107 feedbacks, send into summing circuit 102 and 105 through feedback path 108 and 109 respectively so that convergent-divergent Vin and integrator 103 outputs of convergent-divergent feed back a positive reference signal with quantizer 107 and subtracted each other.Equally, when integrator 106 is output as when negative, negative reference signal of quantizer 107 feedbacks is passed through feedback path 108 and 109 respectively, by summing circuit 102 and 105 will be added in respectively convergent-divergent Vin and convergent-divergent integrator 103 export and subtract each other with it.Therefore the integrator on these two rank has accumulated the poor of input signal and quantized output signal, and attempts to keep integrator output near zero.Integrator is output as zero and shows that input signal Vin and the difference that quantizes output are zero.In fact, the feedback of integrator and quantizer formation forces the local mean values of the local average value trace input signal of quantizer output.Second level second order sigma-delta modulator is identical with first order second order sigma-delta modulator structure, is the gain coefficient c1 of integrator 115, feedback factor g1, and the gain coefficient c2 of integrator 118 is different with feedback factor g2.Summing circuit 112 will be sent into second level second order sigma-delta modulator input after will suing for peace through integrator 106 output signals of scaler 110 (gain coefficient d1) convergent-divergent with through quantizer 107 output signals of scaler 111 convergent-divergents, and coefficient d 1 and d2 influence the noise transmission function of modulator.The noise cancellation logical block is sent in the output of the output of first order second order sigma-delta modulator and second level second order sigma-delta modulator, after summing junction 131 additions as the output Vout of whole ADC.Logic shown in the square frame of Fig. 4 the right is exactly the structure of noise cancellation logical block.
Because above-mentioned mash 2-2sigma-delta analog to digital conversion circuit comprises 4 integrators, it is integrator 103,106,115, with 118, so for realizing the control that resets of integrator to above-mentioned mash 2-2sigma-delta analog to digital conversion circuit, correspondent control circuits can comprise: 4 controlled switchs, it is controlled switch 127,128,129,130, wherein, controlled switch 127 is connected between the input and output of integrator 103, controlled switch 128 is connected between the input and output of integrator 106, controlled switch 129 is connected between the input and output of integrator 115, controlled switch 130 is connected between the input and output of integrator 118, controlled switch 127,128,129,130 separately controlled ends connect power sense circuit, for example, the output of electrify restoration circuit (being por circuit) 132.Because por circuit 132 General Definitions become electronegative potential effective, so controlled switch 127,128,129,130 can be realized by the PMOS pipe.And if that por circuit 132 is defined as high potential is effective, then controlled switch 127,128,129,130 can be realized by the NMOS pipe.
See also Fig. 5 again, it has shown in sigma-delta analog to digital conversion circuit power up and power down process how to avoid making modulator be in saturated labile state because of input signal greater than quantizing reference level.Wherein, AVDD201 is power supply electrifying and power down waveform, Vrefp202 be just quantizing reference level (with respect to the syntype bias signal) power on and the power down process in waveform, Vrefn203 be negative quantity reference level (with respect to the syntype bias signal) power on and the power down process in waveform, Vcom204 be the common-mode reference level power on and the power down process in waveform, reset_n_por205 is the signal output waveform that por circuit 113 produces, por circuit 113 is used to detect supply voltage and powers on and the power down process, promptly after por circuit 113 detects power supply and is stabilized in the suitable scope, it can postpone to make reset_n_por become high level after the regular time (being Tdelay), the length of this set time must can make Vrefp, Vrefn and Vcom are established to the desired accuracy rating of ADC, also want simultaneously to guarantee that digital circuit can correctly start.The general time that all can add delay unit by system's decision of reset_n_por signal delay.When por circuit 113 detects supply voltage and powers on, the reset_n_por signal of its output can make controlled switch 127,128,129,130 closures that are connected each integrator input and output, the input and output short circuit of each integrator thus, thereby the voltage of each integrator is common mode electrical level, and promptly each integrator is in reset mode.And powered on stablely when por circuit 113 detects power supply, and after Vrefp, Vrefn and integrator had all been set up, por circuit 113 control controlled switchs 127,128,129,130 disconnected, and modulator returns to normal operating conditions thus, i.e. the integrating function state.Modulator just saturated labile state can not occur in power up like this.And when por circuit 113 detected power supply and power down occurs, it also can allow modulator be in reset mode.Promptly detect AVDD and be lower than a preset threshold value when por circuit 113, the output of por circuit 113 will step-down, thereby each integrator is resetted.This method has well solved the instability problem of power supply electrifying and power down process sigma-delta ADC.
See also Fig. 6 again, it is a simple low-power consumption por circuit schematic diagram.Because of por circuit is in running order always, so require low-power consumption, general electric current all is less than 1uA.The PMOS pipe M5 and the electric resistance partial pressure on the left side constitute biasing and sample circuit, the quiescent dissipation of por circuit is introduced by biasing circuit and current mirror thereafter, and for keeping low-power consumption, all-in resistance is controlled at about 5M Ω, make branch current greatly about 300nA, the threshold value of AVDD sampled point Vd is at the threshold voltage V of M1
Thn_M1(being about 0.7) located.All insert Schmidt (schmitt) trigger between AB and CD to strengthen antijamming capability.Power on the stage, rise from 0V with power supply, when being in low voltage, the M1 grid voltage is lower, and (Vd＜0.7V) is in cut-off state, M5 and M6 conducting, the A point voltage rises with AVDD, and when AVDD was not enough to reach the state that makes schmitt trigger operate as normal, the B point can not provide normal inversion signal, during near 1V, the schmitt trigger can operate as normal, and B changes 0 into, and this moment, each inverter all can operate as normal.The C point voltage also is 0, and the E point voltage is 0.Then AVDD continues to rise, when its partial pressure value exceeds V
Thn_M1The time, the M1 conducting, A point voltage=0, B point voltage=1 (being exactly AVDD), high level is delivered to the E point needs the certain time-delay of experience.The very big mos capacitance that C point M3 constitutes, and it drives the inverter employing than pipe, the needed time-delay of generation system.Through the time-delay of certain hour, E is a high level, and then M2 ends, and Vd can increase to the resistance between the AVSS, so the raising of power supply sampling voltage ratio, then needs the lower M1 that just can cause to end when power supply AVDD falls, and this has just strengthened the antijamming capability of por circuit.In the power down stage, power supply begins to descend from AVDD, as long as M1 does not end, the high level of exit point E just can not change.When AVDD decline caused M1 to end, the A point voltage was followed the AVDD change and is high level, and the B point is 0 so, and after certain delay, the E point also is 0, and system resets.After this M2 conducting, power supply sampling voltage ratio reduces, and this moment, power supply can not make E point current potential change as a spot of rising interference level occurring yet, had suppressed the interference on the supply voltage.
Need to prove that the foregoing description is only as a specific embodiment of the present invention, but not be used to limit the present invention, any other sigma-delta analog to digital conversion circuit all can adopt Method and circuits of the present invention to control.For example, for other low orders or high-order sigma-delta analog to digital conversion circuit, particularly for the sigma-delta ADC of types such as stable low order (exponent number≤2) itself and mash2-1,, all can adopt above-mentioned described method and circuit to make sigma-delta ADC working stability.Equally, the electrify restoration circuit of employing is not to exceed with shown in Figure 6 yet, and but, the electrify restoration circuit that has disposed with the SOC (system on a chip) at direct employing sigma-delta analog to digital conversion circuit place itself is good.
Need to prove why SOC (system on a chip) needs to dispose electrify restoration circuit, this be because: along with the raising of chip integration, comprised increasing sophisticated functions module on the single chip.The some of them module must power on or be in certain known initial state when energy-saving mode be recovered, thereby guarantees executable operations correctly.Therefore need to adopt electrification reset (Power On Reset) signal can correctly start in power up so that guarantee those circuit to resetting such as element circuits such as the oscillator in memory devices such as trigger, latch and register, counter, the analog circuit, comparators.
Specifically can be referring to Fig. 7, it is the basic framework schematic diagram of system on a slice.As shown in the figure, described SOC (system on a chip) comprises function element 1 and function element 2, wherein, function element 1 and function element 2 can be oscillator in trigger, latch, register, counter, the analog circuit or comparator etc., because function element 1 and function element 2 need power-on reset signal to reset, therefore, described SOC (system on a chip) need be function element 1 and function element 2 configurations one electrify restoration circuit.(for example also comprise above-mentioned described sigma-delta analog to digital conversion circuit and work as described SOC (system on a chip), the sigma-delta analog to digital conversion circuit that comprises n integrator) time, so just can directly adopt this electrify restoration circuit to come control connection (is controlled device 1,2 in each controlled device of this each integrator of sigma-delta analog to digital conversion circuit ... n).
Certainly, the structure of SOC (system on a chip) is not to exceed with the foregoing description, for example, can comprise other digital circuit or analog circuit etc., exemplifies no longer one by one at this.
In sum, the unsettled Method and circuits of solution sigma-delta analog to digital conversion circuit power up of the present invention detects the generation of power supply electrifying or power down situation by electrify restoration circuit, and the corresponding reset enable signal that provides is connected controlled switch closure between each integrator input and output side, avoids the integrator job insecurity that causes because of power supply electrifying or power down.With respect to having now by detection for integrator output signal or output state, this law does not need to set up testing circuit again, but the electrify restoration circuit that can directly utilize SOC (system on a chip) originally to dispose, thus, can simplify the circuit structure of SOC (system on a chip), reduce the complexity of its circuit.And this law is directly power supply to be detected, and therefore, when power supply power-fail, also can realize resetting of integrator, has improved the stability of sigma-delta analog to digital conversion circuit greatly.
The foregoing description just lists expressivity principle of the present invention and effect is described, but not is used to limit the present invention.Any personnel that are familiar with this technology all can make amendment to the foregoing description under spirit of the present invention and scope.Therefore, the scope of the present invention should be listed as claims.
Claims (19)
1. one kind solves the unsettled circuit of sigma-delta analog to digital conversion circuit power up, it is characterized in that comprising:
At least one controlled device is connected with an integrator of sigma-delta analog to digital conversion circuit to be controlled separately; Power sense circuit, be connected with each controlled device, be used to detect the power supply situation of the power supply that offers described sigma-delta analog to digital conversion circuit to be controlled, and when detecting power supply instability, provide first control signal to each controlled device, each integrator is resetted, and after the detection power supply is stable, provide second control signal to each controlled device, make each integrator enter the integration operating state, thereby make the working stability of described sigma-delta analog to digital conversion circuit to be controlled.
2. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 1, it is characterized in that: described power sense circuit is an electrify restoration circuit.
3. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 2 is characterized in that: described electrify restoration circuit is the configuration that the SOC (system on a chip) self at described sigma-delta analog to digital conversion circuit place to be controlled has had.
4. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 1, it is characterized in that: controlled device comprises the controlled switch that is connected between integrator input and the output.
5. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 4, it is characterized in that: described controlled switch is: relay, regular tap or metal-oxide-semiconductor.
6. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 1, it is characterized in that: described sigma-delta analog to digital conversion circuit to be controlled is: a kind of in the low order sigma-delta analog to digital conversion circuit of exponent number≤2, cascade 2-1sigma-delta analog to digital conversion circuit and the cascade 2-2sigma-delta analog to digital conversion circuit.
7. the unsettled circuit of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 6, it is characterized in that: described 2-2sigma-delta analog to digital conversion circuit comprises: first order second order sigma-delta modulator, summing circuit, second level second order sigma-delta modulator, and described first order second order sigma-delta modulator and second level second order sigma-delta modulator output signal are carried out the noise cancellation logical block of noise cancellation, wherein, described first order second order sigma-delta modulator and second level second order sigma-delta modulator all comprise separately: by first single order integrating circuit, second single order integrating circuit, form series circuit with the quantizer serial connection, and the output of quantizer carried out feeding back to after the digital-to-analogue conversion digital to analog converter of first single order integrating circuit, described summing circuit will be sent into described second level second order sigma-delta modulator input after will suing for peace through the output of second integrating circuit in the first order second order sigma-delta modulator of convergent-divergent with through the output of quantizer in the first order second order sigma-delta modulator of convergent-divergent.
8. one kind solves the unsettled method of sigma-delta analog to digital conversion circuit power up, it is characterized in that comprising step:
When a power sense circuit detects the power supply that offers sigma-delta analog to digital conversion circuit to be controlled and is in the power supply instability state, described power sense circuit sends first control signal to each controlled device of each modulator that is connected described sigma-delta analog to digital conversion circuit to be controlled, so that each integrator resets;
When described power sense circuit detect the power supply power supply that offers sigma-delta analog to digital conversion circuit to be controlled stable after, described power sense circuit sends second control signal to each controlled device, so that each integrator is in the integration operating state, realize the working stability of described sigma-delta analog to digital conversion circuit to be controlled thus.
9. the unsettled method of solution sigma-delta number conversion circuit power up as claimed in claim 8, it is characterized in that: when described power sense circuit detects the labile state that the power on labile state that causes or power down cause, send first control signal.
10. solve the unsettled method of sigma-delta analog to digital conversion circuit power up as claimed in claim 8 or 9, it is characterized in that: described power sense circuit is an electrify restoration circuit.
11. the unsettled method of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 10 is characterized in that: described electrify restoration circuit is the configuration that the SOC (system on a chip) self at described sigma-delta analog to digital conversion circuit place to be controlled has had.
12. the unsettled method of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 8 is characterized in that: controlled device comprises the input that is connected integrator and the controlled switch between the output.
13. the unsettled method of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 12, it is characterized in that: controlled switch is metal-oxide-semiconductor, relay or regular tap.
14. the unsettled method of solution sigma-delta number conversion circuit power up as claimed in claim 8, it is characterized in that: described sigma-delta analog to digital conversion circuit to be controlled is: a kind of in the low order sigma-delta analog to digital conversion circuit of exponent number≤2, cascade 2-1sigma-delta analog to digital conversion circuit and the cascade 2-2sigma-delta analog to digital conversion circuit.
15. the unsettled method of solution sigma-delta analog to digital conversion circuit power up as claimed in claim 14, it is characterized in that: described 2-2sigma-delta analog to digital conversion circuit comprises: first order second order sigma-delta modulator, summing circuit, second level second order sigma-delta modulator, and described first order second order sigma-delta modulator and second level second order sigma-delta modulator output signal are carried out the noise cancellation logical block of noise cancellation, wherein, described first order second order sigma-delta modulator and second level second order sigma-delta modulator all comprise separately: by first single order integrating circuit, second single order integrating circuit, form series circuit with the quantizer serial connection, and the output of quantizer carried out feeding back to after the digital-to-analogue conversion digital to analog converter of first single order integrating circuit, described summing circuit will be sent into described second level second order sigma-delta modulator input after will suing for peace through the output of second integrating circuit in the first order second order sigma-delta modulator of convergent-divergent with through the output of quantizer in the first order second order sigma-delta modulator of convergent-divergent.
16. a SOC (system on a chip) is characterized in that comprising at least:
The sigma-delta analog to digital conversion circuit;
Be connected each controlled device of described each integrator of sigma-delta analog to digital conversion circuit;
At least one function element;
Electrify restoration circuit, be used to detect the power supply situation of the power supply of access, and when detecting power supply instability, provide first control signal to each controlled device and described at least one function element, each integrator and at least one function element are resetted, and after the detection power supply is stable, provide second control signal to each controlled device and at least one function element, make each integrator enter the integration operating state, make at least one function element enter normal operating conditions simultaneously.
17. SOC (system on a chip) as claimed in claim 16 is characterized in that: described function element comprises oscillator in trigger, latch, register, counter, the analog circuit, and comparator.
18. SOC (system on a chip) as claimed in claim 16 is characterized in that: controlled device is to be connected the input of integrator and the controlled switch between the output.
19. SOC (system on a chip) as claimed in claim 16 is characterized in that: described sigma-delta analog to digital conversion circuit is: a kind of in the low order sigma-delta analog to digital conversion circuit of exponent number≤2, cascade 2-1sigma-delta analog to digital conversion circuit and the cascade 2-2sigma-delta analog to digital conversion circuit.
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| CN201010558288.6A CN102035550B (en) | 2010-11-23 | 2010-11-23 | Circuit and method for solving instable power-on process of sigma-delta analog-to-digital conversion circuit |
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| CN103021357A (en) * | 2012-12-05 | 2013-04-03 | 江苏清投视讯科技有限公司 | Grouping power supply control device of liquid crystal display (LCD) spliced large screen |
| CN105007080A (en) * | 2015-07-01 | 2015-10-28 | 宁波大学 | Method for realizing sampling value stabilization in analog-digital conversion |
| CN110007132A (en) * | 2019-05-08 | 2019-07-12 | 南京芯耐特半导体有限公司 | A kind of low pressure zero-power CMOS power on detection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105007080B (en) * | 2015-07-01 | 2017-10-31 | 宁波大学 | A kind of method that sampling value stabilization is realized in analog-to-digital conversion |
| CN110007132A (en) * | 2019-05-08 | 2019-07-12 | 南京芯耐特半导体有限公司 | A kind of low pressure zero-power CMOS power on detection circuit |
| CN110007132B (en) * | 2019-05-08 | 2024-03-15 | 南京芯耐特半导体有限公司 | Low-voltage zero-power consumption CMOS power-on detection circuit |
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Effective date of registration: 20201229 Address after: 201306 building C, No. 888, Huanhu West 2nd Road, Lingang New District, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Juquan Microelectronics (Shanghai) Co., Ltd Address before: 201203, room 8, building 200, 601 Newton Road, Zhangjiang hi tech park, Shanghai, Pudong New Area Patentee before: Hi-Trend Technology (Shanghai) Co.,Ltd. |