CN102034830A - Memory with disabling circuit and method for disabling memory - Google Patents

Memory with disabling circuit and method for disabling memory Download PDF

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CN102034830A
CN102034830A CN201010539237.9A CN201010539237A CN102034830A CN 102034830 A CN102034830 A CN 102034830A CN 201010539237 A CN201010539237 A CN 201010539237A CN 102034830 A CN102034830 A CN 102034830A
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output
terminal
memory
state
logic
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CN102034830B (en
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王释兴
袁德铭
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Etron Technology Inc
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Etron Technology Inc
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Abstract

The invention discloses a memory with a disabling circuit, which comprises a memory array and a disabling circuit. The memory array comprises a data output end and an output enabling end. The disabling circuit is coupled to the data output terminal and the output enabling terminal. The disabling circuit comprises a fuse wire and an output end, when the fuse wire is not blown, the disabling circuit determines the logic state of the output end according to the logic states of the output enabling end and the data output end, and when the fuse wire is blown, the disabling circuit enables the output end to be in a high impedance state. Thus, external circuitry cannot read or write to the memory array. The invention also discloses a method for disabling the memory.

Description

Have the memory of anergy circuit and make the method for memory anergy
Technical field
The present invention relates to a kind of memory, more particularly,, can make this memory anergy during for defective products in this memory relevant for a kind of memory with anergy circuit.
Background technology
Along with the development of integrated circuit processing technique and the lifting of component density, order is previous to be applied on the wafer (wafer) of memory and can to have produced a plurality of crystal grain (die) that include millions of electronic components simultaneously.Usually in the manufacturing process of these crystal grain, can carry out a wafer process earlier, to the segment chip on the wafer or all chip deposit simultaneously, technologies such as photoetching or etching.After wafer manufacturing is finished, carry out again as last part technologies such as cutting and encapsulation.
Generally speaking, the wafer that completes needs each crystal grain on the wafer to be carried out the test of every electrical functionality, the integrality when guaranteeing that it dispatches from the factory simultaneously with the crystal grain that judges whether damage on the function preceding through encapsulation (package).The wafer pin is surveyed (Circuit Probe, CP) distinguishable go out on the wafer each crystal grain whether be product or bad product (Not-Good, NG), for instance, when crystal grain when the back finds that performance is not inconsistent situation such as specification or capability error after tested, this crystal grain promptly classifies as bad product.
Since general wafer manufactory with encapsulate factory be different vendor or even in different regions, country, so wafer manufactory can't proceed last part technology usually, but gives the encapsulation factory in downstream.Corresponding wafer figure (wafer map) can enclose in the lump in chip manufacturing factory when the wafer shipment being given encapsulation factory, so that encapsulation factory the crystal grain distributing position and the related data of product and bad product well to be provided.Encapsulation factory just can omit the step with the encapsulation of crystal grain bad product according to this.But encapsulation factory still probably encapsulates the crystal grain bad product in encapsulation process by mistake in the lump.Though packaging and testing (Final Test, standard FT) is surveyed strict than the wafer pin, and the crystal grain bad product after the encapsulation still has the risk by packaging and testing.Moreover; since the crystal grain bad product when carrying out packaging and testing through canned program become memory integrated circuit (Integrated Circuit, IC), therefore even if packaging and testing successfully filter out the crystal grain bad product; still can be to rate of finished products, testing efficiency and technology/testing cost cause appreciable impact.
Summary of the invention
Therefore, a purpose of the present invention is to provide a kind of memory with anergy circuit.
The invention provides a kind of memory.This memory comprises a memory array and an anergy circuit.This memory array comprises a data output end and an output enable end.This anergy circuit is coupled to this data output end and this output enable end.This anergy circuit comprises a fuse and an output, when this fuse is not blown, this anergy circuit determines the logic state of this output according to the logic state of this output enable end and this data output end, when this fuse was blown, it was a high impedance status that this anergy circuit makes this output.
The present invention provides a kind of method that makes the memory anergy in addition.This method comprises provides an anergy circuit with a fuse to be arranged at the output of a memory; And blow this fuse so that this anergy circuit produces a high impedance status in the output of this memory.
When memory array was classified bad product as, the anergy circuit can be exported the signal of a logic of propositions accordingly to allow the output of this anergy circuit present high impedance (or other default state).Therefore, by can't picking out this memory array easily and classify bad product as, reach and reduce encapsulation error, promote yield and reduce purposes such as testing time and cost actions such as this memory array read or writes.
Description of drawings
Following appended accompanying drawing is the part of specification of the present invention, has illustrated example embodiment of the present invention, and appended accompanying drawing illustrates principle of the present invention with the description of specification.
Fig. 1 is the schematic diagram of explanation memory of the present invention;
Fig. 2 is the schematic diagram of an embodiment of explanation anergy circuit of the present invention;
Fig. 3 is the explanation flow chart that makes the method for memory anergy of the present invention.
Wherein, Reference numeral
10 memories, 11 memory arrays
12 anergy circuit OUT outputs
211 fuse circuits, 212 output control circuits
220 output buffer R resistance
F fuse V voltage source
GND ground end IO data output end
OE output enable end 2,121 first inverters
2,122 first NAND gate, 2,123 second inverters
2,124 second NAND gate, 2125 NOR gate
231 first switches, 232 second switches
40 methods, 41～46 steps
Embodiment
In view of this, the present invention utilizes an anergy circuit to control the output of a memory.As long as when a memory cell of this memory was measured to bad product in arbitrary stage in technology, it was high impedance (tri-state) state that the anergy circuit can make the output of this memory, just makes this memory anergy.Therefore, in the follow-up test step, can distinguish directly according to this that this memory is a bad product.
Please refer to Fig. 1.Fig. 1 is the schematic diagram of explanation memory 10 of the present invention.Memory 10 comprises memory array 11, anergy circuit 12 and output OUT.Anergy circuit 12 is coupled to the data output end IO and output enable (Output Enable) the end OE of memory array 11.Memory array comprises a plurality of memory cells, by anergy circuit 12 stored transfer of data is arrived output OUT.The output OUT of anergy circuit 12 writable control storages 10 makes it be rendered as high impedance status.When output OUT is high impedance status, external circuit such as tester table or other device and the action that can't write or read memory 10, therefore, memory 10 can be considered anergy.
Please refer to Fig. 2.Fig. 2 is the schematic diagram of an embodiment of explanation anergy circuit 12 of the present invention.Anergy circuit 12 comprises fuse circuit 211, output control circuit 212 and output buffer 220.Fuse circuit 211 comprises resistance R and fuse F.First end of resistance R couples a voltage source V, and second end of resistance R is coupled to the output of fuse circuit 211.First end of fuse F is coupled to second end of resistance R, and second end of fuse F is coupled to a ground end GND.The fuse F of fuse circuit 211 changes according to the state of memory array 11.For instance, when memory array 11 was measured to bad product, fuse F blew.Whether fuse circuit 211 blows according to fuse F is exported a logic state.More particularly, when fuse F did not blow, the current potential of fuse circuit 211 was held the electronegative potential of GND with being pulled to, the signal of fuse circuit 211 output logics " 0 "; When fuse F blew, the current potential of fuse circuit 211 was pulled to a high potential of voltage source V, the signal of fuse circuit 211 output logics " 1 ".In addition, fuse F can be the user and controls.For example in the present embodiment, when memory array 11 was bad product, fuse F blew.Yet the user can set the pre-conditioned of blown fuse F, is not limited only to when memory array 11 is bad product.
Output control circuit 212 is coupled to the data output end IO and the output enable end OE of memory array 11.Output control circuit 212 is exported a logic state according to the data output end IO of memory array 11 and the signal on the output enable end OE.Output control circuit 212 comprises first inverter 2121, first NAND gate 2122, second inverter 2123, second NAND gate 2124 and NOR gate 2125.First inverter 2121 is coupled to the output of fuse circuit 211, is used for signal inversion that fuse circuit 211 is exported.First end of first NAND gate 2122 is coupled to output enable end OE, and second end of first NAND gate 2122 is coupled to the output of first inverter 2121.First NAND gate 2122 is used for the signal that output enable end OE and first inverter 2121 are exported is carried out NAND operation.Second inverter 2123 is coupled to the output of first NAND gate 2122, is used for signal inversion that first NAND gate 2122 is exported.First end of second NAND gate 2124 is coupled to the data output end IO of memory array 11, and second end of second NAND gate 2124 is coupled to the output of second inverter 2123.Second is used for the signal that the data output end IO and second inverter 2123 of memory array 11 are exported is carried out NAND operation with non-device 2124.First end of NOR gate 2125 is coupled to the output of first NAND gate 2122, and second end of NOR gate 2125 is coupled to the data output end IO of first NAND gate 2122.NOR gate 2125 is used for the signal that data output end IO with first NAND gate 2122 and memory array 11 exported and carries out NOR-operation.
Output buffer 220 is coupled between the output OUT of output control circuit 212 and memory 10, is used for according to this output control circuit 212 data that output storage array 11 is stored.Output buffer 220 comprises first switch 231 and second switch 232.First end of first switch 231 is coupled to voltage source V, and second end of first switch 231 is coupled to the output OUT of memory 10, and the control end of first switch 231 is coupled to the output of second NAND gate 2124.First end of second switch 232 is coupled to the output OUT of memory 10, and second end of second switch 232 is held GND with being coupled to, and the control end of second switch 232 is coupled to the output of NOR gate 2125.In the present embodiment, first switch 231 is a P-type mos (P-type Metal-Oxide Semiconductor, PMOS) transistor, and second switch is a N type metal oxide semiconductor (N-type Metal-Oxide Semiconductor, NMOS) transistor.
When fuse F blows, the signal of fuse circuit 211 outputs one logical one.First inverter 2121 is a logical zero with the signal inversion of the logical one that fuse circuit 211 is exported.The signal that the first NAND gate 2122 pairs of output enable ends OE and first inverter 2121 are exported carries out NAND operation; Because the signal exported of fuse circuit 211 is a logical zero, no matter therefore the signal exported of output enable end OE is logical zero or logical one, the signal of first NAND gate, 2122 output logics " 1 ".Second inverter 2123 is a logical zero with the signal inversion of the logical one that first NAND gate 2122 is exported.The signal that the data output end IO of 2124 pairs of memory arrays 11 of second NAND gate and second inverter 2123 are exported carries out NAND operation; Because the signal exported of second inverter 2123 is a logical zero, no matter therefore the signal exported of data output end IO is logical zero or logical one, the signal of second NAND gate, 2124 output logics " 1 ".NOR gate 2125 is carried out NOR-operation with the signal that the data output end IO of first NAND gate 2122 and memory array 11 is exported; Because the signal exported of first NAND gate 2122 is a logical one, no matter therefore the signal exported of data output end IO is logical zero or logical one, the signal of NOR gate 2125 output logics " 0 ".At last, because the signal of second NAND gate 2124 and NOR gate 2125 difference output logics " 1 " and logical zero, first switch 231 (PMOS transistor) and second switch 232 (nmos pass transistor) are closed all accordingly, and the output OUT of memory 10 is a high impedance status.
It is noted that anergy circuit 12 is not limited in Fig. 2 the disclosed embodiments of the present invention, can also be that other Different Logic arrangements of components forms.Pre-conditioned (for example when memory array is classified bad product as) down the user, everyly can make its internal logic circuit export a logic of propositions state to allow the output of this anergy circuit present a particular state (for example high impedance), can't be to make external circuit accordingly to the anergy circuit spirit all according to the invention of actions such as this memory array reads or writes.
Please also refer to Fig. 2 and table 1.Table 1 is the form of the signal relation of memory array 11 and anergy circuit 12 in the key diagram 2.Under normal operation, whether output enable end OE control storage array 11 action such as can read or write.If output enable end OE is when opening (that is signal of output enable end OE output logic " 1 "), the data of the data output end IO of anergy circuit 12 output storage arrays 11.That is to say that when the signal of the data output end IO of memory array 11 output logic " 0 " or " 1 ", the output of anergy circuit 12 is the signal of output logic " 0 " or " 1 " accordingly also.Otherwise if output enable end OE is when closing (that is signal of output enable end OE output logic " 0 "), the output of anergy circuit 12 presents high impedance, that is memory array 11 and action such as can't read or write.But when fuse F blew (that is memory array 11 is bad product), no matter output enable end OE is for opening or closing, anergy circuit 12 all presented high impedance, and can't read or write.
Fuse OE? IO? OUT?
Do not blow 0? -? High impedance
Do not blow 1? 0? 0?
Do not blow 1? 1? 1?
Blow ?-? ?-? High impedance
Table 1
Please also refer to Fig. 2 and Fig. 3.Fig. 3 is the explanation flow chart that makes the method 40 of memory anergy of the present invention.Step is described as follows:
Step 41: beginning;
Step 42: the fuse opening of fuse circuit 211;
Step 43: the signal of fuse circuit 211 outputs one logic of propositions of the output control circuit 212 of memory array 11;
Step 44: output control circuit 212 is exported the signal of logic of propositions according to the signal of fuse circuit 211 outputs;
Step 45: according to the signal of output control circuit 212 outputs, output buffer 220 is closed, and the output of the anergy circuit 12 of memory array 11 presents high impedance, memory array 11 read functions anergies;
Step 46: finish.
In step 42, the fuse of blown fuse circuit 211 is pre-conditioned according to the user's.In the present embodiment, set pre-conditioned of user surveyed or whether the result of test phase such as packaging and testing is bad product at the wafer pin for memory 10.In addition, if memory array 11 also can be considered as bad product with it when there are misgivings on quality or the specification in any stage.
In step 43, when the fuse opening of fuse circuit 211, the signal of fuse circuit 211 outputs one logic of propositions of the output control circuit 212 of memory array 11.In the present embodiment, when memory array 11 during for product well, the signal of fuse circuit 211 output logics " 0 " (current potential of fuse circuit 211 outputs is held the electronegative potential of GND with being pulled to).When memory array 11 is bad product, the signal of fuse circuit 211 output logics " 1 " (current potential of fuse circuit 211 outputs is pulled to a high potential of voltage source V).
In step 44, the signal that output control circuit 212 is exported according to fuse circuit 211 is exported the signal of logic of propositions.In the present embodiment, signal (that is when memory array 11 is bad product) when fuse circuit 211 output logics " 1 ", no matter the data output end IO of memory array 11 and output enable end OE output is the signal of logical zero or " 1 ", second NAND gate 2124 of output control circuit 212 and NOR gate 2125 be the signal of output logic " 1 " and " 0 " respectively.
In step 45, because the signal that second NAND gate 2124 and NOR gate 2125 are exported is respectively logical one and " 0 ", first switch 231 and the second switch 232 of output buffer 220 are closed accordingly, cause the anergy circuit 12 (that is output of output buffer 220) of memory array 11 to present high impedance.When the anergy circuit 12 of memory array 11 presented high impedance, external circuit (as tester table) just can't come memory array 11 is read or writes by anergy circuit 12.
In sum, in the present invention, when memory array was classified bad product as, the anergy circuit can be exported the signal of a logic of propositions accordingly to allow the output of this anergy circuit present high impedance (or other default state).Therefore, by can't picking out this memory array easily and classify bad product as, reach and reduce encapsulation error, promote yield and reduce purposes such as testing time and cost actions such as this memory array read or writes.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.

Claims (10)

1.一种存储器，其特征在于，包含：1. A memory, characterized in that it comprises: 一存储器阵列，包含一数据输出端以及一输出致能端；以及A memory array, including a data output terminal and an output enabling terminal; and 一失能电路，耦接于该数据输出端与该输出致能端，该失能电路包含一熔丝以及一输出端，当该熔丝未被烧断时，该失能电路根据该输出致能端以及该数据输出端的逻辑状态决定该输出端的逻辑状态，当该熔丝被烧断时，该失能电路使该输出端为一高阻抗状态。A disabling circuit, coupled between the data output end and the output enabling end, the disabling circuit includes a fuse and an output end, when the fuse is not blown, the disabling circuit causes The logic states of the enable end and the data output end determine the logic state of the output end. When the fuse is blown, the disable circuit makes the output end a high-impedance state. 2.根据权利要求1所述的存储器，其特征在于，该失能电路包含：2. The memory according to claim 1, wherein the disabling circuit comprises: 一熔丝电路，用来将该熔丝未被烧断的状态转换为一逻辑“0”状态，以及该熔丝被烧断的状态转换为一逻辑“1”状态；a fuse circuit for converting the unblown state of the fuse to a logic "0" state, and converting the blown state of the fuse to a logic "1" state; 一输出缓冲电路，用来于该输出端产生该逻辑“0”状态、该逻辑“1”状态以及该高阻抗状态；以及an output buffer circuit for generating the logic "0" state, the logic "1" state and the high impedance state at the output; and 一输出控制电路，用来控制该输出缓冲电路，当该熔丝未被烧断且该输出致能端为该逻辑“1”状态时，将该数据输出端的逻辑状态传输至该输出端，当该熔丝被烧断或该输出致能端为该逻辑“0”状态时，使该输出缓冲电路产生该高阻抗状态。An output control circuit, used to control the output buffer circuit, when the fuse is not blown and the output enable end is in the logic "1" state, transmit the logic state of the data output end to the output end, when When the fuse is blown or the output enabling terminal is in the logic "0" state, the output buffer circuit is made to generate the high impedance state. 3.根据权利要求2所述的存储器，其特征在于，该输出控制电路包含：3. The memory according to claim 2, wherein the output control circuit comprises: 一第一反相器，耦接于该熔丝电路，用来将该熔丝电路所输出的一信号反相；a first inverter, coupled to the fuse circuit, for inverting a signal output by the fuse circuit; 一第一与非门，用来对该输出致能端及该第一反相器所输出的信号进行与非运算，包含：一第一端，耦接于该输出致能端；以及一第二端，耦接于该第一反相器的一输出端；A first NAND gate, used for performing NAND operation on the output enabling terminal and the signal output by the first inverter, comprising: a first terminal coupled to the output enabling terminal; and a first two terminals, coupled to an output terminal of the first inverter; 一第二反相器，耦接于该第一与非门的一输出端，用来将该第一与非门器所输出的信号反相；a second inverter, coupled to an output end of the first NAND gate, for inverting the signal output by the first NAND gate; 一第二与非门，用来对该存储器阵列的该输出端及该第二反相器所输出的信号进行与非运算，包含：一第一端，耦接于该第一存储器阵列的该输出端；一第二端，耦接于该第二反相器的一输出端；以及一输出端；以及A second NAND gate, used for performing NAND operations on the output terminal of the memory array and the signal output by the second inverter, including: a first terminal coupled to the first terminal of the first memory array an output terminal; a second terminal coupled to an output terminal of the second inverter; and an output terminal; and 一或非门，用来将该第一与非门及该存储器阵列的该输出端所输出的信号进行或非运算，包含：一第一端，耦接于该第一与非门的该输出端；一第二端，耦接于该存储器阵列的该输出端；以及一输出端。A NOR gate, used to perform NOR operations on the signals output by the first NAND gate and the output terminal of the memory array, including: a first terminal coupled to the output of the first NAND gate terminal; a second terminal coupled to the output terminal of the memory array; and an output terminal. 4.根据权利要求3所述的存储器，其特征在于，该输出缓冲电路包含：4. The memory according to claim 3, wherein the output buffer circuit comprises: 一第一开关，包含：一第一端，耦接于一电压源；一第二端，耦接于该存储器的该输出端；以及一控制端，耦接于第二与非门的该输出端；以及A first switch, comprising: a first terminal coupled to a voltage source; a second terminal coupled to the output terminal of the memory; and a control terminal coupled to the output of the second NAND gate terminal; and 一第二开关，包含：一第一端，耦接于该存储器的该输出端；一第二端，耦接于一地端；以及一控制端，耦接于该或非门的该输出端。A second switch, comprising: a first terminal coupled to the output terminal of the memory; a second terminal coupled to a ground terminal; and a control terminal coupled to the output terminal of the NOR gate . 5.根据权利要求4所述的存储器，其特征在于，该第一开关为一P型金属氧化物半导体晶体管。5. The memory according to claim 4, wherein the first switch is a P-type metal oxide semiconductor transistor. 6.根据权利要求4所述的存储器，其特征在于，该第二开关为一N型金属氧化物半导体晶体管。6. The memory according to claim 4, wherein the second switch is an N-type metal oxide semiconductor transistor. 7.一种使存储器失能的方法，其特征在于，包含：7. A method for disabling memory, comprising: 提供一具有一熔丝的一失能电路设置于一存储器的输出端；以及providing a disabling circuit with a fuse disposed at an output of a memory; and 烧断该熔丝以使该失能电路于该存储器的输出端产生一高阻抗状态。Blowing the fuse causes the disabling circuit to generate a high impedance state at the output of the memory. 8.根据权利要求7所述的方法，其特征在于，另包含：8. The method according to claim 7, further comprising: 利用该存储器的一数据输出端以及一输出致能端读取该存储器所储存的数据；以及using a data output end and an output enable end of the memory to read data stored in the memory; and 当该熔丝未被烧断时，该失能电路根据该输出致能端以及该数据输出端的逻辑状态决定该存储器的输出端的逻辑状态。When the fuse is not blown, the disable circuit determines the logic state of the output terminal of the memory according to the logic states of the output enabling terminal and the data output terminal. 9.根据权利要求8所述的方法，其特征在于，当该熔丝未被烧断时，该失能电路根据该输出致能端以及该数据输出端的逻辑状态决定该存储器的输出端的逻辑状态包含：9. The method according to claim 8, wherein when the fuse is not blown, the disabling circuit determines the logic state of the output terminal of the memory according to the logic states of the output enabling terminal and the data output terminal Include: 当该输出致能端为一逻辑“1”状态时，将该数据输出端的逻辑状态传输至该存储器的输出端；以及when the output enabling terminal is in a logic “1” state, transmitting the logic state of the data output terminal to the output terminal of the memory; and 当该输出致能端为一逻辑“0”状态时，使该存储器的输出端产生该高阻抗状态。When the output enabling terminal is in a logic "0" state, the output terminal of the memory is made to generate the high impedance state. 10.根据权利要求9所述的方法，其特征在于，当该输出致能端为一逻辑“1”状态时，将该数据输出端的逻辑状态传输至该存储器的输出端包含：10. The method according to claim 9, wherein when the output enabling terminal is in a logic “1” state, transmitting the logic state of the data output terminal to the output terminal of the memory comprises: 当该数据输出端为该逻辑“0”状态时，该存储器之输出端输出该逻辑“0”状态；以及When the data output terminal is in the logic "0" state, the output terminal of the memory outputs the logic "0" state; and 当该数据输出端为该逻辑“1”状态时，该存储器的输出端输出该逻辑“1”状态。When the data output end is in the logic "1" state, the output end of the memory outputs the logic "1" state.
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CN112071833A (en) * 2019-11-05 2020-12-11 友达光电股份有限公司 Chip and method for manufacturing the same

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