CN102034830A - Memorizer with disabling circuit and method for disabling memorizer - Google Patents
Memorizer with disabling circuit and method for disabling memorizer Download PDFInfo
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- CN102034830A CN102034830A CN201010539237.9A CN201010539237A CN102034830A CN 102034830 A CN102034830 A CN 102034830A CN 201010539237 A CN201010539237 A CN 201010539237A CN 102034830 A CN102034830 A CN 102034830A
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000015654 memory Effects 0.000 claims description 100
- 206010011968 Decreased immune responsiveness Diseases 0.000 claims description 54
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 description 13
- 238000005538 encapsulation Methods 0.000 description 12
- 238000012360 testing method Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 238000003860 storage Methods 0.000 description 4
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- 230000001143 conditioned effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
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- 238000005520 cutting process Methods 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
- 238000013100 final test Methods 0.000 description 1
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Abstract
The invention discloses a memorizer with a disabling circuit, which comprises a memorizer array and a disabling circuit. The memorizer array comprises a data output end and an output enabling end. The disabling circuit is coupled to the data output end and the output enabling end. The disabling circuit comprises a fuse and an output end, wherein the disabling circuit determines the logic state of the output end according to the logic states of the output enabling end and the data output end when the fuse is not brunt out, and the disabling circuit leads the output end to be under a high-impedance state when the fuse is brunt out. Therefore, an external circuit can not read or write the memorizer array. Meanwhile, the invention further discloses a method for disabling the memorizer.
Description
Technical field
The present invention relates to a kind of memory, more particularly,, can make this memory anergy during for defective products in this memory relevant for a kind of memory with anergy circuit.
Background technology
Along with the development of integrated circuit processing technique and the lifting of component density, order is previous to be applied on the wafer (wafer) of memory and can to have produced a plurality of crystal grain (die) that include millions of electronic components simultaneously.Usually in the manufacturing process of these crystal grain, can carry out a wafer process earlier, to the segment chip on the wafer or all chip deposit simultaneously, technologies such as photoetching or etching.After wafer manufacturing is finished, carry out again as last part technologies such as cutting and encapsulation.
Generally speaking, the wafer that completes needs each crystal grain on the wafer to be carried out the test of every electrical functionality, the integrality when guaranteeing that it dispatches from the factory simultaneously with the crystal grain that judges whether damage on the function preceding through encapsulation (package).The wafer pin is surveyed (Circuit Probe, CP) distinguishable go out on the wafer each crystal grain whether be product or bad product (Not-Good, NG), for instance, when crystal grain when the back finds that performance is not inconsistent situation such as specification or capability error after tested, this crystal grain promptly classifies as bad product.
Since general wafer manufactory with encapsulate factory be different vendor or even in different regions, country, so wafer manufactory can't proceed last part technology usually, but gives the encapsulation factory in downstream.Corresponding wafer figure (wafer map) can enclose in the lump in chip manufacturing factory when the wafer shipment being given encapsulation factory, so that encapsulation factory the crystal grain distributing position and the related data of product and bad product well to be provided.Encapsulation factory just can omit the step with the encapsulation of crystal grain bad product according to this.But encapsulation factory still probably encapsulates the crystal grain bad product in encapsulation process by mistake in the lump.Though packaging and testing (Final Test, standard FT) is surveyed strict than the wafer pin, and the crystal grain bad product after the encapsulation still has the risk by packaging and testing.Moreover; since the crystal grain bad product when carrying out packaging and testing through canned program become memory integrated circuit (Integrated Circuit, IC), therefore even if packaging and testing successfully filter out the crystal grain bad product; still can be to rate of finished products, testing efficiency and technology/testing cost cause appreciable impact.
Summary of the invention
Therefore, a purpose of the present invention is to provide a kind of memory with anergy circuit.
The invention provides a kind of memory.This memory comprises a memory array and an anergy circuit.This memory array comprises a data output end and an output enable end.This anergy circuit is coupled to this data output end and this output enable end.This anergy circuit comprises a fuse and an output, when this fuse is not blown, this anergy circuit determines the logic state of this output according to the logic state of this output enable end and this data output end, when this fuse was blown, it was a high impedance status that this anergy circuit makes this output.
The present invention provides a kind of method that makes the memory anergy in addition.This method comprises provides an anergy circuit with a fuse to be arranged at the output of a memory; And blow this fuse so that this anergy circuit produces a high impedance status in the output of this memory.
When memory array was classified bad product as, the anergy circuit can be exported the signal of a logic of propositions accordingly to allow the output of this anergy circuit present high impedance (or other default state).Therefore, by can't picking out this memory array easily and classify bad product as, reach and reduce encapsulation error, promote yield and reduce purposes such as testing time and cost actions such as this memory array read or writes.
Description of drawings
Following appended accompanying drawing is the part of specification of the present invention, has illustrated example embodiment of the present invention, and appended accompanying drawing illustrates principle of the present invention with the description of specification.
Fig. 1 is the schematic diagram of explanation memory of the present invention;
Fig. 2 is the schematic diagram of an embodiment of explanation anergy circuit of the present invention;
Fig. 3 is the explanation flow chart that makes the method for memory anergy of the present invention.
Wherein, Reference numeral
10 memories, 11 memory arrays
12 anergy circuit OUT outputs
211 fuse circuits, 212 output control circuits
220 output buffer R resistance
F fuse V voltage source
GND ground end IO data output end
OE output enable end 2,121 first inverters
2,122 first NAND gate, 2,123 second inverters
2,124 second NAND gate, 2125 NOR gate
231 first switches, 232 second switches
40 methods, 41～46 steps
Embodiment
In view of this, the present invention utilizes an anergy circuit to control the output of a memory.As long as when a memory cell of this memory was measured to bad product in arbitrary stage in technology, it was high impedance (tri-state) state that the anergy circuit can make the output of this memory, just makes this memory anergy.Therefore, in the follow-up test step, can distinguish directly according to this that this memory is a bad product.
Please refer to Fig. 1.Fig. 1 is the schematic diagram of explanation memory 10 of the present invention.Memory 10 comprises memory array 11, anergy circuit 12 and output OUT.Anergy circuit 12 is coupled to the data output end IO and output enable (Output Enable) the end OE of memory array 11.Memory array comprises a plurality of memory cells, by anergy circuit 12 stored transfer of data is arrived output OUT.The output OUT of anergy circuit 12 writable control storages 10 makes it be rendered as high impedance status.When output OUT is high impedance status, external circuit such as tester table or other device and the action that can't write or read memory 10, therefore, memory 10 can be considered anergy.
Please refer to Fig. 2.Fig. 2 is the schematic diagram of an embodiment of explanation anergy circuit 12 of the present invention.Anergy circuit 12 comprises fuse circuit 211, output control circuit 212 and output buffer 220.Fuse circuit 211 comprises resistance R and fuse F.First end of resistance R couples a voltage source V, and second end of resistance R is coupled to the output of fuse circuit 211.First end of fuse F is coupled to second end of resistance R, and second end of fuse F is coupled to a ground end GND.The fuse F of fuse circuit 211 changes according to the state of memory array 11.For instance, when memory array 11 was measured to bad product, fuse F blew.Whether fuse circuit 211 blows according to fuse F is exported a logic state.More particularly, when fuse F did not blow, the current potential of fuse circuit 211 was held the electronegative potential of GND with being pulled to, the signal of fuse circuit 211 output logics " 0 "; When fuse F blew, the current potential of fuse circuit 211 was pulled to a high potential of voltage source V, the signal of fuse circuit 211 output logics " 1 ".In addition, fuse F can be the user and controls.For example in the present embodiment, when memory array 11 was bad product, fuse F blew.Yet the user can set the pre-conditioned of blown fuse F, is not limited only to when memory array 11 is bad product.
When fuse F blows, the signal of fuse circuit 211 outputs one logical one.First inverter 2121 is a logical zero with the signal inversion of the logical one that fuse circuit 211 is exported.The signal that the first NAND gate 2122 pairs of output enable ends OE and first inverter 2121 are exported carries out NAND operation; Because the signal exported of fuse circuit 211 is a logical zero, no matter therefore the signal exported of output enable end OE is logical zero or logical one, the signal of first NAND gate, 2122 output logics " 1 ".Second inverter 2123 is a logical zero with the signal inversion of the logical one that first NAND gate 2122 is exported.The signal that the data output end IO of 2124 pairs of memory arrays 11 of second NAND gate and second inverter 2123 are exported carries out NAND operation; Because the signal exported of second inverter 2123 is a logical zero, no matter therefore the signal exported of data output end IO is logical zero or logical one, the signal of second NAND gate, 2124 output logics " 1 ".NOR gate 2125 is carried out NOR-operation with the signal that the data output end IO of first NAND gate 2122 and memory array 11 is exported; Because the signal exported of first NAND gate 2122 is a logical one, no matter therefore the signal exported of data output end IO is logical zero or logical one, the signal of NOR gate 2125 output logics " 0 ".At last, because the signal of second NAND gate 2124 and NOR gate 2125 difference output logics " 1 " and logical zero, first switch 231 (PMOS transistor) and second switch 232 (nmos pass transistor) are closed all accordingly, and the output OUT of memory 10 is a high impedance status.
It is noted that anergy circuit 12 is not limited in Fig. 2 the disclosed embodiments of the present invention, can also be that other Different Logic arrangements of components forms.Pre-conditioned (for example when memory array is classified bad product as) down the user, everyly can make its internal logic circuit export a logic of propositions state to allow the output of this anergy circuit present a particular state (for example high impedance), can't be to make external circuit accordingly to the anergy circuit spirit all according to the invention of actions such as this memory array reads or writes.
Please also refer to Fig. 2 and table 1.Table 1 is the form of the signal relation of memory array 11 and anergy circuit 12 in the key diagram 2.Under normal operation, whether output enable end OE control storage array 11 action such as can read or write.If output enable end OE is when opening (that is signal of output enable end OE output logic " 1 "), the data of the data output end IO of anergy circuit 12 output storage arrays 11.That is to say that when the signal of the data output end IO of memory array 11 output logic " 0 " or " 1 ", the output of anergy circuit 12 is the signal of output logic " 0 " or " 1 " accordingly also.Otherwise if output enable end OE is when closing (that is signal of output enable end OE output logic " 0 "), the output of anergy circuit 12 presents high impedance, that is memory array 11 and action such as can't read or write.But when fuse F blew (that is memory array 11 is bad product), no matter output enable end OE is for opening or closing, anergy circuit 12 all presented high impedance, and can't read or write.
| Fuse | OE? | IO? | OUT? |
| Do not blow | 0? | -? | High impedance |
| Do not blow | 1? | 0? | 0? |
| Do not blow | 1? | 1? | 1? |
| Blow | ?-? | ?-? | High impedance |
Table 1
Please also refer to Fig. 2 and Fig. 3.Fig. 3 is the explanation flow chart that makes the method 40 of memory anergy of the present invention.Step is described as follows:
Step 41: beginning;
Step 42: the fuse opening of fuse circuit 211;
Step 43: the signal of fuse circuit 211 outputs one logic of propositions of the output control circuit 212 of memory array 11;
Step 44: output control circuit 212 is exported the signal of logic of propositions according to the signal of fuse circuit 211 outputs;
Step 45: according to the signal of output control circuit 212 outputs, output buffer 220 is closed, and the output of the anergy circuit 12 of memory array 11 presents high impedance, memory array 11 read functions anergies;
Step 46: finish.
In step 42, the fuse of blown fuse circuit 211 is pre-conditioned according to the user's.In the present embodiment, set pre-conditioned of user surveyed or whether the result of test phase such as packaging and testing is bad product at the wafer pin for memory 10.In addition, if memory array 11 also can be considered as bad product with it when there are misgivings on quality or the specification in any stage.
In step 43, when the fuse opening of fuse circuit 211, the signal of fuse circuit 211 outputs one logic of propositions of the output control circuit 212 of memory array 11.In the present embodiment, when memory array 11 during for product well, the signal of fuse circuit 211 output logics " 0 " (current potential of fuse circuit 211 outputs is held the electronegative potential of GND with being pulled to).When memory array 11 is bad product, the signal of fuse circuit 211 output logics " 1 " (current potential of fuse circuit 211 outputs is pulled to a high potential of voltage source V).
In step 44, the signal that output control circuit 212 is exported according to fuse circuit 211 is exported the signal of logic of propositions.In the present embodiment, signal (that is when memory array 11 is bad product) when fuse circuit 211 output logics " 1 ", no matter the data output end IO of memory array 11 and output enable end OE output is the signal of logical zero or " 1 ", second NAND gate 2124 of output control circuit 212 and NOR gate 2125 be the signal of output logic " 1 " and " 0 " respectively.
In step 45, because the signal that second NAND gate 2124 and NOR gate 2125 are exported is respectively logical one and " 0 ", first switch 231 and the second switch 232 of output buffer 220 are closed accordingly, cause the anergy circuit 12 (that is output of output buffer 220) of memory array 11 to present high impedance.When the anergy circuit 12 of memory array 11 presented high impedance, external circuit (as tester table) just can't come memory array 11 is read or writes by anergy circuit 12.
In sum, in the present invention, when memory array was classified bad product as, the anergy circuit can be exported the signal of a logic of propositions accordingly to allow the output of this anergy circuit present high impedance (or other default state).Therefore, by can't picking out this memory array easily and classify bad product as, reach and reduce encapsulation error, promote yield and reduce purposes such as testing time and cost actions such as this memory array read or writes.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (10)
1. a memory is characterized in that, comprises:
One memory array comprises a data output end and an output enable end; And
One anergy circuit, be coupled to this data output end and this output enable end, this anergy circuit comprises a fuse and an output, when this fuse is not blown, this anergy circuit determines the logic state of this output according to the logic state of this output enable end and this data output end, when this fuse was blown, it was a high impedance status that this anergy circuit makes this output.
2. memory according to claim 1 is characterized in that, this anergy circuit comprises:
One fuse circuit, being used for the state exchange that this fuse is not blown is a logical zero state, and the state exchange that this fuse is blown is a logical one state;
One output buffer is used for producing this logical zero state, this logical one state and this high impedance status in this output; And
One output control circuit, be used for controlling this output buffer, when this fuse be not blown and this output enable end when this logical one state, the logic state of this data output end is transferred to this output, when this fuse be blown or this output enable end when this logical zero state, make this output buffer produce this high impedance status.
3. memory according to claim 2 is characterized in that, this output control circuit comprises:
One first inverter is coupled to this fuse circuit, is used for a signal inversion that this fuse circuit is exported;
One first NAND gate is used for the signal that this output enable end and this first inverter are exported is carried out NAND operation, and comprise: one first end is coupled to this output enable end; And one second end, be coupled to an output of this first inverter;
One second inverter is coupled to an output of this first NAND gate, is used for signal inversion that this first NAND gate device is exported;
One second NAND gate is used for the signal that this output and this second inverter of this memory array are exported is carried out NAND operation, comprises: one first end is coupled to this output of this first memory array; One second end is coupled to an output of this second inverter; An and output; And
One NOR gate is used for the signal that this output of this first NAND gate and this memory array is exported is carried out NOR-operation, comprises: one first end is coupled to this output of this first NAND gate; One second end is coupled to this output of this memory array; An and output.
4. memory according to claim 3 is characterized in that, this output buffer comprises:
One first switch comprises: one first end is coupled to a voltage source; One second end is coupled to this output of this memory; And a control end, be coupled to this output of second NAND gate; And
One second switch comprises: one first end is coupled to this output of this memory; One second end is coupled to a ground end; And a control end, be coupled to this output of this NOR gate.
5. memory according to claim 4 is characterized in that, this first switch is a P-type mos transistor.
6. memory according to claim 4 is characterized in that, this second switch is a N type metal oxide semiconductor transistor.
7. a method that makes the memory anergy is characterized in that, comprises:
Provide an anergy circuit with a fuse to be arranged at the output of a memory; And
Blow this fuse so that this anergy circuit produces a high impedance status in the output of this memory.
8. method according to claim 7 is characterized in that other comprises:
Utilize a data output end and an output enable end of this memory to read the stored data of this memory; And
When this fuse was not blown, this anergy circuit determined the logic state of the output of this memory according to the logic state of this output enable end and this data output end.
9. method according to claim 8 is characterized in that, when this fuse was not blown, this anergy circuit determined the logic state of the output of this memory to comprise according to the logic state of this output enable end and this data output end:
When this output enable end is a logical one state, the logic state of this data output end is transferred to the output of this memory; And
When this output enable end is a logical zero state, make the output of this memory produce this high impedance status.
10. method according to claim 9 is characterized in that, when this output enable end was a logical one state, the output that the logic state of this data output end is transferred to this memory comprised:
When this data output end was this logical zero state, the output of this memory was exported this logical zero state; And
When this data output end was this logical one state, the output of this memory was exported this logical one state.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010539237.9A CN102034830B (en) | 2010-11-03 | 2010-11-03 | Memorizer with disabling circuit and method for disabling memorizer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010539237.9A CN102034830B (en) | 2010-11-03 | 2010-11-03 | Memorizer with disabling circuit and method for disabling memorizer |
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| CN102034830A true CN102034830A (en) | 2011-04-27 |
| CN102034830B CN102034830B (en) | 2012-12-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071833A (en) * | 2019-11-05 | 2020-12-11 | 友达光电股份有限公司 | Chip and method for manufacturing the same |
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|---|---|---|---|---|
| US5179540A (en) * | 1985-11-08 | 1993-01-12 | Harris Corporation | Programmable chip enable logic function |
| US20040239405A1 (en) * | 2003-06-02 | 2004-12-02 | Mayer Brian C. | Disabler circuit |
| CN1694183A (en) * | 2004-05-05 | 2005-11-09 | 台湾积体电路制造股份有限公司 | Device regulation and circuit offuse reference resistance regulation and electric device regulation method |
| US20060202232A1 (en) * | 2005-02-25 | 2006-09-14 | Oki Electric Industry Co., Ltd. | Memory control unit and memory system |
| US20090207663A1 (en) * | 2008-02-14 | 2009-08-20 | Sang-Gu Kang | Flash Memory Devices Including Ready/Busy Control Circuits and Methods of Testing the Same |
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2010
- 2010-11-03 CN CN201010539237.9A patent/CN102034830B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5179540A (en) * | 1985-11-08 | 1993-01-12 | Harris Corporation | Programmable chip enable logic function |
| US20040239405A1 (en) * | 2003-06-02 | 2004-12-02 | Mayer Brian C. | Disabler circuit |
| CN1694183A (en) * | 2004-05-05 | 2005-11-09 | 台湾积体电路制造股份有限公司 | Device regulation and circuit offuse reference resistance regulation and electric device regulation method |
| US20060202232A1 (en) * | 2005-02-25 | 2006-09-14 | Oki Electric Industry Co., Ltd. | Memory control unit and memory system |
| US20090207663A1 (en) * | 2008-02-14 | 2009-08-20 | Sang-Gu Kang | Flash Memory Devices Including Ready/Busy Control Circuits and Methods of Testing the Same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112071833A (en) * | 2019-11-05 | 2020-12-11 | 友达光电股份有限公司 | Chip and method for manufacturing the same |
| CN112071833B (en) * | 2019-11-05 | 2023-05-09 | 友达光电股份有限公司 | Chip |
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| CN102034830B (en) | 2012-12-12 |
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