CN102023476B - Semiconductor photoetching process method for forming micro-sized structure - Google Patents
Semiconductor photoetching process method for forming micro-sized structure Download PDFInfo
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- CN102023476B CN102023476B CN 200910195812 CN200910195812A CN102023476B CN 102023476 B CN102023476 B CN 102023476B CN 200910195812 CN200910195812 CN 200910195812 CN 200910195812 A CN200910195812 A CN 200910195812A CN 102023476 B CN102023476 B CN 102023476B
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Abstract
The invention provides a semiconductor photoetching process method for forming a micro-sized structure. The method comprises the following steps of: coating photoresist on the surface of a device and performing photoetching for the first time so as to form an area to be filled with crosslinking materials; filling the crosslinking materials into a filling area formed by a photoresist composition; under the definite reaction condition, fusing the joint between the crosslinking materials and the photoresist to form a crosslinking area; and etching the photoresist and the crosslinking materials to keep the crosslinking area, wherein the crosslinking area has etching selectivity, and the etching rate of the crosslinking area is lower than the etching rate of the photoresist and the crosslinking materials. According to the photoetching process method, the micro-sized structure of less than 45nm is photoetched so as to improve pattern resolution.
Description
Technical field
The present invention relates to a kind of semiconductor technology, particularly a kind of method of photoetching fine pattern.
Background technology
Along with the chip integration of integrated circuit is more and more higher, the design rule of semiconductor devices narrows down to 45nm from 65nm, at present to 32nm even the technique of smaller szie throw down the gauntlet.In the process of reduction process size, photoetching process is one of most important step.In order to obtain high density and high integration, what at first consider is to shorten the optical source wavelength that is used for exposure, makes the energy of exposing light beam stronger, and the irradiation of light beam is more concentrated, thereby obtains trickle pattern.The wavelength of the exposing light beam that adopts at present is to reach the extreme ultraviolet light higher than ultraviolet light frequency, i.e. so-called EUV photoetching technique.The EUV photoetching technique has been used for the above dynamic RAM (DRAM) of large-scale production 1GB, and its process can reach below 0.25 μ m.
Immersion lithography is also a photoetching process of developing in the process of reduction process size.Immersion lithography is that certain liquid is full of the numerical aperture that increases system between the lower surface of last lens of projection objective and silicon chip, the 193nm photoetching can be extended to below the 45nm technology node.
Yet when chip size further dwindled from 45nm, due to the corresponding improvement that can't obtain logarithm value aperture (NA), the improvement of photoetching process was faced with very large challenge.This problem narrows down under the process conditions of 22nm even more serious in size, this is because do not develop so far ripe EUV photoetching technique or the photoetching solution of high-NA (NA＞1.35) under 22nm technique.
Because traditional EUV photoetching technique or immersion lithography all are difficult to be applied to process node below 45nm, therefore, need a kind of improved photoetching technique can realize microtexture less below 45nm is carried out photoetching, to improve the resolution of pattern.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection domain of attempting to determine technical scheme required for protection.
Be difficult to be applied to process node below 45nm in order to solve traditional EUV photoetching technique or immersion lithography, the present invention proposes a kind of semiconductor lithography process method that is used to form structure of fine sizes, described method comprises: apply photoresist at device surface and carry out photoetching for the first time, to form the zone that will fill crosslinked formula material; With described crosslinked formula Material Filling in the fill area that is formed by the photoresist composition; Under certain reaction conditions, crosslinked formula material and photoresist intersection are produced merge, form crosslinked formula regional; Carry out etching, described photoresist and described crosslinked formula material are etched away, keep described crosslinked formula regional.
According to a further aspect in the invention, described crosslinked formula zone has etching selectivity, and its etch-rate is lower than the etch-rate of described photoresist and described crosslinked formula material.By controlling the reaction conditions of crosslinked formula material and photoresist fusion, can adjust the size in described crosslinked formula zone.
According to photoetching technological method of the present invention, can realize microtexture less below 45nm is carried out photoetching, improved the resolution of pattern.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1D makes the schematic diagram of semiconductor devices according to photoetching process of the present invention;
Fig. 2 A-2F makes the schematic diagram of microtexture gate electrode according to photoetching process of the present invention;
Fig. 3 is the process chart according to photoetching process of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and be implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that how explanation the present invention carries out improved to photoetching process in following description.Obviously, execution of the present invention is not limited to the specific details that the technician of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other embodiments.
According to the present invention, the material that will have certain special nature is applied in field of lithography, and particularly, this material is under certain reaction conditions and between photoresist, chemical reaction occurs, thereby merge at the interface at it, form " the crosslinked zone " with special nature.Therefore, this material with special nature of the present invention is called " crosslinked formula material ".
Figure 1A and 1B show the schematic diagram according to crosslinked formula material of the present invention and photoresist fusion.As shown in Figure 1A, apply photoresist 101 at device surface, photoresist 101 is carried out composition and exposure imaging, form a groove 100 in the centre, original photoresist 101 is divided into two parts regional 101 and 101 '.As shown in Figure 1B, crosslinked formula material 102 is filled in the groove 100 that is formed by photoresist 101 and 101 '.Under specific reaction conditions, for example carry out high temperature and cure, stoving temperature is 100 ℃-500 ℃, and the time is 10 seconds-150 seconds, crosslinked formula material 102 has produced partial fusion with photoresist 101 and the 101 ' place that has a common boundary, and has formed the crosslinked formula zone 103 as shown in Fig. 1 C.Described crosslinked formula zone 103 has etching selectivity, and namely under specific etching condition, the etch-rate in crosslinked formula zone 103 is well below photoresist 101 and 101 ' and the etch-rate of crosslinked formula material 102.That is to say, crosslinked formula zone 103 photo etching glue 100 and 101 ' and crosslinked formula material 102 be difficult to be etched away.Then, carry out the etch process step, for example dry etching or wet-etching technology, as shown in Fig. 1 D, photoresist 100 and 100 ' and crosslinked formula material 102 be etched away, and crosslinked formula zone 103 is owing to being difficult to etched so being retained.Dotted line in Fig. 1 D represents the zone that has been etched away.The reaction conditions that merges by controlling crosslinked formula material 102 and photoresist 100, for example control stoving temperature or cure the time, can adjust the width d (as described in Fig. 1 D) in crosslinked formula zone 103, thereby obtain required dimensional requirement, can be adjusted to the critical size less than photoetching process, thereby realize the structure of fine sizes.
Consider the material character of photoresist, described crosslinked formula material 102 can be selected like this: because the light in photoresistance acid can exist with R-COOH (carboxylic acids) form, under certain condition can and R ' OH (alcohols) esterification occurs.Therefore the R ' in R ' OH is the material of high molecular, such as macromolecular chain, could and photoresist in carboxylic acid form long or complicated difficult with destroyed structure, thereby and photoresist in conjunction with the zone of formation " densification " (being difficult to be destroyed by beam-plasma).The general formula of described macromolecule polyol is C
nH
2n+2-X(OH)
X, (wherein n＞=5, x＞=3).
Crosslinked formula material as above can be applied to for example be applied in the following technique of 45nm in the technique of gate electrode that photolithographic fabrication has superfine size.Exemplary technique is with reference to shown in Fig. 2 A-Fig. 2 F.Fig. 2 A-Fig. 2 F shows the technological process that according to the present invention, crosslinked formula material is applied to the gate electrode of the superfine size of photoetching.
As shown in Fig. 2 A, apply photoresist 201 at device surface, carry out photoetching for the first time, photoresist 201 is carried out composition and exposure imaging, have " fence " shape structure of a plurality of rectangular apertures 202 in the middle of forming.This photoetching for the first time is to form the zone of filling crosslinked formula material 203, and is therefore less demanding to lithographic accuracy, can realize by common EUV photoetching.Then as shown in Fig. 2 B, crosslinked formula material 203 is filled in these a plurality of openings 202.Under specific reaction conditions, for example carry out high temperature and cure, stoving temperature is 100 ℃-500 ℃, and the time is 10 seconds-150 seconds, and crosslinked formula material 203 has produced partial fusion with the place that photoresist 201 has a common boundary, and has formed the crosslinked formula zone 204 as shown in Fig. 2 C.Described crosslinked formula zone 204 has etching selectivity, and namely under specific etching condition, the etch-rate in crosslinked formula zone 204 is well below the etch-rate of photoresist 201 and crosslinked formula material 203.Then, carry out the etch process step, for example dry etching or wet-etching technology, as shown in Fig. 2 D, photoresist 201 and crosslinked formula material 203 all are etched away, and crosslinked formula zone 204 is owing to being difficult to etched so being retained.Dotted line in Fig. 1 D represents the zone that has been etched away.
Because crosslinked formula material 102 and photoresist 100 merge in two dimensional surface, so the gate electrode that generates in the step of Fig. 2 D is ring texture as shown in the figure.Then, as shown in Fig. 2 E, apply photoresist 205, carry out photoetching for the second time.The purpose of this time photoetching is the gate electrode that disconnects ring-type, therefore neither form the lithography step of critical size (CD), also can realize by common EUV photoetching for the requirement of lithographic accuracy.By photoetching for the second time, many gate electrodes 206 with superfine critical size have been formed.The reaction conditions that merges by controlling crosslinked formula material 203 and photoresist 201 is for example controlled stoving temperature or cures the time, can adjust the width of gate electrode 206, thereby reach the requirement of the following process conditions of 45nm.
Fig. 3 shows the process flow diagram that carries out photoetching technological method according to the present invention.In step 301, apply photoresist at device surface, carry out photoetching for the first time, the photoresist that applies is carried out composition and exposure imaging, to form the zone that will fill crosslinked formula material.In step 302, with crosslinked formula Material Filling in the fill area that is formed by the photoresist composition.Under specific reaction conditions, for example carry out high temperature and cure, stoving temperature is 100 ℃-500 ℃, and the time is 10 seconds-150 seconds, and the place that crosslinked formula material and photoresist have a common boundary has produced partial fusion, has formed crosslinked formula regional.Described crosslinked formula zone has etching selectivity, and namely under specific etching condition, the etch-rate in crosslinked formula zone is well below the etch-rate of photoresist and crosslinked formula material.Then, in step 303, carry out the etch process step, for example dry etching or wet-etching technology, etch away photoresist and crosslinked formula material, and crosslinked formula zone is owing to being difficult to etched so being retained.The reaction conditions that merges by controlling crosslinked formula material and photoresist is for example controlled stoving temperature or cures the time, can adjust the width in crosslinked formula zone.
Alternatively, can also carry out lithography step 304 for the second time, the crosslinked formula zone that step 303 is formed is composition again.
Be understandable that for those skilled in the art, the crosslinked formula material selected according to the present invention is not limited to the concrete material that above-described embodiment is enumerated, merge as long as can react under certain condition with photoresist, can generate the material in the crosslinked zone with Etch selectivity, all within the scope that the present invention is contained.Also being not limited to the listed high temperature of the present invention according to the condition of crosslinked formula material of the present invention and photoresist generation fusion reaction cures, the time of curing and temperature are only also exemplary, can select low temperature other reaction process conditions well known in the art arbitrarily such as to cure according to material character.After crosslinked formula material and photoresist generation fusion reaction generate crosslinked formula zone, the mode that crosslinked formula material and photoresist are removed in etching also can adopt any technique well known in the art, as the plasma dry etching, physical property dry etching, chemistry dry etching, physical chemistry dry etching etc., the parameters such as the atmosphere of etching gas and energy can be selected and regulate according to the etching selection characteristic in the crosslinked formula zone that generates.Also can adopt wet etching, the composition of selected etching solution, the parameters such as time of immersion also can be selected and regulate according to the etching selection characteristic in the crosslinked formula zone that generates.
To be used for according to crosslinked formula material of the present invention the technique of photoetching fine dimension structure, need not the parameters such as exposing light beam energy, time shutter are carried out special restriction, only need crosslinked formula material is selected, control the reaction conditions that crosslinked formula material and photoresist merge, thereby control the crosslinked area size that forms, can form the gate electrode of required fine dimension.Therefore, can realize microtexture less below 45nm is carried out photoetching according to technique of the present invention, obtain to have more high-resolution photoengraving pattern.
Can be applicable in multiple integrated circuit (IC) according to the semiconductor devices with structure of fine sizes of embodiment manufacturing as above.For example memory circuitry according to IC of the present invention, as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or ROM (read-only memory) (ROM) etc.Can also be logical device according to IC of the present invention, as programmable logic array (PLA), special IC (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio frequency (RF) device or other circuit devcies arbitrarily.
IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera.
In sum, be only preferred embodiment of the present invention, be not the present invention is done any pro forma restriction.Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art are not breaking away from technical solution of the present invention scope situation, all can utilize the method for above-mentioned announcement and technology contents to make possible change and modification to technical solution of the present invention, or are revised as the embodiment that is equal to of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.
Claims (9)
1. semiconductor lithography process method that is used to form structure of fine sizes, described method comprises:
Apply photoresist at device surface and carry out photoetching for the first time, to form the zone that will fill crosslinked formula material, described photoetching for the first time is that described photoresist is carried out composition and exposure imaging;
With described crosslinked formula Material Filling in the fill area that is formed by the photoresist composition;
Under certain reaction conditions, crosslinked formula material and photoresist intersection are produced merge, form crosslinked formula regional, described reaction conditions is to carry out high temperature to cure, and stoving temperature is 100 ℃-500 ℃, and the time is 10 seconds-150 seconds;
Carry out etching, described photoresist and described crosslinked formula material are etched away, keep described crosslinked formula zone, described crosslinked formula zone has etching selectivity, and its etch-rate is lower than the etch-rate of described photoresist and described crosslinked formula material.
2. semiconductor lithography process method as claimed in claim 1, wherein said etching is dry etching or wet-etching technology.
3. semiconductor lithography process method as claimed in claim 1 is wherein adjusted the size in described crosslinked formula zone by controlling reaction conditions that crosslinked formula material and photoresist merge.
4. semiconductor lithography process method as claimed in claim 1, wherein said crosslinked formula material is macromolecule polyol, its general formula is C
nH
2n+2-X(OH)
X, n wherein 〉=5, x 〉=3.
5. semiconductor lithography process method as claimed in claim 1, described method also comprise the step that photoetching is for the second time carried out in described crosslinked formula zone.
6. semiconductor lithography process method as claimed in claim 1, wherein said photoetching for the first time is extreme ultraviolet photoetching or liquid immersion lithography.
7. semiconductor lithography process method as claimed in claim 5, wherein said photoetching for the second time is extreme ultraviolet photoetching or liquid immersion lithography.
8. integrated circuit that comprises the semiconductor devices of making by the method for claim 1, wherein said integrated circuit is selected from dynamic RAM, synchronous RAM, static RAM, ROM (read-only memory), programmable logic array and radio circuit.
9. electronic equipment that comprises the semiconductor devices of making by the method for claim 1, wherein said electronic equipment personal computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
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| CN105655249A (en) * | 2016-03-21 | 2016-06-08 | 京东方科技集团股份有限公司 | Etching method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221971A (en) * | 1997-12-31 | 1999-07-07 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
| JP2003203396A (en) * | 2001-10-23 | 2003-07-18 | Matsushita Electric Ind Co Ltd | Direct stamper, its manufacturing method and optical disc |
| US20080064213A1 (en) * | 2006-09-12 | 2008-03-13 | Hynix Semiconductor Inc. | Method for forming a fine pattern of a semiconductor device |
| KR20080024054A (en) * | 2006-09-12 | 2008-03-17 | 주식회사 하이닉스반도체 | Method for forming fine patterns of semiconductor devices |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1221971A (en) * | 1997-12-31 | 1999-07-07 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
| JP2003203396A (en) * | 2001-10-23 | 2003-07-18 | Matsushita Electric Ind Co Ltd | Direct stamper, its manufacturing method and optical disc |
| US20080064213A1 (en) * | 2006-09-12 | 2008-03-13 | Hynix Semiconductor Inc. | Method for forming a fine pattern of a semiconductor device |
| KR20080024054A (en) * | 2006-09-12 | 2008-03-17 | 주식회사 하이닉스반도체 | Method for forming fine patterns of semiconductor devices |
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