CN102016790B - 数据处理系统中的高速缓存一致性协议 - Google Patents

数据处理系统中的高速缓存一致性协议 Download PDF

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Publication number
CN102016790B
CN102016790B CN200980115765.7A CN200980115765A CN102016790B CN 102016790 B CN102016790 B CN 102016790B CN 200980115765 A CN200980115765 A CN 200980115765A CN 102016790 B CN102016790 B CN 102016790B
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data
cache
write
state
processing system
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Chinese (zh)
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CN102016790A (zh
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威廉·C·莫耶
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NXP USA Inc
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Freescale Semiconductor Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN200980115765.7A 2008-04-30 2009-02-23 数据处理系统中的高速缓存一致性协议 Expired - Fee Related CN102016790B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/112,502 2008-04-30
US12/112,502 US8762652B2 (en) 2008-04-30 2008-04-30 Cache coherency protocol in a data processing system
PCT/US2009/034866 WO2009134517A1 (en) 2008-04-30 2009-02-23 Cache coherency protocol in a data processing system

Publications (2)

Publication Number Publication Date
CN102016790A CN102016790A (zh) 2011-04-13
CN102016790B true CN102016790B (zh) 2014-08-06

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US (1) US8762652B2 (enExample)
JP (1) JP5583660B2 (enExample)
CN (1) CN102016790B (enExample)
TW (1) TW200945057A (enExample)
WO (1) WO2009134517A1 (enExample)

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KR102809573B1 (ko) * 2016-12-12 2025-05-20 인텔 코포레이션 프로세서 아키텍처에 대한 장치들 및 방법들
US10282296B2 (en) 2016-12-12 2019-05-07 Intel Corporation Zeroing a cache line
US10282297B2 (en) * 2017-02-08 2019-05-07 Arm Limited Read-with overridable-invalidate transaction
US10599567B2 (en) 2017-10-06 2020-03-24 International Business Machines Corporation Non-coherent read in a strongly consistent cache system for frequently read but rarely updated data
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Also Published As

Publication number Publication date
US8762652B2 (en) 2014-06-24
JP5583660B2 (ja) 2014-09-03
TW200945057A (en) 2009-11-01
CN102016790A (zh) 2011-04-13
JP2011519461A (ja) 2011-07-07
US20090276578A1 (en) 2009-11-05
WO2009134517A1 (en) 2009-11-05

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Address after: Texas in the United States

Patentee after: NXP USA, Inc.

Address before: Texas in the United States

Patentee before: FREESCALE SEMICONDUCTOR, Inc.

CF01 Termination of patent right due to non-payment of annual fee
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Granted publication date: 20140806