CN102012480A - Method for testing dispatching of on-chip systematic embedded logical core by multistage order algorithm - Google Patents

Abstract

The invention relates to a method for testing dispatching of an on-chip systematic embedded logical core by a multistage order algorithm. The operation method comprises the following steps of: establishing and initializing a dispatching matrix Z; line expanding the dispatching matrix Z; line contracting the dispatching matrix X; two-dimensionally dispatching and sequencing the total testing band width to the total testing time (W-T) of the dispatching matrix Z; double-traversing a total testing band width-adjusting factor (W-alpha) of the dispatching matrix Z; and generating a report. The invention is capable of effectively and integrally solving the two independently problems of the test dispatching of the on-chip systematic embedded logical core and the test link chaining in the logical core, thereby effectively reducing the testing time and testing cost of the on-chip system. The method is convenient in operation, and is applicable to various on-chip systems for finishing the measurability design of the logical core by scanning chain.

Description

The multi-stage sequencing algorithm applies to the method for the embedded logic cores test dispatching of SOC (system on a chip)

Technical field

The present invention relates to the embedded logic cores test dispatching of a kind of SOC (system on a chip) method, particularly a kind of multi-stage sequencing algorithm applies to the method for the embedded logic cores test dispatching of SOC (system on a chip).

Background technology

Because logic cores is reused the use of method for designing, sudden change has taken place in the design scale of integrated circuit and realization function, and (VLSI, Very Large Scale Integration Circuit) develops into present SOC (system on a chip) by original VLSI (very large scale integrated circuit).But, along with the system-on-chip designs scale increases, the function complexity improves, and the design cycle shortening, the problem of a sternness manifests day by day, i.e. and the test of SOC (system on a chip) has become the bottleneck problem that hinders the SOC (system on a chip) development.Effectively reduce the difficulty of test and the testing cost of SOC (system on a chip), become an extremely important approach that promotes the SOC (system on a chip) synthesized competitiveness.

Because the numerous logic cores that are embedded among the SoC are providing aspects such as source, circuit structure and design style to have complicated diversity, the test job of the no longer competent SoC of traditional integrated circuit (IC) testing method, must use SoC design for Measurability (DFT, Design For Testability) method to finish.At present, the resolution chart that mainly is to use Different Logic core supplier to provide to the test of SoC is finished the test of corresponding embedded logic cores.For this reason, must in SoC design for Measurability process, set up the test of carrying out the test data transmission between test wrapper, SoC I/O end and each IP kernel that each embedded logic core is endorsed independently test and look for design for Measurability hardware structures such as mechanism.Simultaneously, in order further effectively to improve SoC test resource utilization factor and to reduce the SoC test duration, also must set up perfect test dispatching strategy.

How test dispatching determines the embedded logic cores build-in test of SOC (system on a chip) link chaining and the embedded logic cores test dispatching of SOC (system on a chip) two parts actual comprising.Current, the most general way to the optimization of sorting respectively of these two parts, is independently treated exactly.Yet, should be noted that these two parts in fact are closely related, ordering optimization is optimum under situation separately respectively, but both combinations, just real desired result is not the most desirable or optimization.Therefore, be necessary to study the method for the unified disposable solution test dispatching of the multi-stage sequencing algorithm problem of a kind of usefulness, effectively solve and the test dispatching that improves the embedded logic cores of SOC (system on a chip).

Summary of the invention

The object of the present invention is to provide a kind of multi-stage sequencing algorithm to apply to the method for the embedded logic cores test dispatching of SOC (system on a chip), the embedded logic cores test dispatching of SOC (system on a chip) and two relatively independent in the past problems of logic cores build-in test link chaining can be unified to solve effectively, and then can reduce the test duration and the test expense of SOC (system on a chip) effectively.The present invention is easy to operate, is applicable to various SOC (system on a chip) with scan chain mode completion logic core design for Measurability.

For reaching above-mentioned purpose, the present invention adopts following technical proposals:

A kind of multi-stage sequencing algorithm applies to the method for the embedded logic cores test dispatching of SOC (system on a chip), read in by the SoC file, the ordering degree of depth and priority criteria are set, utilization multi-stage sequencing algorithm, obtain optimum logic cores test dispatching result on the logic cores test dispatching, it is characterized in that operation steps is: (1) dispatch matrix Z sets up and initialization, (2) the capable expansion of dispatch matrix Z, (3) the capable contraction of dispatch matrix Z, (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling, (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α) and (6) report generation; Described step (1) dispatch matrix Z sets up with initialization: read the SoC file, this document meets the SoC file layout that ITC ' 02 (International Test Conference 2002) formulates, therefrom obtain the logic cores sum p among the SoC, initialization dispatch matrix Z, element among the dispatch matrix Z is a test link chaining object, and this object has two dimension attributes of logic cores bandwidth w and logic cores test duration t; The capable expansion of described step (2) dispatch matrix Z is: by setting test link chaining ordering degree of depth m, each logic cores is formed m test link chaining object by specific formula, thus row expansion dispatch matrix Z; The capable contraction of described step (3) dispatch matrix Z is: by priority criteria is set, m test link chaining object carried out scalarization ordering by priority criteria respectively listing, obtain preferential test link chaining object, abandon all the other test link chaining objects, thereby row shrinks dispatch matrix Z; Described step (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling: under given total test bandwidth and regulatory factor α condition, common p test link chaining object among the dispatch matrix Z of row contraction always tested bandwidth-total test duration (W-T) two dimension ordering obtain total test duration T, test and results such as line number R, idleness IR and logic cores test dispatching strategy; Described step (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α): obtain all effectively total test bandwidth W value and regulatory factor α values from the dispatch matrix Z that row shrinks, always test the dual traversal of bandwidth-regulatory factor (W-α) by dispatch matrix Z always being tested bandwidth-total test duration (W-T) two-dimentional scheduling, thereby obtain all results, and by first total test duration T again the priority of idleness IR last test and line number R the result is sorted, thereby determine final unique test result; Described step (6) report is generated as above institute each details in the operating process and the result forms text respectively and figure is reported in steps.

It is to discern the SoC file layout of being stipulated by ITC ' 02 automatically that above-mentioned steps (1) dispatch matrix Z sets up with initialization, obtain logic cores sum p, foundation has the tables of data of p list item in inside, each list item of this tables of data carries out related with each row of dispatch matrix Z that are initially 0 row p row, each list item all contains the every important information that extracts from the SoC file: input port is counted In, output port is counted Out, and internal scan chain is counted n, each bar scan chain length { s ₁.., s _n, and test pattern figurate number tp; In addition, described dispatch matrix Z foundation also has with initialization (1) to be rejected automatically, incomplete important information is carried out the default ability of filling up automatically the information that does not meet file layout, can import SoC file or other SoC file to be scheduled of renewal repeatedly, import the SoC file, and no longer re-enter or close when input, any operation can not destroy tables of data and the dispatch matrix Z that portion has within it set up.

The capable expansion of above-mentioned steps (2) dispatch matrix Z is according to the ordering degree of depth m that sets and logic cores sum p following formula to be circulated to find the solution,

$\underset{a_{\mathrm{ij}},I_i,O_i}{\min }\underset{1\≤i\≤w}{\mathrm{\Σ}}\left(\right|\underset{j=1}{\overset{n}{\mathrm{\Σ}}}{s}_j{a}_{\mathrm{ij}}+I_i-\frac{\underset{1\≤j\≤n}{\mathrm{\Σ}}{s}_j+\mathrm{In}}{w}|+|\underset{j=1}{\overset{n}{\mathrm{\Σ}}}{s}_j{a}_{\mathrm{ij}}+O_i-\frac{\underset{1\≤j\≤n}{\mathrm{\Σ}}{s}_j+\mathrm{Out}}{w}\left|\right)$

$s.t.\underset{i=1}{\overset{w}{\mathrm{\Σ}}}{a}_{\mathrm{ij}}=1,a_{\mathrm{ij}}\∈\left\{\mathrm{0,1}\right\}$

$\underset{i=1}{\overset{w}{\mathrm{\Σ}}}{I}_i=\mathrm{In},\underset{i=1}{\overset{w}{\mathrm{\Σ}}}{O}_i=\mathrm{Out},I_i,O_i\∈Z^{+};$

Detailed process is: obtain the information in each list item from the tables of data with p list item successively, the above formula of substitution is found the solution decision variable a _Ij, I _i, O _iAnd same list item carried out finding the solution for m time, when finding the solution at every turn, logic cores bandwidth w equals number of times, end loop is found the solution the back and is obtained m * p test link chaining object, logic cores bandwidth w attribute in each test link chaining object is determined in solution procedure, and another attribute logic cores test duration t is calculated by following formula

$\{1+\max [\underset{1\&le;i\&le;w}{\mathrm{<figure-callout\; id="1"\; label="max"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">max</figure-callout>}}(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+I_i),\underset{1\&le;i\&le;w}{\mathrm{<figure-callout\; id="1"\; label="max"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">max</figure-callout>}}(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+O_i)\left]\right\}\&times;\mathrm{tp}$

$+\min \left[\max (\underset{1\&le;i\&le;w}{\mathrm{<figure-callout\; id="1"\; label="max"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">max</figure-callout>}}(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+I_i),\underset{1\&le;i\&le;w}{\mathrm{<figure-callout\; id="1"\; label="max"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">max</figure-callout>}}(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+O_i)\right];$

According to dispatch matrix Z capable the expand to m capable p row of this m * p test link chaining object, shown in following formula to being initially 0 row p row:

$Z=\left[\begin{array}{cccccc}{A}_{11}({\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">w</figure-callout>}}_1,t_1)& A_{21}({\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">w</figure-callout>}}_1,t_1)& L& A_{i1}({\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">w</figure-callout>}}_1,t_1)& L& A_{p1}({\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">w</figure-callout>}}_1,t_1)\\ A_{12}({\mathrm{<figure-callout\; id="2"\; label="w"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">w</figure-callout>}}_2,t_2)& A_{22}({\mathrm{<figure-callout\; id="2"\; label="w"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">w</figure-callout>}}_2,t_2)& L& A_{i2}({\mathrm{<figure-callout\; id="2"\; label="w"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">w</figure-callout>}}_2,t_2)& L& A_{p2}({\mathrm{<figure-callout\; id="2"\; label="w"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">w</figure-callout>}}_2,t_2)\\ M& M& M& M& M& M\\ A_{1m}(w_m,t_m)& A_{2m}(w_m,t_m)& L& A_{\mathrm{im}}(w_m,t_m)& L& A_{\mathrm{pm}}(w_m,t_m)\end{array}\right];$

Simultaneously, the capable expansion of described dispatch matrix Z (2) can be set ordering degree of depth m repeatedly to obtain new dispatch matrix Z.

Above-mentioned steps (3) dispatch matrix Z is capable shrink provide the priority criteria function f that can set up on their own (w, t), this function with the logic cores bandwidth w of test link chaining object and logic cores test duration t attribute as parameter; According to the priority criteria function that sets up on their own dispatch matrix Z is reset with the ascending order that the unit of classifying as carries out scalarization, when the priority criteria function is not set, then according to default priority criteria function f (w, t)=and w * (w+t) dispatch matrix Z is reset with the ascending order that the unit of classifying as carries out scalarization, it is capable to m that dispatch matrix Z after resetting is abandoned the 2nd row, make it degenerate to 1 row p row, shown in following formula:

Z＝[A ₁(w，t)A ₂(w，t)L A _i(w，t)L A _p(w，t)]。

It is to being total to p the test link chaining object with logic cores bandwidth w and logic cores test duration t attribute among the dispatch matrix Z that above-mentioned steps (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling, with w * t is index, carry out the scalarization descending sort, upgrade dispatch matrix Z, as following formula:

Z＝[X ₁(w，t)X ₂(w，t)L X _i(w，t)L X _p(w，t)]；

Under given total test bandwidth W, find the solution decision variable b according to following formula _i, in the formula, α is a regulatory factor,

$\underset{b_i}{\min }\underset{i=1}{\overset{p}{\mathrm{\&Sigma;}}}[\mathrm{\&alpha;}\&CenterDot;i-X_i\left(w\right)]\&CenterDot;b_i$

$s.t.\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{X}_i\left(w\right)\&CenterDot;b_i\&le;W,b_i\&Element;\left\{\mathrm{0,1}\right\};$

According to the decision variable b that tries to achieve, preferentially choose and line number

Individual first test link chaining object, in the enterprising row labels of dispatch matrix Z, the call number of correspondence is set up total test bandwidth (W) that length is R-total test duration (T) two dimension ordering chained list as node, data element in the chained list is pressed the logic cores test duration t attribute descending sort of corresponding test link chaining object, and is that this R corresponding test link chaining object increases by two couples of rectangular coordinate information (x ₁, y ₁) and (x ₂, y ₂), its relation as following formula:

$\left\{\begin{array}{c}{x}_{2L\left(i\right)}=x_{1i}+t_i\\ {\mathrm{<figure-callout\; id="2L"\; label="y"\; filenames="HSA00000282494700031.png"\; state="\{\{state\}\}">y</figure-callout>}}_{2L\left(i\right)}=y_{1i}+X_i\left(w\right)\end{array}\right.\left\{\begin{array}{c}{x}_{1L\left(i\right)}=0\\ y_{1L\left(i\right)}=y_{2[L\left(i\right)-1]}\end{array}\right.\left\{\begin{array}{c}{x}_{1L\left(1\right)}=0\\ y_{1L\left(1\right)}=0\end{array}\right.,$

Wherein L (i) expression chain table index i is to the mapping of dispatch matrix Z call number, and four control variable e, l, u, v are set up in inside simultaneously, and e is used for being recorded in the corresponding minimum x of chained list ₂Chain table index, l be that chained list length, u are used to write down available idle bandwidth and use formula

Calculate, v is used for writing down the transverse axis position of idle bandwidth at rectangular coordinate; Under the initial situation, e is the chained list tail, l=R, u=W-y _{2L (R)}, v=0, will finish the ordering of the total test duration T two dimension of all total test bandwidth of residue W-according to following steps subsequently:

1. on dispatch matrix Z, in the unlabelled test link chaining object, seek the test link chaining object X of logic cores bandwidth w less than control variable u by the call number increment _fIn case, find to stop at once seeking, in the enterprising row labels of dispatch matrix Z,

Call number f is appended to the afterbody of two dimension ordering chained list, for this test link chaining object increase by two pairs of rectangular coordinate information (0, u-X _fAnd (X (w)) _f(t), W), upgrade control variable e, l, u, v; As l＞R, R is updated to l; Whether find all execution in step 2..

2. seek next X by 1. identical mode _fAnd mark, for this test link chaining object increase by two pairs of rectangular coordinate information (0, y _1f) and (X _f(t), y _1f+ X _f(w)), if e not at the chained list tail, then tightly is inserted in call number f after the chain table position e, at this moment, if x _{2L (e)}＞x _{2L (e+1)}, y then _1f=y _{2L (e)}, use interim method L simultaneously ^-1(f) upgrade e, otherwise y _1f=y _{2L (e)}+ u-X _f(w), and not upgrade e; If e at the chained list tail, then tightly is inserted in call number f before the chain table position e, y _1f=y _{2L (e-1)}, use interim method L simultaneously ^-1(f) upgrade e, execution in step 2. subsequently; If again can't find such X _fAnd dispatch matrix is not labeled full, then upgrades e (non-interim method), l, u, v and R, enters step more 3.; If dispatch matrix is labeled full, then finish sequencer procedure.

3. u is revised, if e at linked list head, then correction formula is u=y _{1L (e+1)}If e is in chained list, then correction formula is u=y _{1L (e+1)}-y _{2L (e-1)}If e is at the chained list tail, then correction formula is u=W-y _{2L (e-1)}, continue execution in step 4..4. seek next X by 1. identical mode _fAnd mark, deposit call number f in chain table position e, and be that this test link chaining object increases by two couples of rectangular coordinate information (v, y _1f) and (v+X _f(t), y _1f+ X _f(w)), if e at linked list head, y then _1f=0; If e is at chained list tail, then y _1f=W-X _f(w); If e in chained list, at this moment, if x _{2L (e-1)}＞x _{2L (e+1)}, y then _1f=y _{2L (e-1)}, otherwise, y _1f=y _{1L (e+1)}-X _f(w); If there is no such X _fAnd dispatch matrix is not labeled full, and then no matter whether deletion of node e find, and is full as long as dispatch matrix is not labeled, and then upgrades e (non-interim method), l, v and R, enters step more 3., otherwise finishes sequencer procedure.

It is always to test the dual traversal of bandwidth-regulatory factor (W-α) and obtain all test dispatching results by dispatch matrix Z always being tested bandwidth-total test duration (W-T) two-dimentional scheduling that above-mentioned steps (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α); Its reason is: when always testing bandwidth-total test duration (W-T) two dimension ordering, be used to produce the specific formula of first test link chaining object, its regulatory factor α only exists

Or

(look the α that solves by following formula _kWhether contain 0 and decide) that first selection result is produced is different, this

Or

The end points in individual interval can be found the solution acquisition by following formula,

${\mathrm{\&alpha;}}_k=\frac{X_i\left(w\right)-X_j\left(w\right)}{i-j}i=1\mathrm{Kp},j=1\mathrm{Kp},i\&NotEqual;j,k=1k{\mathrm{<figure-callout\; id="2"\; label="C\; P"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">C</figure-callout>}}_P^{},$

In addition, the effective range of always testing bandwidth (W) is for from MAX (X _i(w)) to SUM (X _i(w)) all integers.Therefore, limited total test bandwidth (W) and regulatory factor (α) have constituted the dual traversal of total test bandwidth-regulatory factor (W-α), and its concrete dual traversal mode is: always test bandwidth (W) from MAX (X _i(w)) beginning adds 1 one by one until SUM (X _i(w)) till, on each value, regulatory factor α chooses each interval intermediate value one by one, for last interval

Then with As selected value; After obtaining all test dispatching results, by earlier total test duration (T) again the priority of idleness (IR) last test and line number (R) result is sorted, thereby determine final unique test dispatching result; The information that comprises among this test dispatching result has final total test bandwidth (W), final total test duration (T), final idleness (IR), final test and line number (R) and final logic cores test dispatching strategy.

Above-mentioned steps (6) report is generated as each details and the result of all other steps in operating process and forms text and figure report respectively, and text entry is carried out in the operating process that is each step, indicates step source, operation name and service data in the record; The text report generates and figure report generation for the operating result of each step carries out.

The present invention compared with prior art, has following conspicuous advantage: the present invention is directed to the test dispatching link in the SOC (system on a chip) design for Measurability, the design and the realization of the embedded logic cores test dispatching of SOC (system on a chip) method have been studied, and use the multi-stage sequencing algorithm, and then can reduce the test duration and the test expense of SOC (system on a chip) effectively with embedded logic cores test dispatching of SOC (system on a chip) and the unified effectively solution of two relatively independent in the past problems of logic cores build-in test link chaining.

Description of drawings

Fig. 1 is the step structural drawing of one embodiment of the invention.

Fig. 2 is that dispatch matrix Z sets up and initialized process flow diagram in Fig. 1 example.

Fig. 3 is the process flow diagram of the capable expansion of dispatch matrix Z in Fig. 1 example.

Fig. 4 is the process flow diagram of the capable contraction of dispatch matrix Z in Fig. 1 example.

Fig. 5 is the process flow diagram that dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling in Fig. 1 example.

Fig. 6 is the process flow diagram that dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α) in Fig. 1 example.

Embodiment

A preferential embodiment of the present invention is: referring to Fig. 1, the multi-stage sequencing algorithm is applied to the method for the embedded logic cores test dispatching of SOC (system on a chip), it reads in by the SoC file, the ordering degree of depth and priority criteria are set, utilization multi-stage sequencing algorithm, obtain optimum logic cores test dispatching result on the logic cores test dispatching, operation steps is that (1) dispatch matrix Z sets up and initialization, (2) the capable expansion of dispatch matrix Z, (3) the capable contraction of dispatch matrix Z, (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling, (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α) and (6) report generation; Step (1) dispatch matrix Z sets up with initialization: read the SoC file, this document meets the SoC file layout that ITC ' 02 (International TestConference 2002) formulates, therefrom obtain the logic cores sum p among the SoC, initialization dispatch matrix Z, element among the dispatch matrix Z is a test link chaining object, and this object has two dimension attributes of logic cores bandwidth w and logic cores test duration t; The capable expansion of step (2) dispatch matrix Z is: by setting test link chaining ordering degree of depth m, each logic cores is formed m test link chaining object by specific formula, thus row expansion dispatch matrix Z; The capable contraction of step (3) dispatch matrix Z is: by priority criteria is set, m test link chaining object carried out scalarization ordering by priority criteria respectively listing, obtain preferential test link chaining object, abandon all the other test link chaining objects, thereby row shrinks dispatch matrix Z; Step (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling: under given total test bandwidth and regulatory factor α condition, common p test link chaining object among the dispatch matrix Z of row contraction always tested bandwidth-total test duration (W-T) two dimension ordering obtain total test duration T, test and results such as line number R, idleness IR and logic cores test dispatching strategy; Step (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α): obtain all effectively total test bandwidth W value and regulatory factor α values from the dispatch matrix Z that row shrinks, always test the dual traversal of bandwidth-regulatory factor (W-α) by dispatch matrix Z always being tested bandwidth-total test duration (W-T) two-dimentional scheduling, thereby obtain all results, and by first total test duration T again the priority of idleness IR last test and line number R the result is sorted, thereby determine final unique test result; Step (6) report is generated as above institute each details in the operating process and the result forms text respectively and figure is reported in steps.

Referring to Fig. 2, above-mentioned steps (1) dispatch matrix Z sets up with initialization: identification is by the SoC file layout of ITC ' 02 regulation automatically, obtain logic cores sum p, foundation has the tables of data of p list item in inside, each list item of this tables of data and each row of dispatch matrix Z that are initially 0 row p row carry out related, and each list item all contains the every important information that extracts from the SoC file: input port is counted In, and output port is counted Out, internal scan chain is counted n, each bar scan chain length { s ₁.., s _n, and test pattern figurate number tp; In addition, above-mentioned dispatch matrix Z foundation also has with initialization (1) to be rejected automatically, incomplete important information is carried out the default ability of filling up automatically the information that does not meet file layout, can import SoC file or other SoC file to be scheduled of renewal repeatedly, import the SoC file, and no longer re-enter or close when input, any operation can not destroy tables of data and the dispatch matrix Z that portion has within it set up.

Referring to Fig. 3, above-mentioned steps (2) dispatch matrix Z is capable, and expansion is: according to the ordering degree of depth m that sets and logic cores sum p following formula is circulated and find the solution,

$\underset{a_{\mathrm{ij}},I_i,O_i}{\min }\underset{1\&le;i\&le;w}{\mathrm{\&Sigma;}}\left(\right|\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+I_i-\frac{\underset{1\&le;j\&le;n}{\mathrm{\&Sigma;}}{s}_j+\mathrm{In}}{w}|+|\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+O_i-\frac{\underset{1\&le;j\&le;n}{\mathrm{\&Sigma;}}{s}_j+\mathrm{Out}}{w}\left|\right)$

$s.t.\underset{i=1}{\overset{w}{\mathrm{\&Sigma;}}}{a}_{\mathrm{ij}}=1,a_{\mathrm{ij}}\&Element;\left\{\mathrm{0,1}\right\}$

$\underset{i=1}{\overset{w}{\mathrm{\&Sigma;}}}{I}_i=\mathrm{In},\underset{i=1}{\overset{w}{\mathrm{\&Sigma;}}}{O}_i=\mathrm{Out},I_{i,}{O}_i\&Element;Z^{+};$

Detailed process is: obtain the information in each list item from the tables of data with p list item successively, the above formula of substitution is found the solution decision variable a _Ij, I _i, O _iAnd same list item carried out finding the solution for m time, when finding the solution at every turn, logic cores bandwidth w equals number of times, end loop is found the solution the back and is obtained m * p test link chaining object, logic cores bandwidth w attribute in each test link chaining object is determined in solution procedure, and another attribute logic cores test duration t is calculated by following formula

$\{1+\max [\underset{1\&le;i\&le;w}{\mathrm{<figure-callout\; id="1"\; label="max"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">max</figure-callout>}}(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+I_i),\underset{1\&le;i\&le;w}{\mathrm{<figure-callout\; id="1"\; label="max"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">max</figure-callout>}}(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+O_i)\left]\right\}\&times;\mathrm{tp}$

$+\min [\max \left(\underset{1\&le;i\&le;w}{\mathrm{<figure-callout\; id="1"\; label="max"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">max</figure-callout>}}\right(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+I_i),\underset{1\&le;i\&le;w}{\mathrm{<figure-callout\; id="1"\; label="max"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">max</figure-callout>}}(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+O_i)];$

According to dispatch matrix Z capable the expand to m capable p row of this m * p test link chaining object, shown in following formula to being initially 0 row p row:

$Z=\left[\begin{array}{cccccc}{A}_{11}({\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">w</figure-callout>}}_1,t_1)& A_{21}({\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">w</figure-callout>}}_1,t_1)& L& A_{i1}({\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">w</figure-callout>}}_1,t_1)& L& A_{p1}({\mathrm{<figure-callout\; id="1"\; label="w"\; filenames="HSA00000282494700011.png,HSA00000282494700031.png"\; state="\{\{state\}\}">w</figure-callout>}}_1,t_1)\\ A_{12}({\mathrm{<figure-callout\; id="2"\; label="w"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">w</figure-callout>}}_2,t_2)& A_{22}({\mathrm{<figure-callout\; id="2"\; label="w"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">w</figure-callout>}}_2,t_2)& L& A_{i2}({\mathrm{<figure-callout\; id="2"\; label="w"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">w</figure-callout>}}_2,t_2)& L& A_{p2}({\mathrm{<figure-callout\; id="2"\; label="w"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">w</figure-callout>}}_2,t_2)\\ M& M& M& M& M& M\\ A_{1m}(w_m,t_m)& A_{2m}(w_m,t_m)& L& A_{\mathrm{im}}(w_m,t_m)& L& A_{\mathrm{pm}}(w_m,t_m)\end{array}\right];$

Simultaneously, the capable expansion of above-mentioned dispatch matrix Z (2) can be set ordering degree of depth m repeatedly to obtain new dispatch matrix Z.

Referring to Fig. 4, capable shrink of above-mentioned steps (3) dispatch matrix Z is: provide the priority criteria function f that can set up on their own (w, t), this function with the logic cores bandwidth w of test link chaining object and logic cores test duration t attribute as parameter; According to the priority criteria function that sets up on their own dispatch matrix Z is reset with the ascending order that the unit of classifying as carries out scalarization, when the priority criteria function is not set, then according to default priority criteria function f (w, t)=and w * t * (w+t) dispatch matrix Z is reset with the ascending order that the unit of classifying as carries out scalarization, it is capable to m that dispatch matrix Z after resetting is abandoned the 2nd row, make it degenerate to 1 row p row, shown in following formula:

Z＝[A ₁(w，t)A ₂(w，t)L A _i(w，t)L A _p(w，t)]。

Referring to Fig. 5, above-mentioned steps (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling: to being total to p the test link chaining object with logic cores bandwidth w and logic cores test duration t attribute among the dispatch matrix Z, with w * t is index, carry out the scalarization descending sort, upgrade dispatch matrix Z, as following formula:

Z＝[X ₁(w，t) X ₂(w，t)L X _i(w，t)L X _p(w，t)]；

Under given total test bandwidth W, find the solution decision variable b according to following formula _i, in the formula, α is a regulatory factor,

$\underset{b_i}{\min }\underset{i=1}{\overset{p}{\mathrm{\&Sigma;}}}[\mathrm{\&alpha;}\&CenterDot;i-X_i\left(w\right)]\&CenterDot;b_i$

$s.t.\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{X}_i\left(w\right)\&CenterDot;b_i\&le;W,b_i\&Element;\left\{\mathrm{0,1}\right\};$

According to the decision variable b that tries to achieve, preferentially choose and line number

Individual first test link chaining object, in the enterprising row labels of dispatch matrix Z, the call number of correspondence is set up total test bandwidth (W) that length is R-total test duration (T) two dimension ordering chained list as node, data element in the chained list is pressed the logic cores test duration t attribute descending sort of corresponding test link chaining object, and is that this R corresponding test link chaining object increases by two couples of rectangular coordinate information (x ₁, y ₁) and (x ₂, y ₂), its relation as following formula:

$\left\{\begin{array}{c}{x}_{2L\left(i\right)}=x_{1i}+t_i\\ y_{2L\left(i\right)}=y_{1i}+X_i\left(w\right)\end{array}\right.\left\{\begin{array}{c}{x}_{1L\left(i\right)}=0\\ y_{1L\left(i\right)}=y_{2[L\left(i\right)-1]}\end{array}\right.\left\{\begin{array}{c}{x}_{1L\left(1\right)}=0\\ y_{1L\left(1\right)}=0\end{array}\right.,$

Wherein L (i) expression chain table index i is to the mapping of dispatch matrix Z call number, and four control variable e, l, u, v are set up in inside simultaneously, and e is used for being recorded in the corresponding minimum x of chained list ₂Chain table index, l be that chained list length, u are used to write down available idle bandwidth and use formula

Calculate, v is used for writing down the transverse axis position of idle bandwidth at rectangular coordinate; Under the initial situation, e is the chained list tail, l=R, u=W-y _{2L (R)}, v=0, will finish the ordering of the total test duration T two dimension of all total test bandwidth of residue W-according to following steps subsequently:

1. on dispatch matrix Z, in the unlabelled test link chaining object, seek the test link chaining object X of logic cores bandwidth w less than control variable u by the call number increment _fIn case, find to stop at once seeking, in the enterprising row labels of dispatch matrix Z, call number f is appended to the afterbody of two dimension ordering chained list, for this test link chaining object increase by two pairs of rectangular coordinate information (0, u-X _fAnd (X (w)) _f(t), W), upgrade control variable e, l, u, v; As l＞R, R is updated to l; Whether find all execution in step 2..

2. seek next X by 1. identical mode _fAnd mark, for this test link chaining object increase by two pairs of rectangular coordinate information (0, y _1f) and (X _f(t), y _1f+ X _f(w)), if e not at the chained list tail, then tightly is inserted in call number f after the chain table position e, at this moment, if x _{2L (e)}＞x _{2L (e+1)}, y then _1f=y _{2L (e)}, use interim method L simultaneously ^-1(f) upgrade e, otherwise y _1f=y _{2L (e)}+ u-X _f(w), and not upgrade e; If e at the chained list tail, then tightly is inserted in call number f before the chain table position e, y _1f=y _{2L (e-1)}, use interim method L simultaneously ^-1(f) upgrade e, execution in step 2. subsequently; If again can't find such X _fAnd dispatch matrix is not labeled full, then upgrades e (non-interim method), l, u, v and R, enters step more 3.; If dispatch matrix is labeled full, then finish sequencer procedure.

3. u is revised, if e at linked list head, then correction formula is u=y _{1L (e+1)}If e is in chained list, then correction formula is u=y _{1L (e+1)}-y _{2L (e-1)}If e is at the chained list tail, then correction formula is u=W-y _{2L (e-1)}, continue execution in step 4..

4. seek next X by 1. identical mode _fAnd mark, deposit call number f in chain table position e, and be that this test link chaining object increases by two couples of rectangular coordinate information (v, y _1f) and (v+X _f(t), y _1f+ X _f(w)), if e at linked list head, y then _1f=0; If e is at chained list tail, then y _1f=W-X _f(w); If e in chained list, at this moment, if x _{2L (e-1)}＞x _{2L (e+1)}, y then _1f=y _{2L (e-1)}, otherwise, y _1f=y _{1L (e+1)}-X _f(w); If there is no such X _fAnd dispatch matrix is not labeled full, and then no matter whether deletion of node e find, and is full as long as dispatch matrix is not labeled, and then upgrades e (non-interim method), l, v and R, enters step more 3., otherwise finishes sequencer procedure.

Referring to Fig. 6, above-mentioned steps (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α) and is: always test the dual traversal of bandwidth-regulatory factor (W-α) and obtain all test dispatching results by dispatch matrix Z always being tested bandwidth-total test duration (W-T) two-dimentional scheduling; Its reason is: when always testing bandwidth-total test duration (W-T) two dimension ordering, be used to produce the specific formula of first test link chaining object, its regulatory factor α only exists

Or

(look the α that solves by following formula _kWhether contain 0 and decide) that first selection result is produced is different, this

Or The end points in individual interval can be found the solution acquisition by following formula,

${\mathrm{\&alpha;}}_k=\frac{X_i\left(w\right)-X_j\left(w\right)}{i-j}i=1\mathrm{Kp},j=1\mathrm{Kp},i\&NotEqual;j,k=1\mathrm{<figure-callout\; id="2"\; label="K\; C\; p"\; filenames="HSA00000282494700011.png"\; state="\{\{state\}\}">K</figure-callout>}{C}_p^{}{}_2^{},$

In addition, the effective range of always testing bandwidth (W) is for from MAX (X _i(w)) to SUM (X _i(w)) all integers.Therefore, limited total test bandwidth (W) and regulatory factor (α) have constituted the dual traversal of total test bandwidth-regulatory factor (W-α), and its concrete dual traversal mode is: always test bandwidth (W) from MAX (X _i(w)) beginning adds 1 one by one until SUM (X _i(w)) till, on each value, regulatory factor α chooses each interval intermediate value one by one, for last interval

Then with As selected value; After obtaining all test dispatching results, by earlier total test duration (T) again the priority of idleness (IR) last test and line number (R) the test dispatching result is sorted, thereby determine final unique test dispatching result; The information that comprises among this test dispatching result has final total test bandwidth (W), final total test duration (T), final idleness (IR), final test and line number (R) and final logic cores test dispatching strategy.

Claims (7)

1. a multi-stage sequencing algorithm applies to the method for the embedded logic cores test dispatching of SOC (system on a chip), read in by the SoC file, the ordering degree of depth and priority criteria are set, utilization multi-stage sequencing algorithm, obtain optimum logic cores test dispatching result on the logic cores test dispatching, it is characterized in that operation steps is: (1) dispatch matrix Z sets up and initialization, (2) the capable expansion of dispatch matrix Z, (3) the capable contraction of dispatch matrix Z, (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling, (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α) and (6) report generation; Described step (1) dispatch matrix Z sets up with initialization: read the SoC file, this document meets the SoC file layout that ITC ' 02 (International TestConference 2002) formulates, therefrom obtain the logic cores sum p among the SoC, initialization dispatch matrix Z, element among the dispatch matrix Z is a test link chaining object, and this object has two dimension attributes of logic cores bandwidth w and logic cores test duration t; The capable expansion of described step (2) dispatch matrix Z is: by setting test link chaining ordering degree of depth m, each logic cores is formed m test link chaining object by specific formula, thus row expansion dispatch matrix Z; The capable contraction of described step (3) dispatch matrix Z is: by priority criteria is set, m test link chaining object carried out scalarization ordering by priority criteria respectively listing, obtain preferential test link chaining object, abandon all the other test link chaining objects, thereby row shrinks dispatch matrix Z; Described step (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling: under given total test bandwidth and regulatory factor α condition, common p test link chaining object among the dispatch matrix Z of row contraction always tested bandwidth-total test duration (W-T) two dimension ordering obtain total test duration T, test and results such as line number R, idleness IR and logic cores test dispatching strategy; Described step (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α): obtain all effectively total test bandwidth W value and regulatory factor α values from the dispatch matrix Z that row shrinks, always test the dual traversal of bandwidth-regulatory factor (W-α) by dispatch matrix Z always being tested bandwidth-total test duration (W-T) two-dimentional scheduling, thereby obtain all results, and by first total test duration T again the priority of idleness IR last test and line number R the result is sorted, thereby determine final unique test result; Described step (6) report generates: above institute is each details in the operating process and the result forms text respectively and figure is reported in steps.

2. multi-stage sequencing algorithm according to claim 1 applies to the method for the embedded logic cores test dispatching of SOC (system on a chip), it is characterized in that it is to discern the SoC file layout of being stipulated by ITC ' 02 automatically that described step (1) dispatch matrix Z sets up with initialization, obtain logic cores sum p, foundation has the tables of data of p list item in inside, each list item of this tables of data carries out related with each row of dispatch matrix Z that are initially 0 row p row, each list item all contains the every important information that extracts from the SoC file: input port is counted In, output port is counted Out, internal scan chain is counted n, each bar scan chain length { s ₁.., s _n, and test pattern figurate number tp; In addition, described dispatch matrix Z foundation also has with initialization to be rejected automatically, incomplete important information is carried out the default ability of filling up automatically the information that does not meet file layout, can import SoC file or other SoC file to be scheduled of renewal repeatedly, import the SoC file, and no longer re-enter or close when input, any operation can not destroy tables of data and the dispatch matrix Z that portion has within it set up.

3. the method that the multi-stage sequencing algorithm is applied to the embedded logic cores test dispatching of SOC (system on a chip) according to claim 1, it is characterized in that the capable expansion of described step (2) dispatch matrix Z is according to the ordering degree of depth m that sets and logic cores sum p following specific formula to be circulated to find the solution

$\underset{a_{\mathrm{ij}},I_i,O_i}{\min }\underset{1\&le;i\&le;w}{\mathrm{\&Sigma;}}\left(\right|\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+I_i-\frac{\underset{1\&le;j\&le;n}{\mathrm{\&Sigma;}}{s}_j+\mathrm{In}}{w}|+|\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+O_i-\frac{\underset{1\&le;j\&le;n}{\mathrm{\&Sigma;}}{s}_j+\mathrm{Out}}{w}\left|\right)$

$s.t.\underset{i=1}{\overset{w}{\mathrm{\&Sigma;}}}{a}_{\mathrm{ij}}=1,a_{\mathrm{ij}}\&Element;\left\{\mathrm{0,1}\right\}$

$\underset{i=1}{\overset{w}{\mathrm{\&Sigma;}}}{I}_i=\mathrm{In},\underset{i=1}{\overset{w}{\mathrm{\&Sigma;}}}{O}_i=\mathrm{Out},I_i,O_i\&Element;Z^{+};$

Detailed process is: obtain the information in each list item from the tables of data with p list item successively, the above specific formula of substitution is found the solution decision variable a _Ij, I _i, O _iAnd same list item carried out finding the solution for m time, when finding the solution at every turn, logic cores bandwidth w equals number of times, end loop is found the solution the back and is obtained m * p test link chaining object, logic cores bandwidth w attribute in each test link chaining object is determined in solution procedure, and another attribute logic cores test duration t is calculated by following formula

$\{1+\max [\underset{1\&le;i\&le;w}{\max }(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+I_i),\underset{1\&le;i\&le;w}{\max }(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+O_i)\left]\right\}\&times;\mathrm{tp}$

$+\min \left[\max (\underset{1\&le;i\&le;w}{\max }(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+I_i),\underset{1\&le;i\&le;w}{\max }(\underset{j=1}{\overset{n}{\mathrm{\&Sigma;}}}{s}_j{a}_{\mathrm{ij}}+O_i)\right];$

According to dispatch matrix Z capable the expand to m capable p row of this m * p test link chaining object, shown in following formula to being initially 0 row p row:

$Z=\left[\begin{array}{cccccc}{A}_{11}(w_1,t_1)& A_{21}(w_1,t_1)& L& A_{i1}(w_1,t_1)& L& A_{p1}(w_1,t_1)\\ A_{12}(w_2,t_2)& A_{22}(w_2,t_2)& L& A_{i2}(w_2,t_2)& L& A_{p2}(w_2,t_2)\\ M& M& M& M& M& M\\ A_{1m}(w_m,t_m)& A_{2m}(w_m,t_m)& L& A_{\mathrm{im}}(w_m,t_m)& L& A_{\mathrm{pm}}(w_m,t_m)\end{array}\right];$

Simultaneously, the capable expansion of described dispatch matrix Z can be set ordering degree of depth m repeatedly to obtain new dispatch matrix Z.

4. multi-stage sequencing algorithm according to claim 1 applies to the method for the embedded logic cores test dispatching of SOC (system on a chip), it is characterized in that the capable contraction of described step (3) dispatch matrix Z provides the priority criteria function f (w that can set up on their own, t), this function with the logic cores bandwidth w of test link chaining object and logic cores test duration t attribute as parameter; According to the priority criteria function that sets up on their own dispatch matrix Z is reset with the ascending order that the unit of classifying as carries out scalarization, when the priority criteria function is not set, then according to default priority criteria function f (w, t)=and w * t * (w+t) dispatch matrix Z is reset with the ascending order that the unit of classifying as carries out scalarization, it is capable to m that dispatch matrix Z after resetting is abandoned the 2nd row, make it degenerate to 1 row p row, shown in following formula:

Z＝[A ₁(w，t) A ₂(w，t)L A _i(w，t)L A _p(w，t)]。

5. multi-stage sequencing algorithm according to claim 1 applies to the method for the embedded logic cores test dispatching of SOC (system on a chip), it is characterized in that it is to being total to p the test link chaining object with logic cores bandwidth w and logic cores test duration t attribute among the dispatch matrix Z that described step (4) dispatch matrix Z always tests bandwidth-total test duration (W-T) two-dimentional scheduling, with w * t is index, carry out the scalarization descending sort, upgrade dispatch matrix Z, as following formula:

Z＝[X ₁(w，t)X ₂(w，t)L X _i(w，t)L X _p(w，t)]；

Under given total test bandwidth W, find the solution decision variable b according to following formula _i, in the formula, α is a regulatory factor,

$\underset{b_i}{\min }\underset{i=1}{\overset{p}{\mathrm{\&Sigma;}}}[\mathrm{\&alpha;}\&CenterDot;i-X_i\left(w\right)]\&CenterDot;b_i$

$s.t.\underset{i=1}{\overset{n}{\mathrm{\&Sigma;}}}{X}_i\left(w\right)\&CenterDot;b_i\&le;W,b_i\&Element;\left\{\mathrm{0,1}\right\};$

According to the decision variable b that tries to achieve, preferentially choose and line number

Individual first test link chaining object, in the enterprising row labels of dispatch matrix Z, the call number of correspondence is set up the total test duration T two dimension of the total test bandwidth W-ordering chained list that length is R as node, data element in the chained list is pressed the logic cores test duration t attribute descending sort of corresponding test link chaining object, and is that this R corresponding test link chaining object increases by two couples of rectangular coordinate information (x ₁, y ₁) and (x ₂, y ₂), its relation as following formula:

$\left\{\begin{array}{c}{x}_{2L\left(i\right)}=x_{1i}+t_i\\ y_{2L\left(i\right)}=y_{1i}+X_i\left(w\right)\end{array}\right.\left\{\begin{array}{c}{x}_{1L\left(i\right)}=0\\ y_{1L\left(i\right)}=y_{2[L\left(i\right)-1]}\end{array}\right.\left\{\begin{array}{c}{x}_{1L\left(1\right)}=0\\ y_{1L\left(1\right)}=0\end{array}\right.,$

Wherein L (i) expression chain table index i is to the mapping of dispatch matrix Z call number, and four control variable e, l, u, v are set up in inside simultaneously, and e is used for being recorded in the corresponding minimum x of chained list ₂Chain table index, l be that chained list length, u are used to write down available idle bandwidth and use formula

Calculate, v is used for writing down the transverse axis position of idle bandwidth at rectangular coordinate; Under the initial situation, e is the chained list tail, l=R, u=W-y _{2L (R)}, v=0, will finish the ordering of the total test duration T two dimension of all total test bandwidth of residue W-according to following steps subsequently:

1. on dispatch matrix Z, in the unlabelled test link chaining object, seek the test link chaining object X of logic cores bandwidth w less than control variable u by the call number increment _fIn case, find to stop at once seeking, in the enterprising row labels of dispatch matrix Z, call number f is appended to the afterbody of two dimension ordering chained list, for this test link chaining object increase by two pairs of rectangular coordinate information (0, u-X _fAnd (X (w)) _f(t), W), upgrade control variable e, l, u, v; As l＞R, R is updated to l; Whether find all execution in step 2..

2. seek next X by 1. identical mode _fAnd mark, for this test link chaining object increase by two pairs of rectangular coordinate information (0, y _1f) and (X _f(t), y _1f+ X _f(w)), if e not at the chained list tail, then tightly is inserted in call number f after the chain table position e, at this moment, if x _{2L (e)}＞x _{2L (e+1)}, y then _1f=y _{2L (e)}, use interim method L simultaneously ^-1(f) upgrade e, otherwise y _1f=y _{2L (e)}+ u-X _f(w), and not upgrade e; If e at the chained list tail, then tightly is inserted in call number f before the chain table position e, y _1f=y _{2L (e-1)}, use interim method L simultaneously ^-1(f) upgrade e, execution in step 2. subsequently; If again can't find such X _fAnd dispatch matrix is not labeled full, then upgrades e (non-interim method), l, u, v and R, enters step more 3.; If dispatch matrix is labeled full, then finish sequencer procedure.

3. u is revised, if e at linked list head, then correction formula is u=y _{1L (e+1)}If e is in chained list, then correction formula is u=y _{1L (e+1)}-y _{2L (e-1)}If e is at the chained list tail, then correction formula is u=W-y _{2L (e-1)}, continue execution in step 4..

4. seek next X by 1. identical mode _fAnd mark, deposit call number f in chain table position e, and be that this test link chaining object increases by two couples of rectangular coordinate information (v, y _1f) and (v+X _f(t), y _1f+ X _f(w)), if e at linked list head, y then _1f=0; If e is at chained list tail, then y _1f=W-X _f(w); If e in chained list, at this moment, if x _{2L (e-1)}＞x _{2L (e+1)}, y then _1f=y _{2L (e-1)}, otherwise, y _1f=y _{1L (e+1)}-X _f(w); If there is no such X _fAnd dispatch matrix is not labeled full, and then no matter whether deletion of node e find, and is full as long as dispatch matrix is not labeled, and then upgrades e (non-interim method), l, v and R, enters step more 3., otherwise finishes sequencer procedure.

6. multi-stage sequencing algorithm according to claim 1 applies to the method for the embedded logic cores test dispatching of SOC (system on a chip), it is characterized in that it is always to test the dual traversal of bandwidth-regulatory factor (W-α) and obtain all test dispatching results by dispatch matrix Z always being tested bandwidth-total test duration (W-T) two-dimentional scheduling that described step (5) dispatch matrix Z always tests the dual traversal of bandwidth-regulatory factor (W-α); Its reason is: when always testing bandwidth-total test duration (W-T) two dimension ordering, be used to produce the specific formula of first test link chaining object, its regulatory factor α only exists

Or

(look the α that solves by following formula _kWhether contain 0 and decide) that first selection result is produced is different, this

Or

The end points in individual interval can be found the solution acquisition by following formula,

${\mathrm{\&alpha;}}_k=\frac{X_i\left(w\right)-X_j\left(w\right)}{i-j}i=1\mathrm{Kp},j=1\mathrm{Kp},i\&NotEqual;j,k=1K{C}_p^2,$

In addition, the effective range of always testing bandwidth (W) is for from MAX (X _i(w)) to SUM (X _i(w)) all integers.Therefore, limited total test bandwidth (W) and regulatory factor (α) have constituted the dual traversal of total test bandwidth-regulatory factor (W-α), and its concrete dual traversal mode is: always test bandwidth (W) from MAX (X _i(w)) beginning adds 1 one by one until SUM (X _i(w)) till, on each value, regulatory factor α chooses each interval intermediate value one by one, for last interval

Then with

As selected value; After obtaining all test dispatching results, by earlier total test duration (T) again the priority of idleness (IR) last test and line number (R) the test dispatching result is sorted, thereby determine final unique test dispatching result; The information that comprises among this test dispatching result has final total test bandwidth (W), final total test duration (T), final idleness (IR), final test and line number (R) and final logic cores test dispatching strategy.

7. the method that the multi-stage sequencing algorithm is applied to the embedded logic cores test dispatching of SOC (system on a chip) according to claim 1, it is characterized in that described step (6) report is generated as each details and the result of all other steps in operating process and forms text and figure report respectively, text entry is carried out in the operating process that is each step, indicates step source, operation name and service data in the record; The text report generates and figure report generation for the operating result of each step carries out.

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