CN102005914B - Power factor conversion control device - Google Patents
Power factor conversion control device Download PDFInfo
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- CN102005914B CN102005914B CN200910172030XA CN200910172030A CN102005914B CN 102005914 B CN102005914 B CN 102005914B CN 200910172030X A CN200910172030X A CN 200910172030XA CN 200910172030 A CN200910172030 A CN 200910172030A CN 102005914 B CN102005914 B CN 102005914B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
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Abstract
The invention provides a power factor conversion control device which is used for receiving input voltage and controlling current flowing by an inductor by turning on and turning off a transfer switch for generating output voltage. The power factor conversion control device comprises a switching control circuit for generating switch control voltage according to the input voltage. The switching control circuit comprises a ramp voltage generator and a control signal generator. When the transfer switch is turned on, the ramp voltage generator can generate ramp voltage with fixed slope according to the input voltage, and the voltage at the initial point of the ramp voltage can be changed according to the size of the input voltage. When the transfer switch is turned on, the control signal generator can disable the switch control voltage by comparing the ramp voltage with shared voltage so as to turn off the transfer switch.
Description
Technical field
The present invention relates to a kind of power factor conversion control device, relate in particular to a kind of control switching circuit of power factor conversion control device.
Background technology
At first please refer to Fig. 1, the schematic diagram that Fig. 1 is existing power factor conversion control device 100.In power factor conversion control device 100, the input voltage ACV of interchange produces input voltage VIN after bridge rectifier 110 rectifications.And during the transistor switch M1 conducting in power factor conversion control device 100, input voltage VIN is charged to inductance L 1.And, when transistor switch M1 closes, 1 of inductance L is discharged to capacitor C 1 via diode D1.After the charge discharge in inductance L 1, transistor switch M1 conducting again, and carry out the action of the charging to inductance L 1 in next cycle.
Power factor conversion control device 100 utilizes the above-mentioned mode that capacitor C 1 is charged that repeats, and produces output voltage VO.Yet, because transistor switch M1 and diode D1 exist parasitic capacitance (being equivalent to capacitor C P).Therefore, in the process of being discharged in inductance L 1, inductance L 1 and capacitor C P will there will be the phenomenon of resonance.The phenomenon of this resonance will make the part electric charge in capacitor C P recharge to input voltage VIN, and affects the process that input voltage VIN is charged to inductance L 1, and the distortion of generation current.
Above-mentioned resonance phenomena can be known by inference by formula, please coordinate Fig. 1, and wherein 1 current flowing of inductance L and the relational expression of time are as shown in the formula shown in (1):
Can be pushed away the maximum I of the electric current of the inductance L of flowing through 1 by formula (1)
LMax is suc as formula shown in (2):
If coordinate the ON time of transistor switch M1, formula (2) can be rewritten into as shown in the formula shown in (3):
Formula (3) is transplanted after computing, and to obtain formula (4) as follows:
Then please coordinate with reference to Fig. 2 A and Fig. 2 B the electric current I that Fig. 2 A is input voltage VIN and the inductance L 1 of flowing through
LGraph of a relation, the conducting closed condition that Fig. 2 B is transistor switch M1 with flow through the electric current I of inductance L 1
LGraph of a relation.In Fig. 2 A, when input voltage VIN levels off to zero (voltage VIN is positioned at zero ecotone 210), by formula (4), can learn that transistor switch M1 will need the ON time Ton grown could meet the demand that enough electric currents are provided very much.Again from Fig. 2 B, due to the resonance phenomena of inductance L 1 with capacitor C P, electric current I
LCan produce reverse electric current I
neg, this need to utilize be controlled during voltage Vg carrys out the conducting ton in period of conducting at transistor switch M1, additionally allots one section compensation tneg in period to supply (transistor switch M1 period during toff for closing).And how to allocate enough conducting ton in period, be the important topic of the staggered distortion of offset zero.
Summary of the invention
The invention provides a kind of power factor conversion control device, effectively reduce and level off to zero the time zero distortion (zero crossing distortion) that interlocks produced when input voltage.
The present invention proposes a kind of power factor conversion control device, this power factor conversion control device has at least one diverter switch and at least one inductance, in order to receive the electric current that input voltage conducting and closing control by diverter switch flow through inductance, produces output voltage.Power factor conversion control device comprises according to input voltage to produce the control switching circuit of switch control voltage.Control switching circuit comprises ramp voltage generator and control signal generator.The ramp voltage generator, when the diverter switch conducting, produces the ramp voltage of fixed slope according to input voltage, wherein the starting point voltage of ramp voltage changes according to the size of input voltage.The control signal generator couples the ramp voltage generator.The control signal generator receives ramp voltage.When the diverter switch conducting, the control signal generator is according to relatively ramp voltage and common voltage come the forbidden energy switch control voltage to close diverter switch.
In an embodiment of the present invention, above-mentioned control signal generator comprises the common voltage generator, resets and hold comparator and SR bolt lock device.The common voltage generator receives the feedback voltage produced according to pressure-dividing output voltage, and according to feedback voltage and the first reference voltage to produce common voltage.The end comparator of resetting couples common voltage generator and ramp voltage generator, according to relatively common voltage and ramp voltage produce reset signal.The SR bolt lock device couples the end comparator of resetting, and has the end of replacement, sets end and output, and its replacement termination is received reset signal, and its output produces switch control voltage.
In an embodiment of the present invention, above-mentioned control signal generator also comprises the inductance energy comparator.The inductance energy comparator couples inductance and SR bolt lock device, and the inductance energy comparator also produces setting signal according to electric current and the reference lower limit value of the inductance of relatively flowing through.Wherein, setting signal is sent to the setting end of SR bolt lock device.
In an embodiment of the present invention, wherein, when above-mentioned setting signal activation, SR bolt lock device activation switch control voltage is with the conducting diverter switch.
In an embodiment of the present invention, above-mentioned control signal generator also comprises overcurrent comparator and or door.The overcurrent comparator couples diverter switch, according to the electric current of the diverter switch of relatively flowing through with the overcurrent reference value with the generation over-current signal.Or door is serially connected in the end comparator transmission reset signal of resetting between the approach of SR bolt lock device, there is first input end, the second input and output, its first input end receives over-current signal, and its second input receives reset signal, and its output is coupled to the replacement end of SR bolt lock device.
In an embodiment of the present invention, above-mentioned ramp voltage generator comprises multivoltage control circuit, electric capacity, current source and charge and discharge switch.The multivoltage control circuit produces the offset voltage of direct current according to input voltage, wherein the magnitude of voltage of offset voltage changes according to the size of input voltage.One end of electric capacity couples the multivoltage control circuit, and its other end produces ramp voltage.The other end of current source coupling capacitance, a charge and discharge switch is with electric capacity and connect.Charge and discharge switch is controlled by and discharges and recharges control signal.
In an embodiment of the present invention, above-mentioned ramp voltage generator also comprises buffer circuit.The input receiving key of buffer circuit is controlled voltage, and its output couples charge and discharge switch and discharges and recharges control signal to provide.
In an embodiment of the present invention, above-mentioned buffer circuit is negater circuit.
In an embodiment of the present invention, above-mentioned ramp voltage generator also comprises bleeder circuit, couples the multivoltage control circuit and in order to receive and the dividing potential drop input voltage, and transmits input voltage after dividing potential drop voltage control circuit at the most.
In an embodiment of the present invention, above-mentioned bleeder circuit comprises the first divider resistance and the second divider resistance.One termination of the first divider resistance is received input voltage, and its other end couples the multivoltage control circuit.The second divider resistance is serially connected between the other end and the first ground connection reference voltage of the first divider resistance.
In an embodiment of the present invention, above-mentioned ramp voltage generator also comprises that ratio-voltage produces circuit, multivoltage control circuit and comparison circuit.Ratio-voltage produce circuit according to a plurality of scalings of input voltage to produce a plurality of convergent-divergent input voltages, and select the convergent-divergent input voltage according to mode signal one of them for selecting voltage.The multivoltage control circuit couples ratio-voltage and produces circuit to receive selection voltage.Multivoltage control circuit foundation select voltage to produce the offset voltage of direct current.Wherein the magnitude of voltage of offset voltage changes according to the size of selecting voltage.Comparison circuit couples ratio-voltage and produces circuit, in order to receives and compare the 3rd reference voltage and convergent-divergent input voltage one of them with the generation mode signal.
In an embodiment of the present invention, above-mentioned ramp voltage generator also comprises reference signal generation circuit.Reference signal generation circuit couples comparison circuit, in order to produce the 3rd reference voltage.
In an embodiment of the present invention, above-mentioned ratio-voltage generation circuit comprises most bleeder circuits and selector.A plurality of bleeder circuits are the different scaling dividing potential drop input voltage of foundation respectively, and produces a plurality of convergent-divergent input voltages.Selector couples bleeder circuit and comparison circuit, in order to receive convergent-divergent input voltage and mode signal, and selects the convergent-divergent input voltage to produce offset voltage according to mode signal.
In an embodiment of the present invention, each above-mentioned bleeder circuit comprises the first divider resistance and the second divider resistance.One termination of the first divider resistance is received input voltage, and its other end couples selector.The second divider resistance is serially connected between the other end and the first ground connection reference voltage of the first divider resistance.
In an embodiment of the present invention, above-mentioned multivoltage control circuit comprises amplifier, the first resistance, the second resistance, the 3rd resistance and the 4th resistance.Amplifier has first input end, the second input and output, and the first resistance is serially connected between the first input end and output of amplifier.And the second resistance is serially connected between the first resistance and the second ground connection reference voltage.One end of the 3rd resistance is coupled in the second input of amplifier, and its other end receives input voltage.And the 4th resistance one end couples the second input of amplifier, its other end receives the second reference voltage.
Based on above-mentioned, the present invention utilizes the ramp voltage of fixed slope to compare with common voltage, and produces switch control voltage thus.And the magnitude of voltage of the starting point voltage by adjusting ramp voltage, reach the conducting of adjusting diverter switch and the time of closing, and effectively reaches the zero staggered distortion that reduces power factor conversion control device.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
The accompanying drawing explanation
The schematic diagram that Fig. 1 is existing power factor conversion control device 100.
The graph of a relation of the electric current I L that Fig. 2 A is input voltage VIN and the inductance L 1 of flowing through.
The graph of a relation of the electric current I L of the conducting closed condition that Fig. 2 B is transistor switch M1 and the inductance L 1 of flowing through.
The schematic diagram of the power factor conversion control device 300 that Fig. 3 is one embodiment of the invention.
One execution mode of the control switching circuit 310 that Fig. 4 is Fig. 3.
One execution mode of the ramp voltage generator 410 that Fig. 5 is Fig. 4.
The graph of a relation of the switch control voltage that correspondence that Fig. 6 produces by the ramp voltage under offset voltages different in the embodiment of the present invention.
Fig. 7,8 is respectively the schematic diagram of the part circuit of two kinds of different ramp generating circuits 410.
The detailed circuit schematic that Fig. 9 is Fig. 8.
The schematic diagram of the execution mode of the multivoltage control circuit 510 that Figure 10 is the embodiment of the present invention.
Main description of reference numerals:
100,300: power factor conversion control device; 110: bridge rectifier;
210: zero ecotone; 310: control switching circuit;
410: the ramp voltage generator; 420: the control signal generator;
421: the common voltage generator; 422: the end comparator of resetting;
The 423:SR bolt lock device; 424: the inductance energy comparator;
425: the overcurrent comparator; 426: or door;
510: the multivoltage control circuit; 710: bleeder circuit;
810: ratio-voltage produces circuit; 820: comparison circuit;
830: reference signal generation circuit; 811: select circuit;
VREF2: reference lower limit value; VREF1, VREF4: reference voltage;
VREF3: overcurrent reference value; T1: transformer;
OC: over-current signal; RST: reset signal;
R: the end of resetting; S: set end;
Q: output; Voffset, Voffset1～3: offset voltage;
MOD: mode signal; VINri: select voltage;
VCOM: common voltage; VRAMP, VRAMP1～3: ramp voltage;
VS: overcurrent detecting voltage; VF: feedback voltage;
Rf1、Rf2、RS、RA1、RA2、RB1、RB2、RC1、RC2、RD1、RD2、RMa1、
RMa2, RMb1, RMb2: resistance;
VD: inductance detecting voltage; OP1: amplifier;
Vg, Vg1～Vg3: switch control voltage; T1: transformer;
VIN, ACV, VINr1, VINr2: input voltage;
L1: inductance; M1, MS: switch;
D1: diode; C1, CP, Cr: electric capacity;
VO: output voltage; I
L, I
neg: electric current;
Tneg, toff, ton: period; IS: current source;
BUF1: buffer circuit; GND: ground connection reference voltage.
Embodiment
At first please refer to Fig. 3, the schematic diagram of the power factor conversion control device 300 that Fig. 3 is one embodiment of the invention.Have by the diverter switch M1 of transistor constructiveness in power factor conversion control device 300 and be configured in the inductance L 1 in transformer T1.Power factor conversion control device 300 receives the electric current I that input voltage VIN conducting and closing control by diverter switch M1 flow through inductance L 1
LProduce output voltage VO.Power factor conversion control device 300 comprises control switching circuit 310, control switching circuit 310 according to input voltage VIN to produce switch control voltage Vg.Control switching circuit 310 also receives the electric current I that flows through inductance L 1 according to detecting
LThe inductance detecting voltage VD produced, and output voltage VO is by the feedback voltage VF of divider resistance Rf1, the generation of Rf2 dividing potential drop.In addition, control switching circuit 310 receives the overcurrent detecting voltage VS (product of the electric current of the diverter switch of wherein flowing through M1 and resistance R S resistance equals the magnitude of voltage of overcurrent detecting voltage VS) of the electric current generation of detecting the diverter switch M1 that flows through.
About the execution mode of control switching circuit 310, referring to Fig. 3 and Fig. 4, an execution mode of the control switching circuit 310 that wherein Fig. 4 is Fig. 3.Control switching circuit 310 comprises ramp voltage generator 410 and control signal generator 420, is used for producing the switch control voltage Vg that controls diverter switch M1 conducting or close.Ramp voltage generator 410 receives input voltage VIN and switch control voltage Vg.Ramp voltage generator 410 judges that by received switch control voltage Vg diverter switch M1 is in conducting state or closed condition.The diverter switch M1 of take is that the N-type transistor is example, and when switch control voltage Vg is the logic high levle, diverter switch M1 is in conducting state.Contrary, when switch control voltage Vg is the logic low level, diverter switch M1 is in closed condition (and if diverter switch M1 while being the P transistor npn npn, the judgment mode of the diverter switch M1 state mode in above-mentioned is contrary).
Once ramp voltage generator 410 is judged the state that diverter switch M1 is conducting, 410 of ramp voltage generators produce ramp voltage VRAMP according to input voltage VIN.It is worth mentioning that, the slope of ramp voltage VRAMP is fixed, and the starting point voltage of ramp voltage VRAMP is that the size according to input voltage VIN changes.
In the present embodiment, control signal generator 420 comprises common voltage generator 421, resets and hold comparator 422, SR bolt lock device 423, inductance energy comparator 424, overcurrent comparator 425 and or door 426.Wherein, common voltage generator 421 receives the feedback voltage VF produced according to pressure-dividing output voltage VO, and according to feedback voltage VF and reference voltage VREF1 to produce common voltage VCOM.Common voltage generator 421 can utilize operational amplifier to implement, and, when the output voltage VO of power factor conversion control device 200 is stablized, the common voltage VCOM that common voltage generator 421 produces is also that a galvanic current is pressed.
422 of the comparators of end of resetting are coupled to common voltage generator 421 and ramp voltage generator 410.The end comparator 422 of resetting compares common voltage VCOM and ramp voltage VRAMP produces reset signal RST.In the present embodiment, this reset signal RST sees through or door 426 is sent to SR bolt lock device 423.When the ramp voltage VRAMP that holds comparator 422 to receive when resetting is less than common voltage VCOM, it is for example the reset signal RST of logic high levle that the end comparator 422 of resetting produces, the reset signal RST of this logic high levle is sent to the replacement end R of SR bolt lock device 423, by SR bolt lock device 423 its switch control voltage Vg produced at output Q that resets, can be the logic low level.Relative, now diverter switch M1 (being for example the construction of N-type transistor institute) is closed.
In addition, 424 of inductance energy comparators are used for receiving inductance detecting voltage VD, and inductance energy comparator 424 couples inductance L 1 and SR bolt lock device 423.Inductance energy comparator 424 compares this inductance detecting voltage VD and reference lower limit value VREF2, learns the current status in inductance L 1.When inductance detecting voltage VD is less than reference lower limit value VREF2, mean that the discharging action of inductance L 1 finishes.At the same time, it is for example the setting signal of logic high levle that inductance energy comparator 424 produces, and this setting signal is sent to the setting end S of SR bolt lock device 423.And, after SR bolt lock device 423 receives the setting signal of this logic high levle, setting the switch control voltage Vg that its output Q exports can be the logic high levle, and the M1 of conducting diverter switch thus.
425 of overcurrent comparators couple diverter switch M1.Overcurrent comparator 425 receives overcurrent detecting voltage VS and overcurrent reference value VREF3.Overcurrent comparator 425 utilizes the result that compares overcurrent detecting voltage VS and overcurrent reference value VREF3 to produce over-current signal OC.That is to say, when the electric current of the diverter switch M1 that flows through excessive, while making overcurrent detecting voltage VS be greater than pre-set overcurrent reference value VREF3, it is for example the over-current signal OC of logic high levle that overcurrent comparator 425 produces, and sees through or door 426 transmits the replacement end R of over-current signal OC to SR bolt lock devices 423.After the SR bolt lock device has received this over-current signal OC, just at its output Q, producing is for example the switch control voltage Vg of logic low level, and then closes diverter switch M1.
At this, please pay special attention to, the above-mentioned logic voltage level about each signal (reset signal RST, over-current signal OC and switch control voltage Vg) is all an example, is not limited to the present invention.Those skilled in the art are in the epistemic losic circuit design, and high levle action (low active) or low level action (lowactive) can be decided in its sole discretion and change easily by the designer.Example SR bolt lock device 423 described above also can be designed as when its end R that resets receives the signal of logic low level, and the switch control voltage Vg that its output of just resetting is exported is the logic low level.
Then please refer to Fig. 5, an execution mode of the ramp voltage generator 410 that Fig. 5 is Fig. 4.In the present embodiment, ramp voltage generator 410 comprises multivoltage control circuit 510, capacitor C r, current source IS, charge and discharge switch MS and buffer circuit BUF1.Multivoltage control circuit 510 produces the offset voltage Voffset of direct current according to input voltage VIN, the magnitude of voltage of offset voltage Voffset wherein changes according to the size of input voltage VIN.Capacitor C r is serially connected in 510 of current source IS and multivoltage control circuits, and charge and discharge switch MS and capacitor C r also connect.In addition, charge and discharge switch MS is controlled by the control signal that discharges and recharges of buffer circuit BUF1 output, and voltage Vg is controlled in the input of buffer circuit BUF1 receiving key.At this, buffer circuit BUF1 also can utilize the negater circuit in logical circuit to implement.The designer can select buffer circuit or negater circuit according to the corresponding relation of the voltage quasi position of the level that discharges and recharges control signal of controlling charge and discharge switch MS and switch control voltage Vg.
When diverter switch M1 conducting, discharge and recharge control signal and control charge and discharge switch MS conducting, and ramp voltage VRAMP be take offset voltage Voffset as fixing slope rising of starting point foundation.This fixing slope can be decided by the size of current of current source IS.
Below please refer to Fig. 6, the graph of a relation of the switch control voltage that correspondence that Fig. 6 produces by the ramp voltage under offset voltages different in the embodiment of the present invention.Wherein, the starting point voltage of ramp voltage VRAMP1 is offset voltage Voffset1, and the starting point voltage of ramp voltage VRAMP2 is offset voltage Voffset2, and the starting point voltage of ramp voltage VRAMP3 is offset voltage Voffset3.When ramp voltage VRAMP1～3 are less than common voltage VCOM, corresponding switch control voltage Vg1～Vg3 is respectively logic level that can conducting diverter switch M1, is for example the logic high levle.Once ramp voltage VRAMP1～3 equal the moment of common voltage VCOM, corresponding switch control voltage Vg1～Vg3 respectively transition be the logic low level, and close diverter switch M1.
Can clearly be found by Fig. 6, by changing the starting point voltage (offset voltage) of ramp voltage, can reach the purpose of controlling diverter switch M1 ON time.In the present embodiment, the ramp voltage that offset voltage is higher, its ON time of the corresponding diverter switch M1 produced shorter.
In the ramp generating circuit 410 shown in Fig. 5, multivoltage control circuit 510 directly receives input voltage VIN and is processed.In fact, multivoltage control circuit 510 also can not need directly to receive and may the higher input voltage VIN of voltage quasi position be processed.Below please refer to Fig. 7 and Fig. 8, Fig. 7,8 is respectively the schematic diagram of the part circuit of two kinds of different ramp generating circuits 410.In Fig. 7, also comprise bleeder circuit 710 in ramp generating circuit 410.Bleeder circuit 710 couples multivoltage control circuit 510, and receives input voltage VIN.Bleeder circuit 710 comprises divider resistance RA1 and the divider resistance RA2 of serial connection.The termination of divider resistance RA1 is received input voltage VIN, and its other end couples multivoltage control circuit 510, and produces the input voltage VIN r1 of dividing potential drop.Divider resistance RA2 is serially connected between the other end and ground connection reference voltage GND of divider resistance RA1.
In addition, comprise that at Fig. 8 ratio-voltage produces circuit 810, comparison circuit 820 and reference signal generation circuit 830.Ratio-voltage generation circuit 810 produces a plurality of convergent-divergent input voltages according to a plurality of scalings of input voltage VIN.Ratio-voltage produce that circuit 810 also selects the convergent-divergent input voltage according to mode signal MOD one of them for selecting voltage VINri.
The execution mode that produces circuit 810 about the ratio-voltage shown in Fig. 8 please refer to shown in Fig. 9, the detailed circuit schematic that Fig. 9 is Fig. 8.Ratio-voltage produces circuit 810 and comprises the three component volt circuits that consist of divider resistance RB1, RB2 and divider resistance RC1, RC2 and divider resistance RD1, RD2.Divider resistance RB1 wherein and divider resistance RB2 are serially connected between input voltage VIN and ground connection reference voltage GND.(same, divider resistance RC1 and divider resistance RC2 are serially connected between input voltage VIN and ground connection reference voltage GND, and divider resistance RD1 and divider resistance RD2 are serially connected between input voltage VIN and ground connection reference voltage GND).Three component volt circuits according to the dividing potential drop input voltage VIN to produce the convergent-divergent input voltage.One of them convergent-divergent input voltage VIN ri is sent to the comparison circuit 820 by the comparator construction.Comparison circuit 820 is another receives the reference voltage VREF4 that reference signal generation circuit 830 produces, and comparison reference voltage VREF4 and select voltage VINri to produce mode signal MOD.
Mode signal MOD is back to ratio-voltage and produces the selection circuit 811 in circuit 810.Select 811, circuit to select one of them the convergent-divergent input voltage VIN r2 in a plurality of convergent-divergent input voltages according to mode signal MOD, be sent to multivoltage control circuit 510.
Note that at this it is only an example that above-mentioned bleeder circuit is three groups.At this, the group number of bleeder circuit is restriction not, and the demand that the designer can use according to reality, arrange arbitrarily the bleeder circuits of organizing more.And produce thus a plurality of convergent-divergent input voltages.
Then please refer to Figure 10, the schematic diagram of the execution mode of the multivoltage control circuit 510 that Figure 10 is the embodiment of the present invention.In the present embodiment, multivoltage control circuit 510 comprises amplifier OP1 and resistance R Ma1, RMa2, RMb1, RMb2.Amplifier OP1 has first input end, the second input and output.Resistance R Mb2 is serially connected between the first input end and output of amplifier OP1, and resistance R Mb1 is serially connected between resistance R Mb2 and ground connection reference voltage GND.The end of resistance R Ma1 is coupled in the second input of amplifier OP1, and its other end receives input voltage VIN.The end of resistance R Ma2 couples the second input of amplifier OP1, and its other end receives reference voltage VREF4.In addition, the other end of resistance R Ma1 also can receive the input voltage VIN r1 after dividing potential drop as shown in Figure 7, or also can receive convergent-divergent input voltage VIN r2 as shown in Figure 8.
In sum, the present invention produces the offset voltage of the different levels that the size according to input voltage changes by the multivoltage control circuit.And provide the ramp voltage generator these offset voltages, make the ramp voltage generator produce fixed slope and ramp voltage that there are different starting point voltages, and then control the length of the ON time of diverter switch.The zero staggered distortion effectively occurred because of the resonance that the parasitic capacitance of inductance and transistor switch produces in compensation power factor conversion control device.The conversion efficiency of effective bring to power factor conversion control device.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment, the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: its technical scheme that still can put down in writing aforementioned each embodiment is modified, or part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (15)
1. a power factor conversion control device, it is characterized in that, there is at least one diverter switch and at least one inductance, in order to receive the electric current that an input voltage conducting and closing control by this diverter switch flow through this inductance, produce an output voltage, comprising:
One switching control circuit, comprising to produce a switch control voltage according to this input voltage:
One ramp voltage generator, when this diverter switch conducting, produce a ramp voltage of fixed slope according to this input voltage, wherein a starting point voltage of this ramp voltage changes according to the size of this input voltage; And
One control signal generator, couple this ramp voltage generator, receives this ramp voltage, and this control signal generator is according to relatively this ramp voltage and a common voltage come this switch control voltage of forbidden energy to close this diverter switch.
2. power factor conversion control device according to claim 1, is characterized in that, wherein this control signal generator comprises:
One common voltage generator, receive the feedback voltage produced according to this output voltage of dividing potential drop, and according to this feedback voltage and one first reference voltage to produce this common voltage;
One resets holds comparator, couples this common voltage generator and this ramp voltage generator, according to relatively this common voltage and this ramp voltage produce a reset signal; And
One SR bolt lock device, couple this replacement end comparator, has the end of replacement, sets end and output, and this replacement termination is received this reset signal, and this output produces this switch control voltage.
3. power factor conversion control device according to claim 2, is characterized in that, wherein this control signal generator also comprises:
One inductance energy comparator, couple this inductance and this SR bolt lock device, and produce a setting signal according to electric current and a reference lower limit value of this inductance of relatively flowing through, and wherein this setting signal is sent to the setting end of this SR bolt lock device.
4. power factor conversion control device according to claim 3, is characterized in that, wherein, when this setting signal activation, this this switch control voltage of SR bolt lock device activation is with this diverter switch of conducting.
5. power factor conversion control device according to claim 2, is characterized in that, wherein this control signal generator also comprises:
One overcurrent comparator, couple this diverter switch, according to the electric current of this diverter switch of relatively flowing through and an overcurrent reference value to produce an over-current signal; And
One or the door, be serially connected in this replacement end comparator and transmit this reset signal between the approach of this SR bolt lock device, there is first input end, the second input and output, this first input end receives this over-current signal, this second input receives this reset signal, and this output is coupled to the replacement end of this SR bolt lock device.
6. power factor conversion control device according to claim 1, is characterized in that, wherein this ramp voltage generator comprises:
One multivoltage control circuit, according to an offset voltage of this input voltage generation direct current, wherein the magnitude of voltage of this offset voltage changes according to the size of this input voltage;
One electric capacity, an end of this electric capacity couples this multivoltage control circuit, and the other end produces this ramp voltage;
One current source, couple the other end of this electric capacity; And
One charge and discharge switch, with this electric capacity and connect, this charge and discharge switch is controlled by one and discharges and recharges control signal.
7. power factor conversion control device according to claim 6, is characterized in that, wherein this ramp voltage generator also comprises:
One buffer circuit, the input of this buffer circuit receives this switch control voltage, and the output of this buffer circuit couples this charge and discharge switch to provide this to discharge and recharge control signal.
8. power factor conversion control device according to claim 7, is characterized in that, wherein this buffer circuit is a negater circuit.
9. power factor conversion control device according to claim 6, is characterized in that, wherein this ramp voltage generator also comprises:
One bleeder circuit, couple this multivoltage control circuit, in order to receive and this input voltage of dividing potential drop and transmit dividing potential drop after this input voltage to this multivoltage control circuit.
10. power factor conversion control device according to claim 9, is characterized in that, wherein this bleeder circuit comprises:
One first divider resistance, a termination of this first divider resistance is received this input voltage, and the other end couples this multivoltage control circuit; And
One second divider resistance, be serially connected between the other end and one first ground connection reference voltage end of this first divider resistance.
11. power factor conversion control device according to claim 6, is characterized in that, wherein this ramp voltage generator also comprises:
One ratio-voltage produces circuit, and according to a plurality of scalings of this input voltage, to produce a plurality of convergent-divergent input voltages, and one of them is a selection voltage according to a mode signal is selected described convergent-divergent input voltage; And
One comparison circuit, couple this ratio-voltage and produce circuit, receive and compare one the 3rd reference voltage and described convergent-divergent input voltage one of them to produce this mode signal.
12. power factor conversion control device according to claim 11, is characterized in that, wherein this ramp voltage generator also comprises:
One reference signal generation circuit, couple this comparison circuit, in order to produce the 3rd reference voltage.
13. power factor conversion control device according to claim 11, is characterized in that, wherein this ratio-voltage generation circuit comprises:
A plurality of bleeder circuits, respectively according to different described this input voltages of scaling dividing potential drop, and produce a plurality of convergent-divergent input voltages; And
Selector, couple described bleeder circuit and this comparison circuit, receives described convergent-divergent input voltage and this mode signal, according to this mode signal, selects described convergent-divergent input voltage to produce this offset voltage.
14. power factor conversion control device according to claim 13, is characterized in that, wherein respectively this bleeder circuit comprises:
One first divider resistance, a termination of this first divider resistance is received this input voltage, and the other end couples this selector; And
One second divider resistance, be serially connected between the other end and one first ground connection reference voltage end of this first divider resistance.
15. power factor conversion control device according to claim 6, is characterized in that, wherein this multivoltage control circuit comprises:
One amplifier, have first input end, the second input and output;
One first resistance, be serially connected between the first input end and output of this amplifier;
One second resistance, be serially connected between this first resistance and one second ground connection reference voltage end;
One the 3rd resistance, an end of the 3rd resistance is coupled in the second input of this amplifier, and the other end receives this input voltage; And
One the 4th resistance, an end of the 4th resistance couples the second input of this amplifier, and the other end receives one second reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910172030XA CN102005914B (en) | 2009-09-03 | 2009-09-03 | Power factor conversion control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910172030XA CN102005914B (en) | 2009-09-03 | 2009-09-03 | Power factor conversion control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102005914A CN102005914A (en) | 2011-04-06 |
| CN102005914B true CN102005914B (en) | 2013-12-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910172030XA Expired - Fee Related CN102005914B (en) | 2009-09-03 | 2009-09-03 | Power factor conversion control device |
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| Country | Link |
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| CN (1) | CN102005914B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614810A (en) * | 1994-02-14 | 1997-03-25 | Magneteck, Inc. | Power factor correction circuit |
| US6388429B1 (en) * | 2000-03-09 | 2002-05-14 | Hengchun Mao | Controller for power factor corrector and method of operation thereof |
| CN1604441A (en) * | 2003-09-30 | 2005-04-06 | 三垦电气株式会社 | Power factor improving circuit |
| CN1906839A (en) * | 2004-08-27 | 2007-01-31 | 三垦电气株式会社 | Power factor improving circuit |
| CN2907072Y (en) * | 2005-11-09 | 2007-05-30 | 崇贸科技股份有限公司 | Switching control circuit for power factor control converter working in non-continuous mode |
-
2009
- 2009-09-03 CN CN200910172030XA patent/CN102005914B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5614810A (en) * | 1994-02-14 | 1997-03-25 | Magneteck, Inc. | Power factor correction circuit |
| US6388429B1 (en) * | 2000-03-09 | 2002-05-14 | Hengchun Mao | Controller for power factor corrector and method of operation thereof |
| CN1604441A (en) * | 2003-09-30 | 2005-04-06 | 三垦电气株式会社 | Power factor improving circuit |
| CN1906839A (en) * | 2004-08-27 | 2007-01-31 | 三垦电气株式会社 | Power factor improving circuit |
| CN2907072Y (en) * | 2005-11-09 | 2007-05-30 | 崇贸科技股份有限公司 | Switching control circuit for power factor control converter working in non-continuous mode |
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| Publication number | Publication date |
|---|---|
| CN102005914A (en) | 2011-04-06 |
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