CN102004439A - Design scheme for time checker of multi-rate watt-hour meter - Google Patents
Design scheme for time checker of multi-rate watt-hour meter Download PDFInfo
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Abstract
The invention provides a design scheme for a time checker of a multi-rate watt-hour meter. In the scheme, a central processing unit (CPU) W77E58 is a control and calculation core; a control input signal selection network selects a signal to be measured and transmits the signal into a timing reference frequency measurement circuit and a time interval switching signal measurement circuit for measurement; and a quartz crystal provides the frequency standard and a global positioning system (GPS) provides the time standard during the measurement. Through the scheme, the timing reference frequency, error and time interval switching error of the multi-rate watt-hour meter can be measured and time service is performed on a checked meter. The scheme has the advantages of high measurement speed and stability, multi-path measurement (60 paths can be measured once at most), simple design and low cost; in addition, the high-accuracy quartz crystal provides the frequency standard to guarantee high timing reference frequency measurement accuracy which is +/-0.2*10<-6>, the GPS provides the time standard and the satellite time service to guarantee high measurement resolution (1ms) of the time interval switching signal.
Description
Technical field
The present invention relates to a kind of multi-rate meter time check instrument design proposal, belong to the surveying instrument field.
Background technology
Universal day by day along with the power industry multi-rate meter, relevant metering and measuring equipment is also progressively put into effect.Because multi-rate meter is to divide section with the time, the accuracy meeting of time directly influences the accuracy of metering, so during the verification multi-rate meter, except that electric energy standard of need, also needs a time standard.The function of time check instrument is exactly to measure timing reference frequency and the error and the period switching error of multi-rate meter, and gives the calibrated meter time service.For this reason, tester must have high-precision frequency standard and time standard.
Summary of the invention
1, goal of the invention: the present invention proposes a kind of multi-rate meter time check instrument design proposal, CPUW77E58 is control and calculating core in this scheme, its control input signals is selected network, need to select the signal of measurement, send into timing reference frequency metering circuit and period switching circuitry for signal measurement is measured, the high-precision quartz crystal provides frequency standard, GPS that time standard is provided during measurement.This scheme can be measured timing reference frequency and the error and the period switching error of multi-rate meter, and gives the calibrated meter time service.
2, technical scheme
General structure of the present invention as shown in Figure 1, CPU W77E58 is for control and calculate core, multidiameter option switch CD4051 and d type flip flop 74LS174 form input signal and select network, counter Intel 8254 and measurement gating circuit are formed timing reference frequency metering circuit, 8 input d type flip flops, rejection gate CD4078 and latch 74LS273 form period switching circuitry for signal measurement, the high-precision quartz crystal provides the frequency standard of 10MHz during measurement, and GPS GSU36 provides time standard and PPS pulse per second (PPS).Measurement result is passed to PC through communication module, by PC to the calibrated meter time service.Keyboard and demonstration receive user's operation as man-machine interface, show specific status information.
3, advantage and effect
CPU W77E58 is control and calculating core among the present invention, multidiameter option switch CD4051 and d type flip flop 74LS174 form input signal and select network, counter Intel 8254 and d type flip flop 74F74 form timing reference frequency metering circuit, d type flip flop 74F74,8 input rejection gate CD4078 and latch 74LS273 form period switching circuitry for signal measurement, and the high-precision quartz crystal provides frequency standard, GPS that time standard is provided during measurement.This scheme measuring speed is fast, good stability, multichannel measurement (at most can one-shot measurement 64 tunnel) and simplicity of design, cost be low, and the high-precision quartz crystal provides frequency standard in addition, timing reference frequency accuracy of measurement height (± 0.2 * 10
-6), GPS provides the time service of time standard satellite, period switching signal measurement resolution height (1ms).
Description of drawings
Fig. 1. overall construction drawing of the present invention;
Fig. 2. input signal of the present invention is selected network;
Fig. 3. timing reference frequency of the present invention is measured gating circuit figure;
Fig. 4. the circuit connection diagram of CPU of the present invention and Intel 8254;
Fig. 5. period switching circuitry for signal measurement figure of the present invention.
Embodiment
General structure of the present invention mainly comprises input selection module, measurement module, CPU W77E58 module, 10MHz crystal oscillator module, GSU36 module, communication module, Keysheet module and display module etc. as shown in Figure 1.CD4051 and 74LS174 form input signal and select network, during meter during reference frequency, under the control of CPU W77E58, from 64 tunnel timing reference frequency signals of input, select 1 the tunnel at every turn, give the timing reference frequency metering circuit of being made up of Intel 8254 and measurement gating circuit and measure, the high-precision quartz crystal provides the standard frequency of 10MHz during measurement.During measurement period switching signal under the control of CPUW77E58, from 64 tunnel period switching signals of input, select 8 the tunnel at every turn, give the period switching circuitry for signal measurement of being made up of 8 d type flip flops and CD4078 and 74LS273 and measure, GPS GSU36 module provides time standard and PPS pulse per second (PPS) during measurement.Measurement result is passed to PC through communication module, by PC to the calibrated meter time service.Keyboard and demonstration receive user's operation as man-machine interface, show particular state information.
With reference to Fig. 2, nine multidiameter option switch CD4051 of U1 six d type flip flop 74LS174 and U2～U10 form input signal and select network.64 road input signal F1～F64 are divided into 8 groups, F1～F8 is first group and links to each other with 8 input end X0～X7 of U2 (CD4051) respectively, F9～F16 is second group and links to each other with 8 input end X0～X7 of U3 (CD4051) respectively, be the 8th group up to F57～F64 by that analogy and link to each other with 8 input end X0～X7 of U9 (CD4051) respectively that such 64 road input signals divide 8 groups to send in the system by 8 CD4051.The selection output terminal of described 8 CD4051 is that 8 X ends of U2～U9 form 8 tunnel selection output signal Fx0～Fx7, this 8 road signal links to each other with the CLK end of 8 input d type flip flops in the described period switching circuitry for signal measurement with 8 input end X0～X7 of U10 (CD4051) respectively, and the selection output terminal X-shaped of U10 (CD4051) becomes the FXIN signal to be sent to described timing reference frequency measurement gating circuit.The selection control signal of U2～U10 is provided by U1 (74LS174), data input pin 1D～6D of U1 (74LS174) links to each other with D0～D5 signal that the P0 mouth of CPU W77E58 produces respectively, and the clock CLK of U1 (74LS174) links to each other with the P3.4 that CPU W77E58 produces the FS signal.Data output end 1Q, the 2Q of U1 (74LS174) selects control end A, B to link to each other with C with the switch of U2～U9 respectively with 3Q, and 4Q, 5Q select control end A, B to link to each other with C with the switch of U10 (CD4051) respectively with 6Q.
During meter during reference frequency, 64 road input signal F1～F64 link to each other with the timing reference frequency signal of 64 road multi-rate meters, input signal selects the U2～U9 of network under the control of CPU W77E58, from 64 road signal F1～F64, select 8 the tunnel earlier, form Fx0～Fx7 and give U10 (CD4051), U10 (CD4051) selects 1 the tunnel again and forms the FXIN signal and be sent to described timing reference frequency and measure gating circuit and measure under the control of CPU W77E58.During measurement period switching signal, 64 road input signal F1～F64 link to each other with the period switching signal of 64 road multi-rate meters, input signal selects the U2～U9 of network under the control of CPUW77E58, select 8 the tunnel from 64 road signal F1～F64, formation Fx0～Fx7 directly is sent to described period switching circuitry for signal measurement and measures.
During meter during reference frequency, input signal selects network to select 1 the tunnel to give described timing reference frequency as the FXIN signal and measure gating circuit as shown in Figure 3 from 64 tunnel input timing reference frequency signals.Signal FXIN is amplified by Q1 (9014) through the base stage that resistance R 1 enters triode Q1 (9014), the grounded emitter of Q1 (9014), collector meets a pull-up resistor R2 and links to each other with the CLK end of two d type flip flop U11A and U12A simultaneously, as the clock of these two d type flip flops.The directreset terminal CLR of the first d type flip flop U11A meets voltage VCC, links to each other with the P1.0 of the CPU W77E58 that produces the GG1 signal after directset terminal PRE links to each other with the directreset terminal CLR of the second d type flip flop U12A, and output terminal Q produces
Signal links to each other with the INT0 of CPUW77E58, and the data input pin D of the data input pin D and the second d type flip flop U12A links to each other afterwards and the output terminal of U12A
Link to each other.The directset terminal PRE of U12A links to each other with the P1.1 of the CPU W77E58 that produces GG2, and output terminal Q generation QIG signal links to each other with the GATE1 of Itel8254 simultaneously and two inputs link to each other with the input end of door AND2.Another input end of AND2 links to each other with the 10MHz standard-frequency signal that the constant temperature quartz crystal provides, and the output terminal of AND2 produces the I-8254 signal and links to each other with the CLK1 of Itel8254.
With reference to Fig. 4, U13 (CPU W77E58) is the control of total system and calculates core.The P0 mouth of U13 (CPU W77E58) produces 8 bit data bus D[0 ... 7] with the D[0 of U15 (Itel8254) ... 7] corresponding linking to each other, and with the D[0 of U14 (74LS373) ... 7] corresponding linking to each other, pass through Q[0 ... 7] output least-significant byte address bus A[0 ... 7], the P2 mouth produces most-significant byte address bus A[8 ... 15].The P1.0 of U13 (CPU W77E58) P1 mouth and P1.1 produce two the trigger U11A and the U12A of GG1 and the described measurement gating circuit of GG2 signal controlling respectively, P1.3 produces the WORK signal of expression CPU operate as normal, K1, K2, K3 and U16 (74LS138) output terminal that P1.4, P1.5, P1.6 produce
Produce Y1, Y2 and form keyboard matrix.U13 (CPU W77E58) P3.4 produces the FS signal and links to each other with the CLK of described input signal sampling network U1 (74LS174), P3.5 produces GPS duty indicator signal GPS, RXD0 forms the RS232 interface with TXD0 and links to each other with TXD with the RXD of host computer, finish with upper PC and communicate by letter, RXD1 receives the time standard signal GPSTXD that GPS sends.The INT0 of U13 (CPU W77E58) and described timing reference frequency are measured the frequency measurement look-at-me that U11A output terminal Q produces in the gating circuit
Link to each other, INT1 links to each other with the interruption input signal INT1 of CD4078 output terminal generation in the described period switching circuitry for signal measurement, and INT2 links to each other with the standard second pulse PPS that GPS sends.The ALE/P of U13 (CPU W77E58) links to each other read-write with the LE of U14 (74LS373)
RD, WR respectively at U15 (Intel 8254) link to each other, and produce CS138 signal, the gating end of CS138 signal and address generator U16 (74LS138) through one two input and door simultaneously
With
Link to each other.The gating end G1 of U16 (74LS138) links to each other with the address A14 that the P2 mouth of U13 (CPUW77E58) produces, decoding address input end A, the B of U16 (74LS138) links to each other the output of U16 (74LS138) with U14 (74LS373) OPADD signal A4, A5 respectively with C with A6
Produce the CS8254 signal and link to each other with the chip selection signal CS of U15 (Intel 8254),
Produce the SDC signal and link to each other with the clock CLK of described period switching circuitry for signal measurement U25 (74LS273),
Produce the SDS signal and link to each other with the clock CLK of described period switching circuitry for signal measurement U27 (74LS273),
K1, K2 that Y1, Y2 signal and the U13 (CPU W77E58) that produces produces and K3 form keyboard matrix,
Produce LCDDATA, CDEN, CDSTR data and control signal as display.
U15 (Intel 8254) is a kind of programmable Timer, and independently 16 down counters are as shown in Figure 4 to have 3.The CLK0 of U15 (Intel 8254) links to each other with the 10MHz standard frequency that the constant temperature quartz crystal provides, and promptly the 10MHz standard-frequency signal is sent into counter 0, and 0 couple of 10MHz of counter carries out 10
4Frequency division obtains the 1KHz signal of standard, sends from OUT0, and GATE0 meets voltage VCC.GATE1 links to each other with the QIG that the described measurement gating circuit second d type flip flop U12A output terminal Q produces, the I-8254 with the generation of door AND2 output terminal of described measurement gating circuit sends into counter 1 by CLK1, the output terminal OUT1 of counter 1 links to each other through the CLK2 of not gate with counter 2, and GATE2 meets voltage VCC.2 cascades of counter 1 sum counter under the control of U13 (CPU W77E58), are carried out frequency measurement to input signal FXIN.A0, the A1 of U15 (Intel 8254) links to each other with address A0, A1 that U14 (74LS373) output terminal produces, the chip selection signal CS of U15 (Intel 8254) and U16 (74LS138) output that produces the CS8254 signal
Link to each other, can analyze, the address of U15 (Intel 8254) is 4000H～4003H, be that the control register port address is 4003H, the port address of 3 counters is respectively 4000H, 4001H, 4002H, can realize operations such as the initialization of U15 (Intel 8254) and read-writes by these addresses.
The measurement of timing reference frequency will be measured the nominal value f of reference frequency He this electric energy meter reference frequency of which road electric energy meter before this by keyboard input
b, CPU W77E58 controls described input signal by the P0 mouth and selects network, selects the accurate frequency signal of this roadbed, forms FXIN, gives described measurement gating circuit.After signal FXIN enters 9014 amplifications of described measurement gating circuit process triode, as the clock CLK of two d type flip flops.The P1.0 of CPU W77E58 is 0 o'clock, the first trigger U11A puts 1, the second trigger U12A clear 0, begin to measure, first rising edge of FXIN makes two triggers put 1 simultaneously, open the AND2 door and start the GATE1 of Intel 8254 counter T1, make Intel 8254 begin to count the 10MHz standard-frequency signal.Second rising edge of FXIN makes U11A and U12A two triggers put 0 simultaneously, the second trigger U12A puts 0, closing AND2 door and GATE1 makes Intel 8254 stop counting, the first trigger U11A puts 0, application is interrupted, CPU W77E58 enters interrupt service subroutine, reference frequency f when reading Intel 8254 count results and calculating meter according to this result
xAccording to r
e=[(f
x-f
b)/f
b] * 10
6(PPM) the relative error r of calculated rate
e, according to d
e=r
eBut the day error d of * 24 * 60 * 60 calculated rate errors
e, show result of calculation by display.
With reference to Fig. 5, one group of 8 road signal of the each measurement of period switching circuitry for signal measurement.Select one group of 8 tunnel period switching signal Fx0～Fx7 of network selecting from described input signal, CLK end with 8 input d type flip flop U17A～U24A links to each other respectively, the data input pin D of 8 input d type flip flop U17A～U24A with after their PRE ends separately link to each other meets voltage VCC, reset terminal CLR links to each other with 1Q～8Q end of the first latch U25 (74LS273) that produces CLR1～CLR8 respectively, and it is corresponding continuous with input end 1D～8D of input end Q1～Q8 of 8 input nand gate U26 (CD4078) and second latch U27 (74LS273) respectively that output terminal Q produces Q1～Q8 signal.The output terminal of 8 input nand gate U26 (CD4078) produces INT1 and links to each other with the INT1 end of CPU W77E58.Output terminal 1Q～8Q of second latch U27 (74LS273) respectively with corresponding linking to each other of D0～D7 of the P0 mouth of CPU W77E58, CLR termination voltage VCC, CLK end and 74LS138 output terminal
The SDS that produces links to each other.Data input pin 1D～8D of first latch U25 (74LS273) is corresponding continuous with D0～D7 that the P0 mouth of CPU W77E58 produces respectively, data output end 1Q～8Q produces CLR1～CLR8 and links to each other the output terminal of the 74LS138 of clock CLK end and generation SDC with the reset terminal CLR of 8 input d type flip flop U17A～U24A respectively
Link to each other CLR termination voltage VCC.
The measurement of period switching signal, the numbering and the nominal value t of every road switching time of 8 tunnel period switching signals that will measure by keyboard input before this
bCPU W77E58 selects network according to the numbering control input signals of input, and 8 tunnel period switching signals of selecting to measure from 64 tunnel form Fx1～Fx8, sends into the CLK end of 8 d type flip flops respectively.CLR1～CLR8 signal that CPU W77E58 produces by first latch U25 (74LS273) during measurement, to 8 input d type flip flop U17A～U24A zero clearings, any switching pulse of coming in 8 road signals, the capital makes the Q end set of its corresponding d type flip flop, 8 input rejection gate U26 (CD4078) output low levels.This low level is delivered to the INT1 of CPU W77E58, and CPU W77E58 interrupts, and enters interrupt service routine, reads the data of second latch U27 (74LS273), and provides time standard to calculate measurement period switching time t according to GPS GSU36 module
c, and according to formula s
e=t
c-t
bCalculation interval switching error shows result of calculation by display.After this drive test amount finished, CLR1～CLR8 signal that CPU W77E58 produces by U25 (74LS273) again made this road input d type flip flop put 0, continues to measure other 7 tunnel period switching signals.
Software design of the present invention four big handling procedures be respectively button handling procedure, DP display processor, each handling procedure all was provided with a zone bit to processing program and communication processing program in one second.Master routine is operated in inquiry mode, inquires about this four zone bits always, finds zone bit and is 1 and forward the alignment processing program run to.This method have clear layer, simple in structure, handle fast, easy characteristics such as expansion.For Intel 8254,2 series connection of counter 1 sum counter have been adopted in order to extend measurement lower limit, but the counter initial value of Intel 8254 is just put into after receiving 1 pulse, so can correctly count in order to make counter 2, must guarantee Intel 8254 before beginning measurement, counter 1 has the output of 1 pulse at least.Make in the native system the pre-work of Intel 8254 10ms with on realize.
Claims (4)
1. multi-rate meter time check instrument design proposal, it is characterized in that: in this scheme, CPU W77E58 is for control and calculate core, the timing reference frequency signal and the period switching signal of the multi-rate meter that its control input signals selection network selecting need be measured, the signal of selecting is sent into timing reference frequency metering circuit and period switching circuitry for signal measurement, measure timing reference frequency and the error and the period switching error of multi-rate meter, and give the calibrated meter time service, quartz crystal provides frequency standard, GPS that time standard is provided during measurement.
2. according to claim 1 described a kind of multi-rate meter time check instrument design proposal, it is characterized in that: described input signal selects network to be made up of 9 multidiameter option switch CD4051 and 1 d type flip flop 74LS174,64 road input signal F1～F64 are divided into 8 groups every group 8, link to each other with input end X0～X7 of preceding 8 CD4051 of described 9 CD4051 respectively, the output terminal X of described preceding 8 CD4051 produces 8 and selects output signal Fx0～Fx7, link to each other with 8 input end X0～X7 of the 9th CD4051 of the CLK end of 8 input d type flip flops and described 9 CD4051 in the described period switching circuitry for signal measurement respectively, the selection output terminal X of described the 9th CD4051 produces the FXIN signal and is sent to described timing reference frequency metering circuit, the selection control end A of described the 9th CD4051, B, C respectively with the data output end 4Q of described 74LS174,5Q, 6Q links to each other, the selection control end A of described preceding 8 CD4051, B, C respectively with the data output end 1Q of described 74LS174,2Q, 3Q links to each other, described 74LS174 data input pin 1D～6D links to each other with D0～D5 signal that the P0 mouth of described CPU W77E58 produces respectively, and clock CLK links to each other with the P3.4 of described CPU W77E58.
3. according to claim 1 described a kind of multi-rate meter time check instrument design proposal, it is characterized in that: described timing reference frequency metering circuit is measured gating circuit by counter Intel 8254 and timing reference frequency and is formed, described timing reference frequency is measured gating circuit and is mainly contained a triode, two d type flip flops and one and door composition, described input signal is selected the signal of network selecting, the base stage that enters described triode through a resistance, amplify by triode, the grounded emitter of described triode, collector connects a pull-up resistor and links to each other with the CLK end of described two d type flip flops simultaneously, clock as these two d type flip flops, the directreset terminal CLR of described two d type flip flop first d type flip flops meets voltage VCC, after linking to each other with the directreset terminal CLR of second d type flip flop of described two d type flip flops, directset terminal PRE links to each other with the P1.0 of described CPU W77E58, the described first d type flip flop output terminal Q links to each other the data input pin D and the data output end of data input pin D and described second d type flip flop with the INT0 of described CPU W77E58
Link to each other, the directset terminal PRE of described second d type flip flop links to each other with the P1.1 of described CPU W77E58, output terminal Q links to each other with the GATE1 of described Itel8254 and links to each other with an input end of door with described simultaneously, describedly link to each other with the 10MHz standard-frequency signal that the constant temperature quartz crystal provides, describedly link to each other with the CLK1 of described Itel8254 with the output terminal of door with another input end of door.
4. according to claim 1 described a kind of multi-rate meter time check instrument design proposal, it is characterized in that: described period switching circuitry for signal measurement mainly contains 8 input d type flip flops, one 8 input rejection gate CD4078 and two latch 74LS273 form, the CLK end of described 8 input d type flip flops selects one group of 8 tunnel period switching signal Fx0～Fx7 of network selecting to link to each other respectively with from described input signal, the data input pin D of described 8 input d type flip flops with after their PRE ends separately link to each other meets voltage VCC, reset terminal CLR links to each other with output terminal 1Q～8Q end of first 74LS273 of described two latch 74LS273 respectively, the output terminal Q of described 8 input d type flip flops is corresponding continuous with input end 1D～8D of second 74LS273 of input end Q1～Q8 of described 8 input nand gate CD4078 and described two latch 74LS273 respectively, the output terminal of described 8 input nand gate CD4078 links to each other with the INT1 end of described CPU W77E58, output terminal 1Q～8Q of described second latch 74LS273 respectively with corresponding linking to each other of D0～D7 of the P0 mouth of described CPU W77E58, the CLR termination voltage VCC of described second latch 74LS273, CLK end and 74LS138 output terminal
Link to each other, data input pin 1D～8D of described first latch 74LS273 is corresponding continuous with D0～D7 that the P0 mouth of described CPU W77E58 produces respectively, the clock CLK end of described first latch 74LS273 and the output terminal of 74LS138
Link to each other CLR termination voltage VCC.
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| CN109709394A (en) * | 2018-12-21 | 2019-05-03 | 深圳市航天泰瑞捷电子有限公司 | A kind of system of detection clock of power meter output |
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