CN101996933B - 顶层铜互连层的制作方法 - Google Patents
顶层铜互连层的制作方法 Download PDFInfo
- Publication number
- CN101996933B CN101996933B CN 200910056768 CN200910056768A CN101996933B CN 101996933 B CN101996933 B CN 101996933B CN 200910056768 CN200910056768 CN 200910056768 CN 200910056768 A CN200910056768 A CN 200910056768A CN 101996933 B CN101996933 B CN 101996933B
- Authority
- CN
- China
- Prior art keywords
- layer
- fsg
- copper interconnection
- etching
- sion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200910056768 CN101996933B (zh) | 2009-08-20 | 2009-08-20 | 顶层铜互连层的制作方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200910056768 CN101996933B (zh) | 2009-08-20 | 2009-08-20 | 顶层铜互连层的制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101996933A CN101996933A (zh) | 2011-03-30 |
CN101996933B true CN101996933B (zh) | 2013-07-31 |
Family
ID=43786868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 200910056768 Expired - Fee Related CN101996933B (zh) | 2009-08-20 | 2009-08-20 | 顶层铜互连层的制作方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101996933B (zh) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1577794A (zh) * | 2003-07-09 | 2005-02-09 | 台湾积体电路制造股份有限公司 | 镶嵌式金属内连线的制造方法及介电层的修复程序 |
CN101312150A (zh) * | 2007-05-21 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | 双镶嵌结构的形成方法 |
-
2009
- 2009-08-20 CN CN 200910056768 patent/CN101996933B/zh not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1577794A (zh) * | 2003-07-09 | 2005-02-09 | 台湾积体电路制造股份有限公司 | 镶嵌式金属内连线的制造方法及介电层的修复程序 |
CN101312150A (zh) * | 2007-05-21 | 2008-11-26 | 中芯国际集成电路制造(上海)有限公司 | 双镶嵌结构的形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN101996933A (zh) | 2011-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6962869B1 (en) | SiOCH low k surface protection layer formation by CxHy gas plasma treatment | |
US7767578B2 (en) | Damascene interconnection structure and dual damascene process thereof | |
US6074942A (en) | Method for forming a dual damascene contact and interconnect | |
US6287956B2 (en) | Multilevel interconnecting structure in semiconductor device and method of forming the same | |
US7436009B2 (en) | Via structures and trench structures and dual damascene structures | |
US7466027B2 (en) | Interconnect structures with surfaces roughness improving liner and methods for fabricating the same | |
CN101587859B (zh) | 形成半导体互联结构的方法 | |
US7968456B2 (en) | Method of forming an embedded barrier layer for protection from chemical mechanical polishing process | |
US8084357B2 (en) | Method for manufacturing a dual damascene opening comprising a trench opening and a via opening | |
CN101996933B (zh) | 顶层铜互连层的制作方法 | |
US20100029086A1 (en) | Method for manufacturing semiconductor device and storage medium | |
US7622331B2 (en) | Method for forming contacts of semiconductor device | |
US7015149B2 (en) | Simplified dual damascene process | |
JPH10116904A (ja) | 半導体装置の製造方法 | |
CN114823489A (zh) | 一种金属线或金属件的形成方法 | |
CN108573912B (zh) | 半导体结构及其形成方法 | |
US20070134915A1 (en) | Method of fabricating a metal line in a semiconductor device | |
US7232746B2 (en) | Method for forming dual damascene interconnection in semiconductor device | |
US8048799B2 (en) | Method for forming copper wiring in semiconductor device | |
TWI248660B (en) | Method of forming a conductor in a fluoride silicate glass (FSG) layer | |
TWI233661B (en) | Method for forming multi-layer metal line of semiconductor device | |
KR100668961B1 (ko) | 금속-절연체-금속 커패시터의 제조 방법 | |
KR101138082B1 (ko) | 반도체 소자의 듀얼 다마신 패턴 형성방법 | |
US7135400B2 (en) | Damascene process capable of avoiding via resist poisoning | |
KR20080024641A (ko) | 반도체 소자의 도전 패턴 형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121119 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20121119 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130731 Termination date: 20200820 |
|
CF01 | Termination of patent right due to non-payment of annual fee |