CN101980145B - No-carry adder of ternary optical computer - Google Patents
No-carry adder of ternary optical computer Download PDFInfo
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- CN101980145B CN101980145B CN2010105183424A CN201010518342A CN101980145B CN 101980145 B CN101980145 B CN 101980145B CN 2010105183424 A CN2010105183424 A CN 2010105183424A CN 201010518342 A CN201010518342 A CN 201010518342A CN 101980145 B CN101980145 B CN 101980145B
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Abstract
The invention discloses a no-carry adder of a ternary optical computer. The no-carry adder comprises a first arithmetic and logic unit, a second arithmetic and logic unit, a third arithmetic and logic unit and an advanced RISC machine development board which are sequentially connected in series, wherein each arithmetic and logic unit consists of liquid crystals, polarizing films and a photosensitive array; the first arithmetic and logic unit is used for performing T operation and W operation; the second arithmetic and logic unit is used for performing T' operation and W' operation; the third arithmetic and logic unit is used for performing the T operation and realizing the once no-carry addition of the ternary optical computer; and the ARM development board is used for generating liquid crystal control signals by using input operands and signals of the outlines of the photosensitive arrays and transmitting the generated liquid crystal control signals to the liquid crystals. The no-carry adder can perform the operation with the operands of hundreds of millions of bits only by replacing a liquid crystal screen with a plurality of liquid crystal dots, finishes the addition operation once for a time which is one third of the time spent on the addition operation of the conventional adders, and increases the running speed of the optical computer.
Description
Technical field
What the present invention relates to is a kind of false add musical instruments used in a Buddhist or Taoist mass of three value optical computers.
Background technology
The 1053rd～1057 page of magazine " Chinese science E collects: information science " the 12nd phase of going up " a kind of optical means of the MSD of realization addition " and publishing in 2008 of 39 the 6th phases of volume of magazine " photon journal " of publishing in 2010 gone up the restructing operation device that " nothing is advanced the depreciation design theory and the application in three value optical computers thereof of (borrowing) bit arithmetic device " discloses MSD addition and three value optical computers respectively; But there is not totalizer on the strict meaning of existing three value optical computers; Existing restructing operation device can only carry out logical operation, will could accomplish with at least three computings of restructing operation device operation according to three steps of MSD addition algorithm when carrying out add operation.Based on the restructing operation device technical design of the algorithm of MSD addition and three value optical computers carry out the totalizer of additive operation that the huge positional operand of three value optical computers is accomplished in once-through operation.Though this MSD addition is a kind of algorithm of completion addition of ability no-carry, this totalizer does not realize this additive operation on liquid crystal or other concrete physical device.
Relate to 4 kinds of logical operations in the MSD addition described in the existing literature " a kind of optical means of the MSD of realization addition ", the truth table of this computing, as shown in the table.
Table: logical operation truth table
Table 1 is the T computing, W computing, the truth table of T ' computing and W ' computing.When carrying out the light path computing ,-1 corresponding vertical light in the table, 0 is corresponding unglazed, 1 corresponding horizon light.For the T computing, the W computing, the input of T ' computing and W ' computing and the span of operation result are-1,0 and 1.A in the truth table and b are one that carries out in two operands of logical operation, and a row are capable with b to be the possible value of carrying out a positional operand of computing, and the value of two value intersections is operation results.For example a row are-1 in the T computing truth table, and b is capable to be-1 o'clock value-1 in the correspondence table, representes that the result that a positional operand-1 and-1 carries out the T computing is-1, and just importing the two-way vertical light, to carry out the result of T computing be vertical light.
Described MSD addition, its concrete steps are following:
1, to the operand of input, carry out T and W conversion simultaneously, the T transformation results of i position writes on position, i+1 position, mends 0 for the 0th, that is, and and t
i=T (x
I-1, y
I-1), w
i=W (x
i, y
i);
2, to t
i=T (x
I-1, y
I-1), w
i=W (x
i, y
i) operation result carry out T ' and W ' conversion respectively, the T ' transformation results of i position writes on position, i+1 position, mends 0 for the 0th, that is, t '
i=T ' (t
I-1, w
I-1), w '
i=W ' (t
i, w
i);
3, to t '
i=T ' (t
I-1, w
I-1), w '
i=W ' (t
i, w
i) operation result carry out the T conversion, obtain its two MSD numbers with, the T transformation results of i position writes on the i position, that is, t
i=T (t '
i, w '
i).
The restructing operation device of three value optical computers described in above-mentioned " nothing is advanced the depreciation design theory and the application in three value optical computers thereof of (borrowing) bit arithmetic device "; When every positional operand carries out T ' computing, need the liquid crystal dots of a HH type and the liquid crystal dots of a VV type.HH type liquid crystal dots representes that the front and back polaroid of this liquid crystal dots all is a horizontal type, and H representes the polaroid of horizontal type, and VV type liquid crystal dots representes that this liquid crystal dots front and back polaroid all is a vertical type, and V representes the polaroid of vertical type.Can judge the operation result of every positional operand through the rear polarizer sensitivity speck at the back of liquid crystal dots.
The output line signal of setting each sensitivity speck is for having light or unglazed two kinds; There is light to represent with 1; Unglazed usefulness 0 representes, the output that the type of this sensitivity speck front polaroid can be judged the liquid crystal dots corresponding with this sensitivity speck is the type of light as a result, if the sensitivity speck front is a V-type vertical type polaroid; And the output line signal of sensitivity speck is 1, and the corresponding output result of this liquid crystal dots is a vertical light so; If the sensitivity speck front is a H type vertical type polaroid, and the output line signal of sensitivity speck is 1, and the corresponding output result of this liquid crystal dots is a horizon light so; If the output line signal of sensitivity speck is 0, the corresponding output result of this liquid crystal dots is unglazed so.
If the signal of the sensitivity speck output line that this VV type liquid crystal dots back is corresponding is 1, the corresponding output result of this liquid crystal dots is a vertical type light so; If the signal of the sensitivity speck output line that this VV type liquid crystal dots back is corresponding is 0, the corresponding output result of this liquid crystal dots is unglazed so.The output result's that VV type liquid crystal dots is corresponding span is a vertical light and unglazed.
If the signal of the sensitivity speck output line that this HH type liquid crystal dots back is corresponding is 1, the corresponding output result of this liquid crystal dots is a horizontal type light so; If the signal of the sensitivity speck output line that this HH type liquid crystal dots back is corresponding is 0, the corresponding output result of this liquid crystal dots is unglazed so.The output result's that HH type liquid crystal dots is corresponding span is a horizontal light and unglazed.
Determine jointly for the T ' operation result of every positional operand light type by the output result of a HH type liquid crystal dots of correspondence and a VV type liquid crystal dots; If the output result of corresponding HH type liquid crystal dots is a horizon light; The corresponding horizon light of the result of this positional operand T ' computing so, just 1.If the output result of corresponding VV type liquid crystal dots is a vertical light, the corresponding vertical light of the result of this positional operand T ' computing so, just-1.
In sum, any logical operation can be accomplished through several above-mentioned liquid crystal dots.When carrying out additive operation, according to the algorithm of MSD addition, T computing and W computing to be done together, T ' computing and W ' computing are done together, move three restructing operation devices at least and could accomplish a sub-addition.Carry out time that one time add operation spent and be three times an of working time of restructing operation device, influence the optical computer travelling speed.
Summary of the invention
The objective of the invention is to overcome deficiency of the prior art, a kind of false add musical instruments used in a Buddhist or Taoist mass of three value optical computers is provided, the disposable completion of this totalizer ability need not the additive operation of carry, is applicable to the computing of hundreds and thousands of the operand that photometry is calculated.
The technical scheme that the present invention adopted is: a kind of false add musical instruments used in a Buddhist or Taoist mass of three value optical computers; This totalizer is between the encoder of three value optical computers; It comprises first logic unit connected in series successively, second logic unit, the 3rd logic unit, ARM development board; First logic unit is made up of first liquid crystal, the first forward and backward polaroid, first photosensitive array, is used for accomplishing simultaneously T computing and the W computing that input light path is participated in; Second logic unit is made up of second liquid crystal, the second forward and backward polaroid, second photosensitive array, is used for accomplishing simultaneously T ' computing and the W ' computing that input light path is participated in; The 3rd logic unit is made up of the 3rd liquid crystal, the 3rd forward and backward polaroid, the 3rd photosensitive array, is used to accomplish the T computing that input light path is participated in, and realizes the disposable three value optical computer additions that need not carry; The ARM development board; Be used for the signal of input operand and photosensitive array output line is generated the liquid crystal control signal; Give liquid crystal with the liquid crystal control signal that generates; Above-mentioned first, second, third forward and backward polaroid is attached to the two sides, front and back of above-mentioned first, second, third liquid crystal respectively; Above-mentioned first, second, third photosensitive array is attached to respectively on above-mentioned first, second, third rear polarizer, and the control signal wire of first, second, third liquid crystal is connected with the ARM development board respectively with first, second, third photosensitive array output line.
The advantage that the false add musical instruments used in a Buddhist or Taoist mass of a kind of three value optical computers of the present invention compared with prior art has:
This false add musical instruments used in a Buddhist or Taoist mass is applied in the operand computing that the used liquid crystal in three value optical computer laboratories can walk abreast and carry out 500 multidigits, only need change the liquid crystal display of more liquid crystal dots numbers for the computing of multidata position more; When existing optical computer carries out additive operation, adopt the restructing operation device of three value optical computers, this arithmetical unit is realized according to three ability of MSD addition algorithm computing at least; This false add musical instruments used in a Buddhist or Taoist mass can disposable completion additive operation, and the used time is suitable with the time of a restructing operation device of operation, and the used time is equivalent to 1/3rd of the used time of previous methods, improves the optical computer travelling speed.
Description of drawings
Fig. 1 is the operational flowchart of the false add musical instruments used in a Buddhist or Taoist mass of three value optical computers of the present invention;
Fig. 2 be the false add musical instruments used in a Buddhist or Taoist mass of three value optical computers of the present invention realize T computing on T computing, T ' computing and the 3rd logic unit in the method for additive operation data bit to bitmap.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment embodiments of the invention are described in further detail.
Referring to Fig. 1; The present invention is a kind of false add musical instruments used in a Buddhist or Taoist mass of three value optical computers; This totalizer is between the encoder of three value optical computers; It comprises first logic unit connected in series successively, second logic unit, the 3rd logic unit, ARM development board, and first logic unit is made up of first liquid crystal, the first forward and backward polaroid, first photosensitive array, is used for accomplishing simultaneously T computing and the W computing that input light path is participated in; Second logic unit is made up of second liquid crystal, the second forward and backward polaroid, second photosensitive array, is used for accomplishing simultaneously T ' computing and the W ' computing that input light path is participated in; The 3rd logic unit is made up of the 3rd liquid crystal, the 3rd forward and backward polaroid, the 3rd photosensitive array, is used to accomplish the T computing that input light path is participated in, and realizes the disposable three value optical computer additions that need not carry; The ARM development board; Be used for the signal of input operand and photosensitive array output line is generated the liquid crystal control signal; Give liquid crystal with the liquid crystal control signal that generates; Above-mentioned first, second, third forward and backward polaroid is attached to the two sides, front and back of above-mentioned first, second, third liquid crystal respectively; Above-mentioned first, second, third photosensitive array is attached to respectively on above-mentioned first, second, third rear polarizer, and the control signal wire of first, second, third liquid crystal is connected with the ARM development board respectively with first, second, third photosensitive array output line.
The false add musical instruments used in a Buddhist or Taoist mass of above-mentioned three value optical computers is realized the method for additive operation, and its concrete operation step is following:
1, input operand produces input light path on first logic unit through scrambler; Produce T computing and the liquid crystal control signal of W computing on first logic unit through the ARM development board; Liquid crystal control signal on first logic unit, operand b in the truth table of corresponding is T computing and W computing;
2, above-mentioned first logic unit carries out T computing and W computing on first liquid crystal and the first forward and backward polaroid; The result of its computing flows to the ARM development board through the output line of first photosensitive array; The ARM development board produces the liquid crystal control signal of second arithmetic unit; Operand a in operand a and the W computing truth table in the corresponding T computing truth table of direct input difference of T computing and W computing; T ' computing liquid crystal control signal on second arithmetic unit is corresponding is the operand b in the truth table of T ' computing, and W ' the computing liquid crystal control signal on second arithmetic unit is corresponding is the operand b in the truth table of W ' computing;
3, above-mentioned second logic unit carries out T ' computing and W ' computing on second liquid crystal and the second forward and backward polaroid; The result of its computing gives ARM development board through the output line of second photosensitive array, and the ARM development board produces the liquid crystal control signal of the 3rd arithmetic unit.The direct input of T ' computing and W ' computing is respectively the operation result of T computing and W computing on first logic unit, respectively operand a in operand a and W ' the computing truth table in corresponding T ' the computing truth table.T computing liquid crystal control signal on the 3rd arithmetic unit is corresponding is the operand b in the truth table of T computing;
4, above-mentioned the 3rd arithmetic unit carries out the T computing on the 3rd liquid crystal and the 3rd forward and backward polaroid.The T computing directly be input as T ' computing on second logic unit operation result, the operand a in the corresponding T computing truth table.After the operation result that carries out the T computing on the 3rd logic unit decoded is exactly the result of additive operation.
The false add musical instruments used in a Buddhist or Taoist mass of above-mentioned three value optical computers realizes that the described truth table of the method for additive operation is following:
The logical operation truth table
Table is the T computing, W computing, the truth table of T ' computing and W ' computing.When carrying out the light path computing ,-1 corresponding vertical light in the table, 0 is corresponding unglazed, 1 corresponding horizon light.For the T computing; The W computing; The input of T ' computing and W ' computing and the span of operation result are that a and the b in-1,0 and 1. truth tables is one that carries out in two operands of logical operation; A row and b are capable to be the possible value of carrying out a positional operand of computing, and the value of two value intersections is operation results.For example a row are-1 in the T computing truth table, and b is capable to be-1 o'clock value-1 in the correspondence table, representes that the result that a positional operand-1 and-1 carries out the T computing is-1, and just importing the two-way vertical light, to carry out the result of T computing be vertical light.
Required liquid crystalline type of logical operation on first, second, third logic unit and number are following:
One positional operand of the T computing on first logic unit needs the liquid crystal of a VV type and a HH type; One positional operand of W computing needs the liquid crystal of a VH type and a HV type; T ' computing on second logic unit needs a HH type and a VV type liquid crystal; W ' computing needs a HH type and a VV type liquid crystal, and the T computing on the 3rd logic unit needs the liquid crystal of a HH type and a VV type.HV type liquid crystal dots is the flat type of polarization sheet of the front agio of liquid crystal dots, and the vertical type polaroid is pasted in the back; VH type liquid crystal dots is that the vertical type polaroid is pasted in the front of liquid crystal dots, the polaroid of the flat type of back agio.
W ' computing on second logic unit.Input light path a is the operation result of W logical operation on first logic unit.Truth table by W ' computing can be found out: have the input a be 0, b is 1, the operation result of W ' logical operation be 1 with the input a be 0, b is-1, the operation result of W ' logical operation is-1 situation.Each operand that is the W ' computing on the second logical operation device is built the compensation light path of another road horizon light and the compensation light path of another road vertical light respectively; Finding its input a when the program on the ARM development board is that unglazed operation result should be horizon light just 1 the time, just starts above-mentioned level compensation light path; If find that its input a is unglazed, operation result should be vertical light, just-1 o'clock, just starts above-mentioned VCP light path.
T computing on the 3rd logic unit.Input light path a is the operation result of T ' logical operation on second logic unit.By the truth table of T computing in the table 1 can find out have the input a be 0, b is 1, the operation result of T logical operation be 1 with the input a be 0, b is-1, the operation result of T logical operation is-1 situation.Each operand that is the T computing on the 3rd logical operation device is built the compensation light path of another road horizon light and the compensation light path of another road vertical light respectively; Finding its input a when the program on the ARM development board is that unglazed operation result should be horizon light just 1 the time, just starts above-mentioned level compensation light path; If find that its input a is unglazed, operation result should be vertical light just-1 o'clock, starts above-mentioned VCP light path.
From top additive operation, find out; The operation result of the T computing n-1 positional operand on first logic unit will be put on the n bit position of T operation result; The operation result of the n-1 positional operand of T ' computing will be put on the n bit position of T operation result on second logic unit, so just the contraposition problem between the data bit between each logic unit occurred.
As shown in Figure 2, the capable corresponding operand a that participates in additive operation of a* moves to left after two, and two 0 result is mended in the back, and indicating the number of the position of a1 putting is the actual correspondence primary lowest order in the right of operand a originally.The data bit of the operation result on capable corresponding first logic unit of T, the data bit of the operation result on corresponding second logic unit of T ' row, the data bit of the operation result of T computing on capable corresponding the 3rd logic unit of nethermost T.Ti representes the i position of T logical operation, and T ' i representes the i position of T ' logical operation.
The several the 3rd to be listed as physical location just be 3 position to Fig. 2 from the right; The direct input of T computing is the lowest order that a1 just participates in the operand a of additive operation; Control signal is the lowest order generation by the operand b that participates in additive operation; Its output is t2 the 2nd of T operation result just, and the operation result of several first a1 of T arithmetic operation is placed on second t2 of T operation result and just realizes t
i=T (x
I-1, y
I-1).For T ' computing, directly be input as the t2 as a result of T computing, control signal is by the result's of W computing the 2nd generation, and operation result is T ' 3 the 3rd of T ' operation result just, just realizes t '
i=T ' (t
I-1, w
I-1).T computing on the 3rd logic unit, its direct input is T ' 3, and control signal is produced by W ' among Fig. 43, and the output result is t3, realizes t
i=T (t '
i, w '
i).
Claims (1)
- One kind three the value optical computer the false add musical instruments used in a Buddhist or Taoist mass; It is characterized in that; This totalizer is between the encoder of three value optical computers; It comprises first logic unit connected in series successively, second logic unit, the 3rd logic unit, ARM development board, and first logic unit is made up of first liquid crystal, the first forward and backward polaroid, first photosensitive array, is used for accomplishing simultaneously T computing and the W computing that input light path is participated in; Second logic unit is made up of second liquid crystal, the second forward and backward polaroid, second photosensitive array, is used for accomplishing simultaneously T ' computing and the W ' computing that input light path is participated in; The 3rd logic unit is made up of the 3rd liquid crystal, the 3rd forward and backward polaroid, the 3rd photosensitive array, is used to accomplish the T computing that input light path is participated in, and realizes the disposable three value optical computer additions that need not carry; The ARM development board; Be used for the signal of input operand and photosensitive array output line is generated the liquid crystal control signal; Give liquid crystal with the liquid crystal control signal that generates; Above-mentioned first, second, third forward and backward polaroid is attached to the two sides, front and back of above-mentioned first, second, third liquid crystal respectively; Above-mentioned first, second, third photosensitive array is attached to respectively on above-mentioned first, second, third rear polarizer, and the control signal wire of first, second, third liquid crystal is connected with the ARM development board respectively with first, second, third photosensitive array output line.
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| CN110837354B (en) * | 2019-11-04 | 2023-07-14 | 上海大学 | MSD parallel adder based on three-value logic operator and construction method thereof |
| CN111045273B (en) * | 2020-01-06 | 2020-12-01 | 武汉大学 | Tri-value optical computer decoder based on super surface and design method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1363855A (en) * | 2002-01-30 | 2002-08-14 | 北京大学 | NOT gate and AND gate for optical logic operation |
| CN101834595A (en) * | 2010-05-04 | 2010-09-15 | 宁波大学 | Single-power clock clocked transmission gate ternary heat insulating circuit and T computing circuit |
-
2010
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1363855A (en) * | 2002-01-30 | 2002-08-14 | 北京大学 | NOT gate and AND gate for optical logic operation |
| CN101834595A (en) * | 2010-05-04 | 2010-09-15 | 宁波大学 | Single-power clock clocked transmission gate ternary heat insulating circuit and T computing circuit |
Non-Patent Citations (3)
| Title |
|---|
| 李国强，刘立人，邵岚.负二进制编码的光学阵列化复数运算.《光学学报》.1995,第15卷(第10期),第1409－1412页. * |
| 王先超,姚云飞,金.基于三值光计算机的并行无进位加法.《计算机科学》.2010,第37卷(第2期),第290-293页. * |
| 罗沛霖等.直接与亚直接逻辑原理在极高速运算中的应用.《前沿科学》.2008,第2卷(第02期),第8－9页. * |
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