CN101968960B - Multi-path audio real-time encoding and decoding hardware design platform based on FAAC and FAAD2 - Google Patents
Multi-path audio real-time encoding and decoding hardware design platform based on FAAC and FAAD2 Download PDFInfo
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- CN101968960B CN101968960B CN2010102877221A CN201010287722A CN101968960B CN 101968960 B CN101968960 B CN 101968960B CN 2010102877221 A CN2010102877221 A CN 2010102877221A CN 201010287722 A CN201010287722 A CN 201010287722A CN 101968960 B CN101968960 B CN 101968960B
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Abstract
The invention provides a multi-path audio real-time encoding and decoding hardware design platform based on an FAAC and an FAAD2, mainly comprising a multi-path real-time encoding subsystem, a multi-path real-time decoding subsystem, a power supply module, a peripheral circuit and a connector, wherein the multi-path real-time encoding subsystem comprises an analog operation-amplification input circuit, an ADC, an FPGA, a DSP and a flash, wherein the analog operation-amplification input circuit is responsible for converting analog audio signals into differential signals so as to meet the input requirement of the ADC, the ADC can complete four paths of analog-to-digital conversion simultaneously, the flash stores an AAC encoding program, the DSP operates the AAC encoding program, and the FPGA is responsible for communication with peripheral devices; and the multi-path real-time decoding subsystem comprises an analog operation-amplification output circuit, a DAC, an FPGA, a DSP and a flash, wherein the DAC can carry out analog-to-digital conversion on four paths of digital audio signals simultaneously, the signals output by the DAC are differential signals which are converted into the analog audio signals by the analog operation-amplification output circuit, the flash stores an AAC decoding program, the DSP operates the AAC decoding program, and the FPGA is responsible for communication with peripheral devices.
Description
Technical field
The present invention relates to a kind of MCVF multichannel voice frequency real time codec hardware designs platform based on FAAC and FAAD2, this hardware designs platform combines FAAC and FAAD2, can carry out multi-channel A AC audio coding decoding, belongs to the communications field.
Background technology
Advanced audio (Advanced Audio Coding; Be called for short AAC) be the sensing audio compression coding and decoding technology of new generation that on the MP3 basis, grows up; This technological synthesis the advantage of multiple main flow audio encoding and decoding technique; Have signal compression than high, reconstruction tonequality is good, characteristics such as encoding-decoding process high modularization and sound channel flexible configuration.
In practical application, often need the AAC codec can handle MCVF multichannel voice frequency simultaneously, to reach low-power consumption, purpose cheaply from different transmission links.
Summary of the invention
In order to realize AAC codec support MCVF multichannel voice frequency encoding and decoding, the invention provides a kind of MCVF multichannel voice frequency real time codec hardware designs platform based on FAAC and FAAD2.This hardware designs platform mainly comprises: multichannel real-time coding subsystem; Comprise simulation amplifier input circuit, modulus switching device (Analog to Digital Converter; Abbreviation ADC), field programmable gate array (Field Programmable Gate Array is called for short FPGA), digital signal processor (Digital Signal Processor is called for short DSP) and flash; Wherein simulating the amplifier input circuit is responsible for converting simulated audio signal into differential signal; To satisfy the input requirement of ADC, ADC can accomplish 4 tunnel analog to digital conversion simultaneously, flash storage AAC coded program; Dsp operation AAC coded program is responsible for by FPGA with communicating by letter between the peripheral components; Multichannel real-time decoding subsystem comprises simulation amplifier output circuit, digital-to-analog conversion device (Digital to Analog Converter is called for short DAC), FPGA, DSP and flash; Wherein DAC can carry out digital-to-analog conversion to 4 way word sound signals simultaneously; DAC output signal is a differential signal, converts differential signal into simulated audio signal through simulation amplifier output circuit, flash storage AAC decoding program; Dsp operation AAC decoding program is responsible for by FPGA with communicating by letter between the peripheral components; Power module; Peripheral circuit; Connector.This hardware designs platform comprises five parts composition:
One multichannel real-time coding subsystem; Comprise simulation amplifier input circuit, ADC, FPGA, DSP and flash, wherein simulate the amplifier input circuit and be responsible for converting simulated audio signal into differential signal, to satisfy the input requirement of ADC; ADC can accomplish 4 tunnel analog to digital conversion simultaneously; Flash storage AAC coded program, dsp operation AAC coded program is responsible for by FPGA with communicating by letter between the peripheral components;
Two multichannel real-time decoding subsystems; Comprise simulation amplifier output circuit, DAC, FPGA, DSP and flash, wherein DAC can carry out digital-to-analog conversion to 4 way word sound signals simultaneously, and DAC output signal is a differential signal; Convert differential signal into simulated audio signal through simulation amplifier output circuit; Flash storage AAC decoding program, dsp operation AAC decoding program is responsible for by FPGA with communicating by letter between the peripheral components;
Three power modules, outside input 5V digital power reaches ± the 12V analog power, through power conversion chip output digital power 1.2V, 1.5V, 3.3V, and analog power 5V and 5V reference data power supply;
Enclose circuit all round, LED light, reset circuit;
Five connectors; All elements of MCVF multichannel voice frequency real time codec hardware designs platform all are positioned on the same printed circuit board (PCB); And 32 pins and 20 pin connectors are installed on circuit board; 20 pin connectors are used for the input and output and the analog power input of analogue audio frequency, and 32 pin connectors are used for the input and output and the digital power input of AAC code stream.
Wherein, Described multichannel real-time coding subsystem: simulation amplifier input circuit is made up of 4 fully differential amplifier chip OPA1632 and 1 amplifier chip OPA2134 of TI company; Realization converts 4 road simulated audio signals into 4 road differential signals, and ADC adopts the PCM4204 of TI company, and FPGA adopts the Cyclone EP1C12F256C8N of altera corp; DSP adopts the TMS320C6727B of TI company, and flash adopts the S29GL512N of SPANSION company.
Wherein, Described multichannel real-time decoding subsystem: simulation amplifier output circuit is made up of 2 amplifier chip OPA2134 of TI company; Accomplish 4 road differential signals and convert 4 road simulated audio signals into, DAC adopts the PCM4104 of TI company, and FPGA adopts the Cyclone EP1C12F256C8N of altera corp; DSP adopts the TMS320C6727B of TI company, and flash adopts the S29GL512N of SPANSION company.
Wherein, Described power module: outside input 5V digital power; As the input of power integrated module PT6944A of TI company and PT6943A, PT6944A output 1.2V/6A and 3.3V/6A are the DSP power supply, and PT6943A output 1.5V/6A and 3.3V/6A are the FPGA power supply; Wherein 3.3V (does not comprise DSP for the components and parts of other 3.3V on the circuit board simultaneously; DSP is independently-powered by PT6944A) power supply, outside input ± 12V analog power is the power supply of amplifier OPA1632 and OPA2134, wherein+the 12V while is as the input of power conversion chip LT1085 of Linear Technology company and LTC6652; LT1085 output 5V/3A is as the analog power of ADC, DAC, and LTC6652 output 5V is as the reference data power supply of DAC.
Wherein, Described peripheral circuit: reset circuit is made up of the TPS3823-33Q of the TI company chip that resets; Its output, resets to FPGA, ADC, DAC, DSP and flash after FPGA receives reset signal as the input of FPGA in the multichannel real time codec subsystem.
The present invention is with the advantage that the prior art scheme is compared:
1, adopts the ADC and the DAC of low-power consumption, high sampling rate, high s/n ratio, four-way;
2, DSP only moves AAC encoding and decoding program, is responsible for by FPGA with communicating by letter of peripheral components.
Description of drawings
Fig. 1 is an one-piece construction block diagram of the present invention;
Fig. 2 is a simulation amplifier input circuit schematic diagram of the present invention;
Fig. 3 is a modulus switching device schematic diagram of the present invention;
Fig. 4 is FPGA of the present invention and ADC syndeton block diagram;
Fig. 5 is FPGA, DSP and a flash syndeton block diagram in the multichannel real-time coding subsystem of the present invention;
Fig. 6 is multichannel real time codec subsystem FPGA of the present invention and 32 pin connector syndeton block diagrams;
Fig. 7 is FPGA of the present invention and DAC syndeton block diagram;
Fig. 8 is a digital-to-analog conversion device schematic diagram of the present invention;
Fig. 9 is a simulation amplifier output circuit schematic diagram of the present invention;
Figure 10 is one of power module schematic diagram of the present invention: analog power;
Figure 11 is two of a power module schematic diagram of the present invention: digital power PT6944A;
Figure 12 is three of a power module schematic diagram of the present invention: digital power PT6943A;
Figure 13 is a reset circuit schematic diagram of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is further specified.
The invention provides a kind of MCVF multichannel voice frequency real time codec hardware designs platform based on FAAC and FAAD2.Referring to accompanying drawing 1, this hardware designs platform mainly comprises: multichannel real-time coding subsystem comprises simulation amplifier input circuit (102), ADC (103), FPGA (104), DSP (106) and flash (105); Wherein simulating the amplifier input circuit is responsible for converting simulated audio signal into differential signal; To satisfy the input requirement of ADC, ADC can accomplish 4 tunnel analog to digital conversion simultaneously, flash storage AAC coded program; Dsp operation AAC coded program is responsible for by FPGA with communicating by letter between the peripheral components; Multichannel real-time decoding subsystem; Comprise simulation amplifier output circuit (112), DAC (111), FPGA (108), DSP (110) and flash (109), wherein DAC can carry out digital-to-analog conversion to 4 way word sound signals simultaneously, and DAC output signal is a differential signal; Convert differential signal into simulated audio signal through simulation amplifier output circuit; Flash storage AAC decoding program, dsp operation AAC decoding program is responsible for by FPGA with communicating by letter between the peripheral components; Power module (114); Peripheral circuit (113); 20 pin connectors (101) and 32 pin connectors (107).
The 102nd, simulation amplifier input circuit of the present invention converts 4 road simulated audio signals into 4 road differential signals, satisfies the input requirement of ADC.Referring to accompanying drawing 2,3; Simulation amplifier input circuit is made up of 4 fully differential amplifier chip OPA1632 and 1 amplifier chip OPA2134; Every difference amplifier chip OPA1632 realizes the conversion of 1 road simulated audio signal to differential signal; Its output differential pair is imported linking to each other with the difference of ADC, and OPA2134 is responsible for common mode voltage to OPA1632 being provided, and its common mode voltage derives from the common mode voltage output of ADC.
The 103rd, ADC of the present invention can accomplish 4 tunnel analog to digital conversion, and has the characteristics of low-power consumption, high sampling rate, high s/n ratio.Referring to accompanying drawing 2,3,4 groups of output differential pairs of simulation amplifier input circuit and 4 groups of difference inputs of ADC are to linking to each other, and the reference data voltage of ADC is provided by himself.In the present invention, ADC works in holotype, and sampling rate is 44.1KHz; Data output format is 24bit serial digital audio-frequency bus agreement (Inter-IC Sound bus; Be called for short I2S), its major clock and configuration signal are provided by FPGA, and bit clock and frame synchronization clock are produced by ADC oneself.Referring to accompanying drawing 4; FPGA provides major clock SCKI=22.5792MHz to ADC; Through the configuration signal to ADC FS0=1, FS1=0, FS2=0 are set, ADC oneself produces bit clock BCK=5.6448MHz, frame synchronization clock LRCK=44.1KHz; Through configuration signal FMT0=1, FMT1=0, FMT2=0 are set, the data output format of ADC is 24bit I2S.
104,105 and 106 is nucleus modules of multichannel real-time coding subsystem of the present invention, flash storage AAC coded program, and dsp operation AAC coded program is responsible for by FPGA with communicating by letter between the peripheral components.Referring to accompanying drawing 5; DSP is through 32 external memory interface (External Memory Interface; Being called for short EMIF) bus and FPGA communicate, and on the hardware designs, need 32 EMIF data buss, EMIF be read clock, EMIF writes clock and asynchronous device chip selection signal links to each other with the IO of FPGA; For realizing correctly reading the purpose of multi-path audio-frequency data; 14 general I/O (General Purpose Input Output is called for short GPIO) of DSP are linked to each other with the IO of FPGA, be used for handshake communication each other.Flash and DSP communicate through 16 EMIF buses; On the hardware designs; Need low 16 position datawires of EMIF bus be connected with the data line of flash, low 13 bit address lines are connected with low 13 address wires of flash, and EMIF reads clock, EMIF writes the corresponding connection of clock.Because the address wire of EMIF bus has only 13, so the high 11 bit address lines of flash are expanded by FPGA, the chip selection signal of flash is controlled by FPGA equally.
The connection of DSP, flash and FPGA and multichannel real-time coding subsystem are just the same in the multichannel real-time decoding subsystem, do not explain at this.
The 107th, multichannel real time codec subsystem of the present invention sends the interface that receives the AAC code stream; Referring to accompanying drawing 6; After FPGA in the multichannel real-time coding subsystem receives the AAC code stream of DSP transmission; Through 32 pin connectors data are sent to transmission link, other AAC codec hardware platform just can obtain the AAC code stream through connecting 32 pin connectors; FPGA obtains by other AAC codec hardware platform through 32 pin connectors and is sent to the AAC code stream in the transmission link in the multichannel real-time decoding subsystem, then the AAC code stream is sent to DSP and decodes.
The 112nd, simulation amplifier output circuit of the present invention; Accomplish of the conversion of 4 road differential signals to 4 road simulated audio signals; Referring to accompanying drawing 8,9; Simulation amplifier output circuit is made up of 2 amplifier chip OPA2134, and every amplifier chip OPA2134 realizes the conversion of 2 road differential signals to simulated audio signal, and its input difference pair is exported differential pair with DAC and linked to each other.
The 111st, DAC of the present invention can accomplish the conversion of 4 way moulds, and have the characteristics of low-power consumption, high sampling rate, high s/n ratio.Referring to accompanying drawing 8,9,4 groups of differential pairs of simulation amplifier output circuit are exported being connected with 4 groups of difference of DAC, and its reference data voltage is provided by the LTC6652 in the power module.In the present invention, DAC works in from pattern, and sampling rate is 44.1KHz, data entry format 24bit I2S, and its major clock, bit clock, frame synchronization clock and configuration signal are provided by FPGA.Referring to accompanying drawing 7; FPGA provides major clock SCKI=22.5792MHz to ADC, bit clock BCK=5.6448MHz, frame synchronization clock LRCK=44.1KHz; Through configuration signal DEM0=0, DEM1=0, FS0=0, FS1=0 are set; DAC is operated under the 44.1KHz sampling rate pattern, and through configuration signal FMT0=1, FMT1=0, FMT2=0 are set, the data entry format that makes DAC is 24bit I2S.
The 114th, power module of the present invention; Referring to accompanying drawing 10,11 and 12, outside input 5V digital power is as the input of power integrated module PT6944A of TI company and PT6943A; PT6944A output 1.2V/6A and 3.3V/6A are the DSP power supply; PT6943A output 1.5V/6A and 3.3V/6A are the FPGA power supply, and wherein 3.3V supplies power for the components and parts (do not comprise DSP, DSP is independently-powered by PT6944A) of other 3.3V on the circuit board simultaneously; Outside input ± 12V analog power is amplifier OPA1632 and OPA2134 power supply; Wherein+and as the input of power conversion chip LT1085 of Linear Technology company and LTC6652, LT1085 output 5V/3A is as the analog power of ADC, DAC simultaneously for 12V, and LTC6652 output 5V is as the reference data power supply of DAC.
The 113rd, peripheral circuit of the present invention; Referring to accompanying drawing 13, reset circuit is made up of the TPS3823-33Q of the TI company chip that resets, and its output is as the input of FPGA in the multichannel real time codec subsystem; After FPGA receives reset signal, FPGA, ADC, DAC, DSP and flash are resetted.
The english abbreviation that occurs in the Figure of description, its implication is following:
Connector: connector;
I2S: serial digital audio-frequency bus agreement;
ADC: modulus switching device;
DAC: digital-to-analog conversion device;
FPGA: field programmable gate array;
DSP: digital signal processor;
R: resistance;
C: electric capacity;
FB: magnetic bead;
EMIF: external memory interface;
GPIO: general I/O.
Claims (5)
1. MCVF multichannel voice frequency real time codec hardware designs platform based on FAAC and FAAD2 is characterized in that: this hardware designs platform comprises that five parts form:
(1) multichannel real-time coding subsystem; Comprise simulation amplifier input circuit, ADC, FPGA, DSP and flash, wherein simulate the amplifier input circuit and be responsible for converting simulated audio signal into differential signal, to satisfy the input requirement of ADC; ADC can accomplish 4 tunnel analog to digital conversion simultaneously; Flash storage AAC coded program, dsp operation AAC coded program is responsible for by FPGA with communicating by letter between the peripheral components;
(2) multichannel real-time decoding subsystem; Comprise simulation amplifier output circuit, DAC, FPGA, DSP and flash, wherein DAC can carry out digital-to-analog conversion to 4 way word sound signals simultaneously, and DAC output signal is a differential signal; Convert differential signal into simulated audio signal through simulation amplifier output circuit; Flash storage AAC decoding program, dsp operation AAC decoding program is responsible for by FPGA with communicating by letter between the peripheral components;
(3) power module, outside input 5V digital power reaches ± the 12V analog power, through power conversion chip output digital power 1.2V, 1.5V, 3.3V, and analog power 5V and 5V reference data power supply;
(4) peripheral circuit, LED light, reset circuit;
(5) connector; All elements of MCVF multichannel voice frequency real time codec hardware designs platform all are positioned on the same printed circuit board (PCB); And 32 pins and 20 pin connectors are installed on circuit board; 20 pin connectors are used for the input and output and the analog power input of analogue audio frequency, and 32 pin connectors are used for the input and output and the digital power input of AAC code stream.
2. a kind of MCVF multichannel voice frequency real time codec hardware designs platform according to claim 1 based on FAAC and FAAD2; It is characterized in that: described multichannel real-time coding subsystem: simulation amplifier input circuit is made up of 4 fully differential amplifier chip OPA1632 and 1 amplifier chip OPA2134 of TI company; Realization converts 4 road simulated audio signals into 4 road differential signals; ADC adopts the PCM4204 of TI company; FPGA adopts the Cyclone EP1C12F256C8N of altera corp, and DSP adopts the TMS320C6727B of TI company, and flash adopts the S29GL512N of SPANSION company.
3. a kind of MCVF multichannel voice frequency real time codec hardware designs platform according to claim 1 based on FAAC and FAAD2; It is characterized in that: described multichannel real-time decoding subsystem: simulation amplifier output circuit is made up of 2 amplifier chip OPA2134 of TI company; Accomplish of the conversion of 4 road differential signals to 4 road simulated audio signals; DAC adopts the PCM4104 of TI company; FPGA adopts the Cyclone EP1C12F256C8N of altera corp, and DSP adopts the TMS320C6727B of TI company, and flash adopts the S29GL512N of SPANSION company.
4. a kind of MCVF multichannel voice frequency real time codec hardware designs platform according to claim 1 based on FAAC and FAAD2; It is characterized in that: described power module: outside input 5V digital power; Input as power integrated module PT6944A of TI company and PT6943A; PT6944A output 1.2V/6A and 3.3V/6A are the DSP power supply; PT6943A output 1.5V/6A and 3.3V/6A are the FPGA power supply, and wherein 3.3V supplies power for the components and parts (do not comprise DSP, DSP is independently-powered by PT6944A) of other 3.3V on the circuit board simultaneously; Outside input ± 12V analog power is the power supply of amplifier OPA1632 and OPA2134; Wherein+and as the input of power conversion chip LT1085 of Linear Technology company and LTC6652, LT1085 output 5V/3A is as the analog power of ADC, DAC simultaneously for 12V, and LTC6652 output 5V is as the reference data power supply of DAC.
5. a kind of MCVF multichannel voice frequency real time codec hardware designs platform according to claim 1 based on FAAC and FAAD2; It is characterized in that: described peripheral circuit: reset circuit is made up of the TPS3823-33Q of the TI company chip that resets; Its output is as the input of FPGA in the multichannel real time codec subsystem; After FPGA receives reset signal, FPGA, ADC, DAC, DSP and flash are resetted.
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| CN103064810B (en) * | 2011-10-18 | 2016-05-25 | 上海航天控制工程研究所 | A kind of method that realizes satellite serial communication |
| CN105047200A (en) * | 2015-07-21 | 2015-11-11 | 重庆邮电大学 | FPGA-based FLAC hardware decoder and decoding method |
| CN106297840A (en) * | 2016-07-30 | 2017-01-04 | 广州湖森电子科技有限公司 | A kind of digital audio processing system |
| CN109360574B (en) * | 2018-10-18 | 2022-06-21 | 恒玄科技(上海)股份有限公司 | Advanced audio coding/decoding method and system improved by wireless Bluetooth system |
| CN111261169A (en) * | 2020-01-08 | 2020-06-09 | 上海齐网网络科技有限公司 | Speech recognition chip based on multi-channel data processor |
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| JP3125543B2 (en) * | 1993-11-29 | 2001-01-22 | ソニー株式会社 | Signal encoding method and apparatus, signal decoding method and apparatus, and recording medium |
| JPH10124092A (en) * | 1996-10-23 | 1998-05-15 | Sony Corp | Method and device for encoding speech and method and device for encoding audible signal |
| CN1186909C (en) * | 2003-04-01 | 2005-01-26 | 西安大唐电信有限公司 | Multichannel interconnected vocoder and its realizing method |
| CN1595393A (en) * | 2003-12-22 | 2005-03-16 | 上海广电信息产业股份有限公司 | Real-time pre-processing software-hardware system for audio encoder interface and method and uses |
| CN101231850B (en) * | 2007-01-23 | 2012-02-29 | 华为技术有限公司 | Encoding/decoding device and method |
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