CN101968753A - Powder down memory circuit - Google Patents
Powder down memory circuit Download PDFInfo
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- CN101968753A CN101968753A CN2010105307380A CN201010530738A CN101968753A CN 101968753 A CN101968753 A CN 101968753A CN 2010105307380 A CN2010105307380 A CN 2010105307380A CN 201010530738 A CN201010530738 A CN 201010530738A CN 101968753 A CN101968753 A CN 101968753A
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Abstract
The invention discloses a power down memory circuit, comprising a detection chip IC1. The detection chip IC1 comprises an input and output terminal i/o1, an input and output terminal i/o2, an input and output terminal i/o3, an input and output terminal i/o4 and a reset terminal REST; wherein the input and output terminal i/o4 is connected with the collector electrode of an audion Q1, the base electrode of the audion Q1 is connected with a detection power supply V by a resistor R1, the connecting ends of the audion Q1 and the resistor R1 are grounded by a resistor R2; the emitting electrode of the audion Q1 is connected to the earth terminal of the resistor R2; a capacitor C1 is connected between the base electrode and the emitting electrode of the audion Q1 in a bridging mode; and the input and output terminal i/o1, the input and output terminal i/o2 and the input and output terminal i/o3 are respectively connected to an eighth pin, a fifth pin and a sixth pin of a memory chip IC2 and the other pins of the memory chip IC2 are grounded. The circuit of the invention has the characteristics of simple structure and convenient use.
Description
Technical field
The present invention relates to a kind of application circuit, be specifically related to a kind of power-failure memory circuit.
Background technology
Existing power-failure memory circuit is varied of a great variety, but most complex structure, the function complexity, and only need under the application scenario of function singleness at some, adopt the power-failure memory circuit of complicated circuit construction to finish the power-failure memory function of simple function often, cost can increase so on the one hand, in addition on the one hand, after circuit structure was in a single day complicated, its labile factor was behind so just reducing product percent of pass virtually also increasing.
Summary of the invention
For overcoming deficiency of the prior art, the object of the present invention is to provide a kind of power-failure memory circuit simple in structure.
In order to solve the problems of the technologies described above, realize above-mentioned purpose, the present invention has adopted following technical scheme:
A kind of power-failure memory circuit, comprise a detection chip IC1, described detection chip IC1 comprises input/output terminal i/o1, i/o2, i/o3, i/o4 and reset terminal REST, described input/output terminal i/o4 connects the collector of triode Q1, the base stage of described triode Q1 connects by a resistance R 1 and detects power supply V, the link of described triode Q1 and resistance R 1 is also by a resistance R 2 ground connection, the emitter of described triode Q1 is connected the earth terminal of described resistance R 2, cross-over connection one capacitor C 1 between the base stage of described triode Q1 and the emitter, described input/output terminal i/o1, i/o2 and i/o3 are connected to the 8th pin of a storage chip IC2, on the 5th pin and the 6th pin, first pin of described storage chip IC2, second pin, the 3rd pin, the 4th pin and the 7th pin interconnect back ground connection.
Further, described reset terminal REST is connected on the described input/output terminal i/o1 by a resistance R 3, described reset terminal REST and described resistance R 3 links also are connected on the described input/output terminal i/o1 by a diode D1, described reset terminal REST and described resistance R 3 links also are connected with a capacitor C 2, described capacitor C 2 connects a polar capacitor C3, described polar capacitor C3 is connected on the described input/output terminal i/o1, described capacitor C 2 and polar capacitor C3 link ground connection.
Further, cross-over connection resistance R 5 between described input/output terminal i/o1 and the input/output terminal i/o2.
Further, cross-over connection resistance R 4 between described input/output terminal i/o1 and the input/output terminal i/o3.
The course of work of power-failure memory circuit of the present invention is as follows:
Detect the base stage of power supply V by resistance R 1 to triode Q1, described triode Q1 conducting, input/output terminal i/o4 by detection chip IC1 has when checking, if detect power supply V power down, not conducting of then described triode Q1, the input/output terminal i/o4 of described detection chip IC1 does not have electricity when checking, this moment, storage chip IC2 preserved the preceding all parameter settings of power down.
The present invention has the following advantages:
Power-failure memory circuit structure of the present invention is simple, easy to use.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, below with preferred embodiment of the present invention and conjunction with figs. describe in detail as after.The specific embodiment of the present invention is provided in detail by following examples and accompanying drawing thereof.
Description of drawings
Fig. 1 is the circuit theory diagrams of power-failure memory circuit of the present invention.
Embodiment
Below in conjunction with drawings and Examples technology implementation process of the present invention is described further.
Referring to shown in Figure 1, a kind of power-failure memory circuit, comprise a detection chip IC1, described detection chip IC1 comprises input/output terminal i/o1, i/o2, i/o3, i/o4 and reset terminal REST, described input/output terminal i/o4 connects the collector of triode Q1, the base stage of described triode Q1 connects by a resistance R 1 and detects power supply V, the link of described triode Q1 and resistance R 1 is also by a resistance R 2 ground connection, the emitter of described triode Q1 is connected the earth terminal of described resistance R 2, cross-over connection one capacitor C 1 between the base stage of described triode Q1 and the emitter, described input/output terminal i/o1, i/o2 and i/o3 are connected to the 8th pin 8 of a storage chip IC2, on the 5th pin 5 and the 6th pin 6, first pin 1 of described storage chip IC2, second pin 2, the 3rd pin 3, the 4th pin 4 and the 7th pin 7 interconnect back ground connection.
Further, described reset terminal REST is connected on the described input/output terminal i/o1 by a resistance R 3, described reset terminal REST and described resistance R 3 links also are connected on the described input/output terminal i/o1 by a diode D1, described reset terminal REST and described resistance R 3 links also are connected with a capacitor C 2, described capacitor C 2 connects a polar capacitor C3, described polar capacitor C3 is connected on the described input/output terminal i/o1, described capacitor C 2 and polar capacitor C3 link ground connection.
Further, cross-over connection resistance R 5 between described input/output terminal i/o1 and the input/output terminal i/o2.
Further, cross-over connection resistance R 4 between described input/output terminal i/o1 and the input/output terminal i/o3.
The foregoing description just is to allow the one of ordinary skilled in the art can understand content of the present invention and enforcement according to this for technical conceive of the present invention and characteristics being described, its objective is, can not limit protection scope of the present invention with this.The variation or the modification of every equivalence that the essence of content has been done according to the present invention all should be encompassed in protection scope of the present invention.
Claims (4)
1. power-failure memory circuit, comprise a detection chip IC1, described detection chip IC1 comprises input/output terminal i/o1, i/o2, i/o3, i/o4 and reset terminal REST, described input/output terminal i/o4 connects the collector of triode Q1, the base stage of described triode Q1 connects by a resistance R 1 and detects power supply V, the link of described triode Q1 and resistance R 1 is also by a resistance R 2 ground connection, the emitter of described triode Q1 is connected the earth terminal of described resistance R 2, cross-over connection one capacitor C 1 between the base stage of described triode Q1 and the emitter, it is characterized in that: described input/output terminal i/o1, i/o2 and i/o3 are connected to the 8th pin (8) of a storage chip IC2, on the 5th pin (5) and the 6th pin (6), first pin (1) of described storage chip IC2, second pin (2), the 3rd pin (3), the 4th pin (4) and the 7th pin (7) interconnect back ground connection.
2. power-failure memory circuit according to claim 1, it is characterized in that: described reset terminal REST is connected on the described input/output terminal i/o1 by a resistance R 3, described reset terminal REST and described resistance R 3 links also are connected on the described input/output terminal i/o1 by a diode D1, described reset terminal REST and described resistance R 3 links also are connected with a capacitor C 2, described capacitor C 2 connects a polar capacitor C3, described polar capacitor C3 is connected on the described input/output terminal i/o1, described capacitor C 2 and polar capacitor C3 link ground connection.
3. power-failure memory circuit according to claim 1 is characterized in that: cross-over connection resistance R 5 between described input/output terminal i/o1 and the input/output terminal i/o2.
4. power-failure memory circuit according to claim 1 is characterized in that: cross-over connection resistance R 4 between described input/output terminal i/o1 and the input/output terminal i/o3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105307380A CN101968753A (en) | 2010-11-03 | 2010-11-03 | Powder down memory circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105307380A CN101968753A (en) | 2010-11-03 | 2010-11-03 | Powder down memory circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101968753A true CN101968753A (en) | 2011-02-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105307380A Pending CN101968753A (en) | 2010-11-03 | 2010-11-03 | Powder down memory circuit |
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| Country | Link |
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| CN (1) | CN101968753A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103235215A (en) * | 2013-04-08 | 2013-08-07 | 上海久创电气自动化设备有限公司 | Multi-functional instrument |
| CN108875881A (en) * | 2017-05-11 | 2018-11-23 | 展讯通信（上海）有限公司 | SIM card method for controlling power supply, device and mobile terminal |
-
2010
- 2010-11-03 CN CN2010105307380A patent/CN101968753A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103235215A (en) * | 2013-04-08 | 2013-08-07 | 上海久创电气自动化设备有限公司 | Multi-functional instrument |
| CN108875881A (en) * | 2017-05-11 | 2018-11-23 | 展讯通信（上海）有限公司 | SIM card method for controlling power supply, device and mobile terminal |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20110209 |