CN101958834A - On-chip network system supporting cache coherence and data request method - Google Patents
On-chip network system supporting cache coherence and data request method Download PDFInfo
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Abstract
The invention discloses an on-chip network system supporting cache coherence. The network system comprises a network interface part and a router, wherein the network interface part is connected with the router, a multi-core processor and a second level cache; a consistent state cache connected with the multi-core processor is additionally arranged in the network interface part and is used for storing and maintaining the consistent state of a data block in a first level cache of the multi-core processor; and an active directory cache connected with the second level cache is also additionally arranged in the network interface part and is used for caching and maintaining the directory information of the data block usually accessed by the first level cache. Coherence maintenance work is separated from the work of a processor, directory maintenance work is separated from the work of the second level cache, and the directory structure in the second level cache is eliminated, so that the design and the verification process of the multi-core processor are simplified, the storage cost of a chip is reduced, and the performance of the multi-core processor is improved. The invention also discloses a data request method of the system.
Description
Technical field
The present invention relates to the Computer Systems Organization technical field, particularly a kind of network-on-a-chip and request of data method of supporting the high-speed cache unanimity.
Background technology
Enter single-chip after 1,000,000,000 transistorized epoch, how the emphasis of architectural study makes full use of the processor that requirements such as high-performance, low-power consumption are satisfied in ever-increasing transistor resource design from how utilizing limited resources realization required function progressively to turn to.Polycaryon processor (Multicore processors) provides a kind of efficient, extendible scheme for effectively utilizing these transistor resources, and the heat that has been subjected to academia and industrial quarters is held in both hands.On one chips with integrated a plurality of (Multicore) or numerous (Manycore) processor cores, promptly extensive polycaryon processor.The main challenge that extensive polycaryon processor faces is design complexity, autgmentability and memory access delay etc.
Along with the increase of polycaryon processor scale, need that storage system provides lot of data for it on the sheet.For reducing the consideration that memory access postpones and reduces the programming complexity, polycaryon processor adopts storage system on the sheet of sharing Cache usually.Owing to comprise privately owned Cache usually in the processor core, in polycaryon processor, must use the Cache consistency protocol to safeguard the consistency and the integrality of data among the privately owned Cache.Along with the expansion of polycaryon processor scale, bus structures and based on the requirement that consistency protocol can't satisfy autgmentability of intercepting of bus.In order to address this problem, the consistency protocol of network-on-chip and catalogue is used to substitute bus and intercepts agreement.
The catalogue consistency protocol is a kind of basic communication mechanism of polycaryon processor, has guaranteed the consistency and the integrality of data in the polycaryon processor, and its realization is relevant with a plurality of parts:
1, processor core: the coherency state of in processor core, safeguarding privately owned Cache;
2, share Cache: in sharing Cache, preserve and maintenance directory information;
3, network-on-chip: network-on-chip provides the transmission service for consistency operation.
Because catalogue consistency protocol and processor, shared Cache and network-on-chip all are closely related, increased the difficulty of polycaryon processor design.
Heterogeneous multi-nucleus processor has obtained extensive use owing to the advantage of performance and power consumption in industrial quarters, as the Cell processor of IBM Corporation, and the Bulldozer processor of AMD etc.But the incompatibility problem that has consistency protocol in the heterogeneous multi-nucleus processor between the different processor nuclear, the support consistency protocol that has, what have does not support consistency protocol.PowerPC 755 processors as IBM Corporation are supported MEI (modified, exclusive, and invalid) agreement, the IA-32 series processors of INTEL Corp. is supported MESI (modified, exclusive, shared, and invalid) agreement, the Ultrasparc processor of SUN company is supported MOESI (exclusive modified, shared modified, exclusive clean, shared clean, andinvalid) agreement, AMD 64 series are supported MOESI (modified, owned, exclusive, shared, and invalid) agreement, but very big-difference is arranged with MOESI agreement that the Ultrasparc processor is supported.The DSP of TI company provides conforming simple functions between maintenance processor and the L2 cache.Some flush bonding processors such as MIPS 4K series though processors such as ARM 7 series comprise privately owned Cache, are not supported consistency protocol.Most of application specific processor and hardware-accelerated parts are not supported consistency protocol yet.Incompatible consistency protocol makes the heterogeneous multi-nucleus processor design difficult unusually.
Because consistency protocol and processor, shared Cache and network-on-chip all are closely related, incompatible consistency protocol in the heterogeneous multi-nucleus processor particularly, make when designing new polycaryon processor, each parts all need to redesign for maintaining coherency, reduce the reusability of parts, increased the difficulty of design.
Along with the expansion of polycaryon processor scale, there is serious scaling concern in the catalogue consistency protocol.In the consistency protocol based on catalogue, the storage of catalogue can take resource on a part of sheet.With full catalogue consistency protocol is example, and when the size of data block was 64B, the storage overhead of catalogue accounted for 3% of L2 cache storage overhead in the 16 nuclear polycaryon processors; When being increased to 64 nuclears, the ratio of directory stores expense is increased to 12.5%; When being increased to 512 nuclears, the ratio of directory stores expense is increased to 50%.Directory stores expense in the catalogue consistency protocol not only increases chip area and cost, has also increased the power consumption of system, has had a strong impact on the autgmentability of polycaryon processor.
In the catalogue consistency protocol, catalogue is generally held among the afterbody Cache (as the L2 cache in the two-stage Cache structure), and each data block in the L2 cache is all safeguarded a catalogue vector, in order to the processor of this data block of trace cache.All miss request of processor all need to search directory information in the L2 cache of host's node, and carry out corresponding consistency operation.Along with the expansion of processor scale,, have a strong impact on the performance of polycaryon processor to the also increase thereupon of access delay of catalogue.The catalogue consistency protocol also is the performance bottleneck of extensive polycaryon processor.
Summary of the invention
(1) technical problem that will solve
The technical problem to be solved in the present invention is the problem that consistency protocol brought in the polycaryon processor design complexity, catalogue are difficult to expand and access delay is bigger
(2) technical scheme
For solving the problems of the technologies described above, the invention provides a kind of network-on-a-chip of supporting the high-speed cache unanimity, comprise: network interface unit, described network interface unit connects router, and connection polycaryon processor and L2 cache, have additional the coherency state buffer memory that links to each other with polycaryon processor in described network interface unit, described coherency state buffer memory is used for preserving and safeguards the coherency state of level cache data block of each nuclear of polycaryon processor.
Wherein, described coherency state buffer memory comprises:
The coherency state memory has the storage line identical with described level cache, is used for preserving the coherency state of described level cache data block;
Processor interface, connect described polycaryon processor, be used for isolating the needed request signal of coherency state buffer memory, and the coherency state buffer memory is converted to the signal that polycaryon processor can be discerned to the response or the request signal of polycaryon processor from the bus request of dissimilar processor cores;
The consistency protocol controller, be used for when the level cache of polycaryon processor is visited miss request or receiveed the response through network interface unit, obtain this visit miss request or receive the response by described processor interface, therefrom isolate address tag, and safeguard corresponding coherency state.
Wherein, also have additional in the described network interface unit link to each other with L2 cache enliven the catalogue buffer memory, be used for buffer memory and safeguard the directory information of the data block that L2 cache is often visited by described level cache.
Wherein, the described catalogue buffer memory that enlivens comprises:
Catalog memory is used for the directory information of the data block that the buffer memory L2 cache often visited by described level cache: the address tag, directory states and the catalogue vector that comprise described data block;
The L2 cache interface connects L2 cache, is used for the visit miss request of polycaryon processor is sent to described L2 cache, or the back-signalling of L2 cache returned to enlivens the catalogue buffer memory;
The catalog control device is used for obtaining the access request of polycaryon processor to L2 cache by the L2 cache interface, and searches the directory information in the catalog memory, and whether the type decided according to request sends this access request to local L2 cache then.
The present invention also provides a kind of request of data method of utilizing above-mentioned system, may further comprise the steps:
S1: the consistency protocol controller of requesting node is caught the level cache visit miss request of described request modal processor,
S2: the consistency protocol controller of described request node is searched the address tag of described miss request in the coherency state memory, and sends request of data according to corresponding coherency state to the L2 cache of host's node;
S3: the catalog control device that enlivens the catalogue buffer memory in the network interface unit of described host's node router is caught described request of data, and in this catalog memory, search the directory information of described request of data correspondence, whether send described request of data according to the request type decision then to the L2 cache of this host's node;
S4: the L2 cache of described host's node according to described request of data to requesting node processor return messages, when the router of process requesting node, the consistency protocol controller of this router is caught this message, and store the coherency state of data in the address according to the type of message change or the address tag described in the state cache that keeps consistency, and the request msg that comprises in the message is returned to the requesting node processor.
Wherein, described step S2 specifically comprises: when described miss request is:
Read request operation: in the coherency state memory of the coherency state buffer memory of requesting node, be cache lines of this request address distribution, and coherency state is made as interim state I S, simultaneously transmit this request to the L2 cache of host's node, described interim state I S represents that read request also do not finish, and waits for the data response of this L2 cache;
Write request operation: if the coherency state buffer memory of requesting node does not hit, it then is cache lines of this address assignment, and coherency state is made as interim state I M, and transmit this write request to the L2 cache of host's node, described interim state I M represents that write request also do not finish, and waits for the response of writing of this L2 cache; If the coherency state cache hit of requesting node and be in shared state then is made as the IM state to coherency state, and sends to the L2 cache of host's node and to write update request; If the coherency state cache hit of requesting node and be in the modification state is then directly returned to the requesting node processor and write back-signalling, the state in the coherency state buffer memory does not change;
Update request operation: the coherency state in the coherency state buffer memory of requesting node is made as the IM state, sends update request to host's node then;
Replace and write back solicit operation: the coherency state buffer memory of requesting node directly is transmitted to this request the L2 cache of host's node;
Replacement operation: when the coherency state buffer memory of requesting node because during capacity conflict generation replacement operation, then send invalid signals to the requesting node processor, the privately owned level cache of requesting node processor then can send invalid response or write back message to host's node according to its state, after the coherency state buffer memory of requesting node receives the invalid response of requesting node processor or writes back message, L2 cache to host's node sends replacement or writes back request, the replacement of receiving host's node is by the time deleted this cache lines after responding or write back and receiveing the response from the coherency state buffer memory of requesting node.
Wherein, described step S3 specifically comprises: when described miss request is:
Read request operation: if host's node enliven the catalogue cache hit, the position of node joins request in enlivening the catalogue vector of directory information, if directory states is in shared state, then the L2 cache to this host's node sends read data request, after obtaining the data response of L2 cache, this data forwarding is given the processor of requesting node; If directory states is in the modification state, then send degradation and write back request to the shared node that has these data, when the catalog control device receives the data that write back, the data forwarding that writes back is given the processor of requesting node, and these data are write back the L2 cache of this host's node, directory states becomes shared state; If host's node enliven the catalogue cache miss, then add directory entry in enlivening the catalogue buffer memory, the L2 cache to this host's node sends read request then, after obtaining data in buffer and responding, the processor of the data forwarding of request to requesting node, directory states becomes shared state;
Write request operation: if the enlivening the catalogue cache hit and be in shared state of host's node, then the processor to all shared nodes sends invalid signals, and send read request to the L2 cache of this host's node, after the catalog control device is collected all invalid receiveing the response, the position of sharing node is accordingly deleted from the catalogue vector, the data response that returns from L2 cache is transmitted to the processor of requesting node, the directory states of enlivening the catalogue buffer memory of host's node is changed into the modification state, the position of the node that in the catalogue vector, joins request; If the catalogue buffer memory that enlivens of host's node is in the modification state, then send invalid and write back request to the processor of sharing node, when the catalog control device is received the data that write back, delete from the catalogue vector node corresponding position, give requesting node data forwarding, the position of the node that in the catalogue vector, joins request; If the catalogue buffer memory that enlivens of host's node does not hit, then in enlivening the catalogue buffer memory, add directory entry, L2 cache to this host's node sends read request, after obtaining the data response of L2 cache, give requesting node the data forwarding of request, directory states becomes the modification state, the position of the node that joins request in the catalogue vector;
The replacement request operation: delete from the catalogue vector of host's node requesting node position that will be to be replaced, and return the replacement back-signalling to this requesting node, if unique shared node is then deleted this catalogue vector from enlivening the catalogue buffer memory of host's node;
Write back solicit operation: node location is deleted, data are write back to the L2 cache of this host's node, and return to requesting node and to write back back-signalling, this catalogue vector is deleted from enlivening the catalogue buffer memory of host's node from the catalogue vector of host's node;
Replacement operation: during the enlivening the catalogue buffer memory and replace of host's node owing to capacity conflict, send invalidation request to all shared nodes, if the directory states of this catalog memory is in shared state, after then the catalog control device is collected all invalid responses, this catalogue vector is deleted from enliven the catalogue buffer memory; If this catalog memory directory states is in the modification state, after then the catalog control device is received the data that write back, these data are write back in the L2 cache of this host's node, delete the catalogue vector of this data correspondence then;
When receiving the invalidation request of L2 cache of host's node, if the catalogue buffer memory that enlivens of this node does not hit, then directly return invalid back-signalling to L2 cache, if enliven the catalogue cache hit, then enliven the replacement operation of catalogue buffer memory, after replacement operation is finished, return invalid back-signalling or write back signal, the catalogue vector is deleted from enliven the catalogue buffer memory to L2 cache.
Wherein, described step S4 specifically comprises: when the response of described miss request correspondence is operating as:
Read back and should operate: the IS state of the coherency state buffer memory of requesting node is changed into shared state, and to requesting node processor return data;
Write and respond and upgrade and respond operation: the IM state of the coherency state buffer memory of requesting node is changed into the modification state, and return to write to the requesting node processor and respond or upgrade and respond;
Replace to respond and write back and respond operation: the cache lines at this place, address in the coherency state buffer memory of removal request node, and back-signalling is transmitted to the requesting node processor;
Invalidation request operation: when the coherency state buffer memory of requesting node receives from the invalidation request of host's node L2 cache, directly be transmitted to the requesting node processor;
Invalid response operation: when the coherency state buffer memory of requesting node receives from the invalid back-signalling of requesting node processor, deletion corresponding cache row, and invalid back-signalling forwarding host node.
(3) beneficial effect
The network-on-a-chip of the support high-speed cache unanimity that the present invention proposes is by integrated coherency state buffer memory in the network interface unit of network-on-chip and enliven the catalogue buffer memory, consistency maintenance work is separated from processor, directory maintenance work is separated from L2 cache, and cancelled the bibliographic structure in the L2 cache, the design and the proof procedure of polycaryon processor have been simplified, reduce the storage and the time-delay expense of chip, improved the performance of polycaryon processor.
Description of drawings
Fig. 1 is the network-on-a-chip structural representation of the support high-speed cache unanimity of the embodiment of the invention;
Fig. 2 is a coherency state buffer structure schematic diagram in the network-on-a-chip of support high-speed cache unanimity of the embodiment of the invention;
Fig. 3 is the structural representation that enlivens the catalogue buffer memory in the network-on-a-chip of support high-speed cache unanimity of the embodiment of the invention;
Fig. 4 is the request of data method flow diagram of the above-mentioned system of utilizing of the embodiment of the invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples are used to illustrate the present invention, but are not used for limiting the scope of the invention.
In polycaryon processor, the operation of buffer consistency agreement is transmitted by network-on-chip.Privately owned buffer memory (level cache) miss request of polycaryon processor sends in the network-on-chip by network interface unit, and echo message also is transferred to the router of requesting node by network-on-chip, return to polycaryon processor by network interface unit again.Visit to catalogue and data in the shared L2 cache is also transmitted by network interface unit.Share L2 cache to the receiveing the response and the invalid message of privately owned buffer memory is injected into network-on-chip by network interface unit of polycaryon processor, be transferred to corresponding polycaryon processor.Network interface unit can obtain all the consistency protocol operations in the system, and makes further processing.
For the coherency state maintenance work is separated from processor, the present invention has increased a coherency state buffer memory in network interface unit, as shown in Figure 1, described coherency state buffer memory is used for preserving and safeguarding the coherency state of local privately owned level cache data block, and the level cache of polycaryon processor is worked by the mode of oneself, needn't be concerned about consistency maintenance work.By the coherency state buffer memory, realized separating of consistency protocol and processor, compatibility has the polycaryon processor of different consistencies agreement.
As shown in Figure 2, above-mentioned coherency state buffer memory comprises:
The coherency state memory has the storage line identical with described level cache, and address tag that stores level cache and coherency state in the storage line are used for preserving the coherency state of described level cache data block.
Processor interface, connect described polycaryon processor, be used for isolating the needed request signal of coherency state buffer memory, and the coherency state buffer memory is converted to the signal that polycaryon processor can be discerned to the response or the request signal of polycaryon processor from the bus request of dissimilar processor cores.
The consistency protocol controller, be used for when the level cache of polycaryon processor is visited miss request or receiveed the response through network interface unit, obtain this access request or receive the response by described processor interface, therefrom isolate address tag, and safeguard corresponding coherency state.
For directory stores and maintenance work are separated from L2 cache, also have additional in the network interface unit link to each other with L2 cache enliven the catalogue buffer memory, as shown in Figure 1, enliven the directory information that the catalogue buffer memory is used for buffer memory and safeguards the data block that L2 cache is often visited by level cache.Cancel directory stores space and directory maintenance work in the L2 cache simultaneously.Enliven the catalogue buffer memory and reduced the directory stores expense, realized separating of consistency protocol and L2 cache.Enliven the catalogue buffer memory and also reduced the directory access delay, the performance of system is increased.
As shown in Figure 3, the above-mentioned catalogue buffer memory that enlivens comprises:
Catalog memory is used for the directory information of the data block that the buffer memory L2 cache often visited by described level cache, and each storage line is made up of address tag, directory states and the catalogue vector etc. of described data block.The purpose of catalogue vector is the position of the level cache of this address of trace cache.Keep a shared position for each processor core that comprises privately owned level cache in the catalogue vector.
The L2 cache interface connects L2 cache, and the miss request of polycaryon processor is used for the visit miss request of polycaryon processor is sent to described L2 cache after visit enlivens the catalogue buffer memory, or the back-signalling of L2 cache returned to enlivens the catalogue buffer memory.
The catalog control device is used for obtaining the access request of polycaryon processor to L2 cache by the L2 cache interface, and searches the directory information in the catalog memory, and whether the type decided according to request sends this access request to local L2 cache then.
With respect to traditional network-on-chip, in the network-on-a-chip structure of supporting the high-speed cache unanimity, increased the coherency state buffer memory and enlivened the catalogue buffer memory.They all are implemented in the network interface unit of network-on-chip.The coherency state buffer memory is the interface of router and processor, enlivens the interface that the catalogue buffer memory is router and L2 cache.Coherency state safeguard and directory maintenance work respectively by the coherency state buffer memory with enliven the catalogue buffer memory and finish.The major function of network interface unit is that the data that send are packed and the data that receive are unpacked processing.Coherency state buffer memory and enliven the packing of catalogue buffer memory and network interface and unpack the parts concurrent working has been hidden the coherency state buffer memory and has been enlivened the access delay of catalogue buffer memory.Such design does not change the structure of router, and topological structure and routing algorithm are not all had influence, has increased adaptability and the flexibility of supporting the network-on-chip structure of high-speed cache unanimity.The present invention supports polycaryon processor to be directly connected in the network-on-chip by supporting the consistent network-on-chip structure of high-speed cache with L2 cache, realizes the seamless integrated of polycaryon processor, and consistency protocol is transparent to polycaryon processor and L2 cache.
The invention also discloses a kind of request of data method of utilizing above-mentioned system, this method can make the L2 cache request msg of the host node of processor on network of requesting node, the described request node is meant the computer node at the processor place of sending request of data, and described host's node is meant the computer node on the network at the L2 cache place of preserving these data.As shown in Figure 4, comprising:
Step S401, the consistency protocol controller of described request node catch the level cache visit miss request of described request modal processor.
Step S402, the consistency protocol controller of described request node is searched the address tag of described miss request in the coherency state memory, and sends request of data according to corresponding coherency state to the L2 cache of host's node.
Step S403, enliven the catalog control device of catalogue buffer memory in the network interface unit of described host's node router and catch described request of data, and in described catalog memory, search the directory information of described request of data correspondence, whether send described request of data according to the request type decision then to the L2 cache of this host's node.
Step S404, the L2 cache of described host's node according to described request of data to described request modal processor return messages, when the router of process requesting node, the consistency protocol controller of this router is caught this message, and store the coherency state of data in the address according to the type of message change or the address tag described in the state cache that keeps consistency, and the request msg that comprises in the message is returned to the requesting node processor.
Of the present invention connecting internet system operation principle is as follows:
In the network-on-a-chip of above-mentioned support high-speed cache unanimity, during the memory access miss request of processor process network interface unit, enter the coherency state buffer memory.The consistency protocol controller is at first searched the address tag of level cache request address in the coherency state buffer memory, and according to corresponding coherency state information, sends request to the L2 cache of host's node.If this address tag not in the coherency state buffer memory then adds this address tag.L2 cache returns to receiveing the response of this polycaryon processor and is intercepted and captured by the consistency protocol controller, the consistency protocol controller is according to the type of receiveing the response, change or keep coherency state in the coherency state buffer memory, simultaneously, give polycaryon processor the data forwarding of request, finish single treatment device disappearance accessing operation.L2 cache is is also intercepted and captured by the consistency protocol controller the data block invalidation request of polycaryon processor and invalid the receiveing the response of polycaryon processor, and coherency state is changed accordingly.Concrete consistency protocol operation is as follows:
Read request operation: in the coherency state memory of the coherency state buffer memory of requesting node, be cache lines of this request address distribution, and coherency state is made as the IS state, and (IS is a kind of interim state, the expression read request is not also finished, wait for the data response of this L2 cache), and transmit this request to the L2 cache of host's node.
Write request operation: if the coherency state buffer memory of requesting node does not hit, it then is cache lines of this address assignment, and coherency state is made as the IM state, and (IM also is a kind of interim state, the expression write request is not also finished, wait for the response of writing of this L2 cache), and transmit this write request to the L2 cache of host's node; If the coherency state cache hit of requesting node and be in shared (S) state then is made as the IM state to coherency state, and sends to host's node and to write renewals (Update) and ask; If the coherency state cache hit of requesting node and be in modification (M) state is then directly returned to the requesting node processor and write back-signalling, the state in the coherency state buffer memory does not change.
Update request operation: the coherency state in the coherency state buffer memory of requesting node is made as the IM state, sends update request to host's node then.When receiving the update request of polycaryon processor, the coherency state buffer memory should be in shared (S) state.
Replace and write back solicit operation: the coherency state buffer memory of requesting node directly is transmitted to this request the L2 cache of host's node.When receiving the replacement request of polycaryon processor, the coherency state buffer memory should be in shared (S) state.When request of writing back that receives polycaryon processor, the coherency state buffer memory should be in modification (M) state.
Read back and should operate: the IS state of the coherency state buffer memory of requesting node is changed into shared (S) state, and to requesting node processor return data.
Write and respond and upgrade and respond operation: the IM state of the coherency state buffer memory of requesting node is changed into modifications (M) state, and return to write to the requesting node processor and respond or upgrade response.
Replace to respond and write back and respond operation: the cache lines at this place, address in the coherency state buffer memory of removal request node, and back-signalling is transmitted to the requesting node processor.
Invalidation request operation: when the coherency state buffer memory of requesting node receives from the invalidation request of host's node L2 cache, directly be transmitted to the requesting node processor.
Invalid response operation: when the coherency state buffer memory of requesting node receives from the invalid back-signalling of polycaryon processor, deletion corresponding cache row, and invalid back-signalling forwarding host node.
Replacement operation: when the coherency state buffer memory of requesting node because during capacity conflict generation replacement operation, then send invalid signals to the requesting node processor, the privately owned level cache of requesting node processor then can send invalid response or write back message to host's node according to its state.After the coherency state buffer memory of requesting node receives the invalid response of requesting node processor or writes back message, send replacement or write back request to host's node.The replacement of receiving host's node is by the time deleted this cache lines after responding or write back and receiveing the response from the coherency state buffer memory of requesting node.
In the network-on-a-chip of above-mentioned support high-speed cache unanimity, enliven the catalogue buffer memory and preserve recently the often directory information of the data of visit.The read-write miss request of all polycaryon processors all can cause the visit to host's node L2 cache, and these visits are caught by the catalogue buffer memory that enlivens on the network interface.The catalog control device that enlivens in the catalogue buffer memory is at first searched directory information in the catalog memory that enlivens the catalogue buffer memory, and whether the type decided according to request sends read-write requests to local L2 cache then.Its course of work is as follows:
Read request operation: if host's node enliven the catalogue cache hit, the position of node joins request in the catalogue vector, if directory states is in shared (S) state, then the L2 cache to this host's node sends read data request, after obtaining the data response of L2 cache, the processor of this data forwarding, finish read operation to requesting node.If directory states is in modification (M) state, then send degradation and write back request to the shared node that has these data, when the catalog control device receives the data that write back, the data forwarding that writes back is given the processor of requesting node, and these data are write back the L2 cache of this host's node, directory states becomes shared (S) state.If this host's node enliven the catalogue cache miss, then in enlivening the catalogue buffer memory, add directory entry, L2 cache to this host's node sends read request then, after obtaining the data in buffer response, give the processor of requesting node the data forwarding of request, directory states becomes shared (S) state.
Write request operation: if the enlivening the catalogue cache hit and be in shared (S) state of host's node, then the processor to all shared nodes sends invalid signals, and sends read request to the L2 cache of this host's node.Write request in fact also is a read operation, and this is at a word because of write command, and read-write requests is all capable at a Cache, when carrying out write request, need all read the capable data of Cache, deliver to requesting node, to merge into a new Cache capable with the content that writes.After the catalog control device is collected all invalid receiveing the response, the corresponding node location of sharing is deleted from the catalogue vector, the data response that returns from L2 cache is transmitted to the processor of requesting node, the state of the catalogue of enlivening the catalogue buffer memory of host's node is changed into modification (M) state, the position of the node that joins request in the catalogue vector.If the catalogue buffer memory that enlivens of host's node is in modification (M) state, then send invalid and write back request to the processor of sharing node, be unique correct copy because at this moment share the copy of the preservation of node, need write back.When the catalog control device was received the data that write back, deleted from the catalogue vector node corresponding position, gives requesting node data forwarding, the position of the node that joins request in the catalogue vector.If the catalogue buffer memory that enlivens of host's node does not hit, then in enlivening the catalogue buffer memory, add directory entry, L2 cache to this host's node sends read request, after obtaining the data response of L2 cache, give requesting node the data forwarding of request, directory states becomes modification (M) state, the position of the node that joins request in the catalogue vector.
The replacement request operation: delete from the catalogue vector requesting node position that will be to be replaced, and return the replacement back-signalling to requesting node.If unique shared node is then deleted this catalogue vector from enlivening the catalogue buffer memory of host's node.
Write back solicit operation: node location is deleted, data are write back to the L2 cache of this host's node, and return to requesting node and to write back back-signalling, then this catalogue vector is deleted from enlivening the catalogue buffer memory of host's node from the catalogue vector of host's node.
Replacement operation: during the enlivening the catalogue buffer memory and replace of host's node, send invalidation request to all shared nodes owing to capacity conflict.If the directory states of this catalog memory is in shared (S) state after then the catalog control device is collected all invalid responses, is deleted this catalogue vector from enliven the catalogue buffer memory.If the directory states of this catalog memory is in modification (M) state, after then the catalog control device is received the data that write back, these data are write back in the L2 cache of this host's node, delete the catalogue vector of this data correspondence then.
When receiving the invalidation request of L2 cache of host's node, do not hit, then directly return invalid back-signalling to L2 cache if this node enlivens the catalogue buffer memory.If enliven the catalogue cache hit, then enliven the replacement operation of catalogue buffer memory, after replacement operation is finished, return invalid back-signalling or write back signal to L2 cache, the catalogue vector is deleted from enliven the catalogue buffer memory.
Above execution mode only is used to illustrate the present invention; and be not limitation of the present invention; the those of ordinary skill in relevant technologies field; under the situation that does not break away from the spirit and scope of the present invention; can also make various variations and modification; therefore all technical schemes that are equal to also belong to category of the present invention, and scope of patent protection of the present invention should be defined by the claims.
Claims (8)
1. network-on-a-chip of supporting the high-speed cache unanimity, comprise: network interface unit, described network interface unit connects router, and connection polycaryon processor and L2 cache, it is characterized in that, have additional the coherency state buffer memory that links to each other with polycaryon processor in described network interface unit, described coherency state buffer memory is used for preserving and safeguards the coherency state of level cache data block of each nuclear of polycaryon processor.
2. the network-on-a-chip of support high-speed cache unanimity as claimed in claim 1 is characterized in that, described coherency state buffer memory comprises:
The coherency state memory has the storage line identical with described level cache, is used for preserving the coherency state of described level cache data block;
Processor interface, connect described polycaryon processor, be used for isolating the needed request signal of coherency state buffer memory, and the coherency state buffer memory is converted to the signal that polycaryon processor can be discerned to the response or the request signal of polycaryon processor from the bus request of dissimilar processor cores;
The consistency protocol controller, be used for when the level cache of polycaryon processor is visited miss request or receiveed the response through network interface unit, obtain this visit miss request or receive the response by described processor interface, therefrom isolate address tag, and safeguard corresponding coherency state.
3. the network-on-a-chip of support high-speed cache unanimity as claimed in claim 2, it is characterized in that, also have additional in the described network interface unit link to each other with L2 cache enliven the catalogue buffer memory, be used for buffer memory and safeguard the directory information of the data block that L2 cache is often visited by described level cache.
4. the network-on-a-chip of support high-speed cache unanimity as claimed in claim 3 is characterized in that, the described catalogue buffer memory that enlivens comprises:
Catalog memory is used for the directory information of the data block that the buffer memory L2 cache often visited by described level cache: the address tag, directory states and the catalogue vector that comprise described data block;
The L2 cache interface connects L2 cache, is used for the visit miss request of polycaryon processor is sent to described L2 cache, or the back-signalling of L2 cache returned to enlivens the catalogue buffer memory;
The catalog control device is used for obtaining the access request of polycaryon processor to L2 cache by the L2 cache interface, and searches the directory information in the catalog memory, and whether the type decided according to request sends this access request to local L2 cache then.
5. a request of data method of utilizing the described system of claim 4 is characterized in that, may further comprise the steps:
S1: the consistency protocol controller of requesting node is caught the level cache visit miss request of described request modal processor,
S2: the consistency protocol controller of described request node is searched the address tag of described miss request in the coherency state memory, and sends request of data according to corresponding coherency state to the L2 cache of host's node;
S3: the catalog control device that enlivens the catalogue buffer memory in the network interface unit of described host's node router is caught described request of data, and in this catalog memory, search the directory information of described request of data correspondence, whether send described request of data according to the request type decision then to the L2 cache of this host's node;
S4: the L2 cache of described host's node according to described request of data to requesting node processor return messages, when the router of process requesting node, the consistency protocol controller of this router is caught this message, and store the coherency state of data in the address according to the type of message change or the address tag described in the state cache that keeps consistency, and the request msg that comprises in the message is returned to the requesting node processor.
6. request of data method as claimed in claim 5 is characterized in that, described step S2 specifically comprises: when described miss request is:
Read request operation: in the coherency state memory of the coherency state buffer memory of requesting node, be cache lines of this request address distribution, and coherency state is made as interim state I S, simultaneously transmit this request to the L2 cache of host's node, described interim state I S represents that read request also do not finish, and waits for the data response of this L2 cache;
Write request operation: if the coherency state buffer memory of requesting node does not hit, it then is cache lines of this address assignment, and coherency state is made as interim state I M, and transmit this write request to the L2 cache of host's node, described interim state I M represents that write request also do not finish, and waits for the response of writing of this L2 cache; If the coherency state cache hit of requesting node and be in shared state then is made as the IM state to coherency state, and sends to the L2 cache of host's node and to write update request; If the coherency state cache hit of requesting node and be in the modification state is then directly returned to the requesting node processor and write back-signalling, the state in the coherency state buffer memory does not change;
Update request operation: the coherency state in the coherency state buffer memory of requesting node is made as the IM state, sends update request to host's node then;
Replace and write back solicit operation: the coherency state buffer memory of requesting node directly is transmitted to this request the L2 cache of host's node;
Replacement operation: when the coherency state buffer memory of requesting node because during capacity conflict generation replacement operation, then send invalid signals to the requesting node processor, the privately owned level cache of requesting node processor then can send invalid response or write back message to host's node according to its state, after the coherency state buffer memory of requesting node receives the invalid response of requesting node processor or writes back message, L2 cache to host's node sends replacement or writes back request, the replacement of receiving host's node is by the time deleted this cache lines after responding or write back and receiveing the response from the coherency state buffer memory of requesting node.
7. request of data method as claimed in claim 5 is characterized in that, described step S3 specifically comprises: when described miss request is:
Read request operation: if host's node enliven the catalogue cache hit, the position of node joins request in enlivening the catalogue vector of directory information, if directory states is in shared state, then the L2 cache to this host's node sends read data request, after obtaining the data response of L2 cache, this data forwarding is given the processor of requesting node; If directory states is in the modification state, then send degradation and write back request to the shared node that has these data, when the catalog control device receives the data that write back, the data forwarding that writes back is given the processor of requesting node, and these data are write back the L2 cache of this host's node, directory states becomes shared state; If host's node enliven the catalogue cache miss, then add directory entry in enlivening the catalogue buffer memory, the L2 cache to this host's node sends read request then, after obtaining data in buffer and responding, the processor of the data forwarding of request to requesting node, directory states becomes shared state;
Write request operation: if the enlivening the catalogue cache hit and be in shared state of host's node, then the processor to all shared nodes sends invalid signals, and send read request to the L2 cache of this host's node, after the catalog control device is collected all invalid receiveing the response, the position of sharing node is accordingly deleted from the catalogue vector, the data response that returns from L2 cache is transmitted to the processor of requesting node, the directory states of enlivening the catalogue buffer memory of host's node is changed into the modification state, the position of the node that in the catalogue vector, joins request; If the catalogue buffer memory that enlivens of host's node is in the modification state, then send invalid and write back request to the processor of sharing node, when the catalog control device is received the data that write back, delete from the catalogue vector node corresponding position, give requesting node data forwarding, the position of the node that in the catalogue vector, joins request; If the catalogue buffer memory that enlivens of host's node does not hit, then in enlivening the catalogue buffer memory, add directory entry, L2 cache to this host's node sends read request, after obtaining the data response of L2 cache, give requesting node the data forwarding of request, directory states becomes the modification state, the position of the node that joins request in the catalogue vector;
The replacement request operation: delete from the catalogue vector of host's node requesting node position that will be to be replaced, and return the replacement back-signalling to this requesting node, if unique shared node is then deleted this catalogue vector from enlivening the catalogue buffer memory of host's node;
Write back solicit operation: node location is deleted, data are write back to the L2 cache of this host's node, and return to requesting node and to write back back-signalling, this catalogue vector is deleted from enlivening the catalogue buffer memory of host's node from the catalogue vector of host's node;
Replacement operation: during the enlivening the catalogue buffer memory and replace of host's node owing to capacity conflict, send invalidation request to all shared nodes, if the directory states of this catalog memory is in shared state, after then the catalog control device is collected all invalid responses, this catalogue vector is deleted from enliven the catalogue buffer memory; If this catalog memory directory states is in the modification state, after then the catalog control device is received the data that write back, these data are write back in the L2 cache of this host's node, delete the catalogue vector of this data correspondence then;
When receiving the invalidation request of L2 cache of host's node, if the catalogue buffer memory that enlivens of this node does not hit, then directly return invalid back-signalling to L2 cache, if enliven the catalogue cache hit, then enliven the replacement operation of catalogue buffer memory, after replacement operation is finished, return invalid back-signalling or write back signal, the catalogue vector is deleted from enliven the catalogue buffer memory to L2 cache.
8. request of data method as claimed in claim 5 is characterized in that, described step S4 specifically comprises: when the response of described miss request correspondence is operating as:
Read back and should operate: the IS state of the coherency state buffer memory of requesting node is changed into shared state, and to requesting node processor return data;
Write and respond and upgrade and respond operation: the IM state of the coherency state buffer memory of requesting node is changed into the modification state, and return to write to the requesting node processor and respond or upgrade and respond;
Replace to respond and write back and respond operation: the cache lines at this place, address in the coherency state buffer memory of removal request node, and back-signalling is transmitted to the requesting node processor;
Invalidation request operation: when the coherency state buffer memory of requesting node receives from the invalidation request of host's node L2 cache, directly be transmitted to the requesting node processor;
Invalid response operation: when the coherency state buffer memory of requesting node receives from the invalid back-signalling of requesting node processor, deletion corresponding cache row, and invalid back-signalling forwarding host node.
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| CN115514772A (en) * | 2022-11-15 | 2022-12-23 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device and equipment for realizing cache consistency and readable medium |
| CN115514772B (en) * | 2022-11-15 | 2023-03-10 | 山东云海国创云计算装备产业创新中心有限公司 | Method, device and equipment for realizing cache consistency and readable medium |
| WO2024103907A1 (en) * | 2022-11-15 | 2024-05-23 | 山东云海国创云计算装备产业创新中心有限公司 | Method and apparatus for achieving cache consistency, device, and readable medium |
| CN116167310A (en) * | 2023-04-25 | 2023-05-26 | 上海芯联芯智能科技有限公司 | Method and device for verifying cache consistency of multi-core processor |
| CN118260304A (en) * | 2024-05-29 | 2024-06-28 | 山东云海国创云计算装备产业创新中心有限公司 | Request processing method, device, equipment and medium based on cache consistency directory |
| CN118260304B (en) * | 2024-05-29 | 2024-08-13 | 山东云海国创云计算装备产业创新中心有限公司 | Request processing method, device, equipment and medium based on cache consistency directory |
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