CN101958701B - outage delay circuit, method and sound system with outage delay - Google Patents
outage delay circuit, method and sound system with outage delay Download PDFInfo
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- CN101958701B CN101958701B CN200910151668.5A CN200910151668A CN101958701B CN 101958701 B CN101958701 B CN 101958701B CN 200910151668 A CN200910151668 A CN 200910151668A CN 101958701 B CN101958701 B CN 101958701B
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- voltage
- external power
- feed end
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Abstract
The invention relates to an outage delay circuit which is characterized by comprising an external power input end, an internal power supply end, a capacitor which is connected with the internal power supply end, a switch which is connected between the external power input end and the internal power supply end, and a hysteresis comparator which is provided with a first input end to connect with the external power input end, a second input end to connect the internal power supply end, and an output end to generate a control signal for controlling the switch. The switch is turned on under a first state to connect the external power input end to the internal power supply end, and is turned off under a second state.
Description
Technical field
The present invention relates to a kind of power-off delay circuit and method, specifically, is a kind of power-off delay circuit and method for sound system.
background technology
For avoiding loud speaker to produce sonic boom (pop) in the time that sound system is opened and closed, known technology uses message noise reduction (audio mute) integrated circuit (IC) to eliminate sonic boom.But in the time of power-off, message noise reduction IC lacks enough large supply voltage and supports that its internal circuit correctly operates, and is therefore difficult to maintain its silencing function.For head it off, must holding time at the supply voltage of power-off time delay long news noise reduction IC, its internal circuit still can normally be worked a period of time after power-off, allow the quiet Function effect of source of sound, and allow the output voltage signal of sound system after power-off, still can correctly maintain a period of time.
U.S. Patent number 5778238 discloses a kind of power-off for microcontroller and restarts circuit, it is that P-N junction rectifier is connected to external power source with to capacitor charging, described electric capacity provides low-voltage circuit for detecting to operate required energy in the time of power-off, make mosfet transistor conducting and discharge power supply and restart the electric charge of the delay electric capacity of circuit input end, postpone that electric capacity does not discharge completely described in when avoiding because last time shutting down and time of delay while causing starting shooting again shortens.Can consume extra voltage drop but described diode is connected between external power source and internal circuit, cause the marginal value of internal circuit operating voltage to diminish, and the voltage of described diode output also can float with outer power voltage.
Therefore the known power-off for microcontroller is restarted circuit and is existed above-mentioned all inconvenience and problem.
summary of the invention
Object of the present invention, is to propose a kind of power-off delay circuit and method for sound system.
Another object of the present invention, is to propose a kind of sound system of tool power-off delay.
For achieving the above object, technical solution of the present invention is:
A kind of power-off delay circuit, is characterized in that comprising:
One external power source input;
One internal electric source feed end;
One electric capacity connects described internal electric source feed end;
One switch is connected between described external power source input and described internal electric source feed end;
One hysteresis comparator has that first input end connects described external power source input, the second input connects described internal electric source feed end, and output produces and controls switch described in signal control;
Wherein, described switch is opened and is connected described external power source input to described internal electric source feed end under the first state, and closes under the second state.
Power-off delay circuit of the present invention can also be further achieved by the following technical measures.
Aforesaid power-off delay circuit, wherein said switch comprises that a MOS transistor is connected between described external power source input and described internal electric source feed end, is subject to the control of described control signal.
Aforesaid power-off delay circuit, wherein said switch comprises:
One the one PMOS transistor is connected between described external power source input and described internal electric source feed end, is subject to the control of described control signal;
One voltage commutation circuit connects the transistorized substrate of a described PMOS, to switch its voltage.
Aforesaid power-off delay circuit, wherein described voltage commutation circuit comprises:
One the 2nd PMOS transistor is connected between described external power source input and the transistorized substrate of a described PMOS, the voltage of described external power source input is applied to the transistorized substrate of a described PMOS under described the first state;
One resistance is connected between described internal electric source feed end and the transistorized substrate of a described PMOS, the voltage of described internal electric source feed end is applied to the transistorized substrate of a described PMOS under described the second state.
Aforesaid power-off delay circuit, wherein described resistance comprises the transistorized substrate resistance of a described PMOS.
Aforesaid power-off delay circuit, wherein described hysteresis comparator comprise that initial state sets resistance and connect the output of described hysteresis comparator, set the initial logic state of described control signal.
Aforesaid power-off delay circuit, wherein described hysteresis comparator comprises:
First and second input transistors, described the first input transistors has gate and connects described external power source input;
Magnetic hysteresis is connected to resistance between the gate of described the second input and described the second input transistors;
The source-series described magnetic hysteresis resistance of electric current for magnetic hysteresis;
Wherein, described magnetic hysteresis produces pressure drop to determine the magnetic hysteresis size of described hysteresis comparator with resistance.
Aforesaid power-off delay circuit, wherein the capacitance of described electric capacity define time of delay of described power-off delay circuit.
A kind of power-off delay method, is characterized in that comprising the following steps:
(A) monitor the voltage of external power source input and the voltage of internal electric source feed end;
(B) according to the voltage magnetic hysteresis of the voltage of described external power source input and described internal electric source feed end control and described external power source input connected or be free of attachment to described internal electric source feed end;
(C) during described external power source input is connected to described internal electric source feed end, to capacitor charging.
Power-off delay method of the present invention can also be further achieved by the following technical measures.
Aforesaid power-off delay method, wherein said steps A comprises the voltage of more described external power source input and the voltage of described internal electric source feed end.
Aforesaid power-off delay method, wherein said step B comprises and opens MOS transistor and described external power source input is connected to described internal electric source feed end.
Aforesaid power-off delay method, wherein said step B comprises:
Open PMOS transistor and described external power source input is connected to described internal electric source feed end;
The voltage of described external power source input is applied to the transistorized substrate of described PMOS.
Aforesaid power-off delay method, wherein said step B comprises:
Close PMOS transistor and cut off being connected between described external power source input and described internal electric source feed end;
The voltage of described internal electric source feed end is applied to the transistorized substrate of described PMOS.
Aforesaid power-off delay method, wherein more comprises that setting initial state makes described external power source input be connected to described internal electric source feed end.
A kind of sound system, is characterized in that comprising:
One sound source wire;
One driving transistors, connects described sound source wire;
One power-off delay circuit, connect described driving transistors, described power-off delay circuit has external power source input, internal electric source feed end and electric capacity and connects described internal electric source feed end, the voltage of described internal electric source feed end during lower than the voltage of described external power source input to described capacitor charging, and give described driving transistors by described electric capacity for induced current in the time of power-off, with the current potential of drop-down described sound source wire.
Aforesaid sound system, wherein said power-off delay circuit comprises:
One switch is connected between described external power source input and described internal electric source feed end;
One hysteresis comparator has that first input end connects described external power source input, the second input connects described internal electric source feed end, and output produces and controls switch described in signal control;
Wherein, described switch is opened and is connected described external power source input to described internal electric source feed end under the first state, and closes under the second state.
Aforesaid power-off delay circuit, wherein said switch comprises that MOS transistor is connected between described external power source input and described internal electric source feed end, is subject to the control of described control signal.
Aforesaid power-off delay circuit, wherein said switch comprises:
The one PMOS transistor is connected between described external power source input and described internal electric source feed end, is subject to the control of described control signal;
Voltage commutation circuit connects the transistorized substrate of a described PMOS, to switch its voltage.
Aforesaid power-off delay circuit, wherein said voltage commutation circuit comprises:
The 2nd PMOS transistor is connected between described external power source input and the transistorized substrate of a described PMOS, the voltage of described external power source input is applied to the transistorized substrate of a described PMOS under described the first state;
Resistance is connected between described internal electric source feed end and the transistorized substrate of a described PMOS, the voltage of described internal electric source feed end is applied to the transistorized substrate of a described PMOS under described the second state.
Aforesaid power-off delay circuit, wherein said resistance comprises the transistorized substrate resistance of a described PMOS.
Aforesaid power-off delay circuit, wherein said hysteresis comparator comprises that initial state setting resistance connects the output of described hysteresis comparator, sets the initial logic state of described control signal.
Aforesaid power-off delay circuit, wherein said hysteresis comparator comprises:
First and second input transistors, described the first input transistors has gate and connects described external power source input;
Magnetic hysteresis is connected to resistance between the gate of described the second input and described the second input transistors;
The source-series described magnetic hysteresis resistance of electric current for magnetic hysteresis;
Wherein, described magnetic hysteresis produces pressure drop to determine the magnetic hysteresis size of described hysteresis comparator with resistance.
Aforesaid power-off delay circuit, the capacitance of wherein said electric capacity defines the time of delay of described power-off delay circuit.
Adopt after technique scheme, power-off delay circuit of the present invention and method, and the sound system of tool power-off delay has advantages of and in the time that sound system is opened and closed, eliminates sonic boom.
Brief description of the drawings
Fig. 1 is the sound system calcspar of application power-off delay circuit of the present invention;
Fig. 2 is an embodiment schematic diagram of power-off delay circuit of the present invention;
Fig. 3 is while realizing switch 16 with diode, NMOS or PMOS, the graph of a relation on switch 16 between pressure differential deltap V and the electric current of loss;
Fig. 4 is the circuit diagram of another embodiment of the present invention;
Fig. 5 is the outer power voltage V of Fig. 4
cCwith internal power source voltage V
dDcurve chart;
Fig. 6 is outer power voltage V
cCwith internal power source voltage V
dDcurve comparison diagram.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof, the present invention is illustrated further.
Now refer to Fig. 1, Fig. 1 ties up to the schematic diagram that uses power-off delay circuit in sound system.As shown in the figure, restart integrated circuit (reset IC) 10 and connect external power source V
cC, external capacitor C and multiple driving transistors M1-MN, each driving transistors is connected to a loud speaker 12 through a sound source wire (audio line) 11.Detect outer power voltage V when restarting IC 10
cCextremely, for example when power-off, the electric charge just storing by capacitor C provides load current I_load to driving transistors M1-MN, thereby moves the voltage of sound source wire 11 to 0 volt to avoid sonic boom to produce.Be to be incorporated into restart in IC 10 according to power-off delay circuit of the present invention, the time of the internal electric source power-off of IC 10 is restarted in its delay, makes to restart IC 10 at external power source V
cCafter power-off, in a period of time, can maintain enough load current I_load.As shown in Figure 2, power-off delay circuit 14 comprises capacitor C and connects internal electric source feed end V
dD, switch 16 is connected to external power source input V
cCwith internal electric source feed end V
dDbetween, and hysteresis comparator 18 is according to outer power voltage V
cCand internal power source voltage V
dDcontrol switch 16.The first input end of hysteresis comparator 18 connects external power source input V
cC, the second input connects internal electric source feed end V
dD, output produces controls signal S1 control switch 16.Under the first state, switch 16 is opened (turn on) and by external power source input V
cCbe connected to internal electric source feed end V
dD, therefore external power source V
cCcan charge to capacitor C.Under the second state, switch 16 cuts out (turn off) and cuts off external power source input V
cCand internal electric source feed end V
dDbetween connection, provide internal circuit 20 to operate required electric power by capacitor C.By magnetic hysteresis control external power source input V
cCconnect or be free of attachment to internal electric source feed end V
dD, can maintain stable internal power source voltage V
dD.The time of delay of the capacitance size definition power-off delay circuit 14 of capacitor C, that is power-off delay circuit 14 is supported the time of internal circuit 20 correct work.In the present embodiment, capacitor C system is arranged on the outside of restarting IC 10, to adjust the size of capacitor C, optimization time of delay in other embodiments, also can be arranged on capacitor C the inside of restarting IC 10 according to system requirements.
Fig. 3 is the embodiment schematic diagram of switch 16 and hysteresis comparator 18.At this, switch 16 comprises PMOS transistor P1 and is connected to external power source input V
cCwith internal electric source feed end V
dDbetween, controlled signal S1 controls, and PMOS transistor P2 and resistance R
wELLcomposition voltage commutation circuit is connected to external power source input V
cCwith internal electric source feed end V
dDbetween.PMOS transistor P2 is connected to external power source input V
cCand between the substrate of PMOS transistor P1, resistance R
wELLbe connected to internal electric source feed end V
dDand between the substrate of PMOS transistor P1.Adopting PMOS transistor P1 to realize switch 16, is in order to reduce the pressure drop of loss on switch 16 as far as possible.PMOS transistor P2 and resistance R
wELLfor switching the framework of well (switching well), with so that the wellblock of PMOS transistor P1 connects maximum potential, promote the ability that prevents breech lock (latch up).In the present embodiment, PMOS transistor P1 is used for defining switch 16 in the time opening, external power source input V
cCwith internal electric source feed end V
dDbetween pressure drop, PMOS transistor P2 and resistance R
wELLbe used for switching the current potential of N-type well, N-type well can be with the both end voltage V of switch 16
cCand V
dDdifference and be connected to not homonymy.As outer power voltage V
cChigher than internal power source voltage V
dDtime, hysteresis comparator 18 is opened PMOS transistor P1 and P2, and N-type well is connected to external power source V through PMOS transistor P2
cC, therefore the substrate of PMOS transistor P1 (being N-type well) is connected to hot end V
cC.As outer power voltage V
cClower than internal power source voltage V
dDtime, PMOS transistor P1 and P2 are closed by hysteresis comparator 18, therefore dead resistance R
wELLthe substrate of PMOS transistor P1 is connected to hot end V
dD.By the current potential that switches N-type well, PMOS transistor P1 operates as same switch module.Fig. 4 is the schematic diagram of the effect of comparison the present invention and known technology, the Δ V of trunnion axis represents the pressure drop of switch 16, vertical axis represents the electric current of switch 16, and curve 22 is the current-voltage characteristic curve of PMOS transistor P1, and curve 24 is the current-voltage characteristic curve of diode.Use PMOS transistor P1 to be used as switch module, the pressure differential deltap V of its loss is about 0.1V, is less than the conduction voltage drop V of diode
dIODE(being about 0.6V), therefore reduce external power source input V
cCwith internal electric source feed end V
dDbetween pressure drop, internal power source voltage V
dD(=V
cC-Δ V) higher than the internal power source voltage (=V that uses diode
cC-V
dIODE), and then increased the about 0.5V of marginal value of the operating voltage of internal circuit 20.On the other hand, the rate of rise of curve 22
Slope=1/Ron, [formula 1]
Wherein Ron is the conduction resistance value of PMOS transistor P1.The size that increases PMOS transistor P1 can reduce its conduction resistance value Ron, and then improves the rate of rise Slope of curve 22.
Get back to Fig. 3, hysteresis comparator 18 has a pair of input transistors M1 and M2, and the gate of input transistors M1 connects external power source input V
cC, bias current source I
bIASconnect input transistors M1 and M2, magnetic hysteresis resistance P
hYSbe connected between the second input of hysteresis comparator 18 and the gate of input transistors M2 magnetic hysteresis current source I
hYSseries resistance R
hYS, the electric current resistance R of flowing through is provided
hYSand generation pressure drop, the magnetic hysteresis size delta H of decision hysteresis comparator 18.Preferably, uses initial state to set resistance R
iNIthe output that connects hysteresis comparator 18, is preset in logic low level by its output signal S1, makes the preset state of PMOS transistor P1 for opening.With reference to Fig. 5, waveform 26 represents outer power voltage V
cC, waveform 28 represents internal power source voltage V
dD, level 30 represents external power source V
cCstandby value (standby power), be generally 3.3V or 5V.After electric power starting, outer power voltage V
cCrise to rated value from 0.During this period, because switch 16 is conductings, so internal power source voltage V
dDalso rise thereupon.Due to the hysteresis characteristic of hysteresis comparator 18, switch 16 cuts out at time t1 after a while, until internal power source voltage V
dDdrop to lower than threshold value, for example time t2, hysteresis comparator 18 is opened switch 16 once again, therefore external power source V
cCcapacitor C charging is drawn high to internal power source voltage V
dD.During to time t3, switch 16 is cut out by hysteresis comparator 18 again, therefore internal power source voltage V
dDstart again to decline.As outer power voltage V
cCdrop to lower than after standby level 30 internal power source voltage V
dDdescending slope determine as follows by the capacitance of capacitor C
R
sW=V
cCdescending slope (V/s), [formula 2]
C＞I_load/R
SW。[formula 3]
For instance, if load current I_load is 5mA, R
sW=5V/1ms=5K (V/s),
C＞5mA/5KV/s＝1μF。
If load current I_load is 20mA, R
sW=5V/10ms=0.5K (V/s),
C＞20mA/0.5KV/s＝40μF。
As shown in the section 32 in Fig. 5, in the time that the capacitance of capacitor C is larger, internal power source voltage V
dDthe slope declining also becomes and relaxes.
With reference to Fig. 6, after electric power starting, as outer power voltage V
cCwhile rising to the cut-in voltage Vr of PMOS transistor P1, PMOS transistor P1 opens, therefore internal power source voltage V
dDjump to lower than outer power voltage V
cCthe size of approximately 0.1 volt, then along with outer power voltage V
cCrise.At outer power voltage V
cCafter arriving rated value, since the cause of magnetic hysteresis, internal power source voltage V
dDthe more late V that reaches
cCsize.After this, internal power source voltage V
dDmaintained V by hysteresis comparator 18
cCnear, its ripple size depends on magnetic hysteresis size delta H.During this period, switch 16 is controlled signal S1 and is repeatedly switched, and its time T of closing each time depends on load I_load and magnetic hysteresis size delta H.Select suitable magnetic hysteresis size delta H can reduce the switching frequency of switch 16, reduce power switched loss.
Above embodiment is used for illustrative purposes only, but not limitation of the present invention, person skilled in the relevant technique, without departing from the spirit and scope of the present invention, can also make various conversion or variation.Therefore, all technical schemes that are equal to also should described in belong to category of the present invention, should be limited by each claim.
Claims (10)
1. a power-off delay circuit, is characterized in that comprising:
One external power source input;
One internal electric source feed end;
One electric capacity connects described internal electric source feed end;
One switch is connected between described external power source input and described internal electric source feed end;
One hysteresis comparator has that first input end connects described external power source input, the second input connects described internal electric source feed end, and switch described in the control of output generation control signal, the voltage of the more described external power source input of described hysteresis comparator and the voltage of described internal electric source feed end produce described control signal;
Wherein, described switch is opened and is connected described external power source input to described internal electric source feed end under the first state, and closes under the second state;
Wherein, described switch comprises:
One the one PMOS transistor is connected between described external power source input and described internal electric source feed end, is subject to the control of described control signal;
One voltage commutation circuit connects the transistorized substrate of a described PMOS, to switch its voltage.
2. power-off delay circuit as claimed in claim 1, is characterized in that, described voltage commutation circuit comprises:
One the 2nd PMOS transistor is connected between described external power source input and the transistorized substrate of a described PMOS, the voltage of described external power source input is applied to the transistorized substrate of a described PMOS under described the first state;
One resistance is connected between described internal electric source feed end and the transistorized substrate of a described PMOS, the voltage of described internal electric source feed end is applied to the transistorized substrate of a described PMOS under described the second state.
3. power-off delay circuit as claimed in claim 2, is characterized in that, described resistance comprises the transistorized substrate resistance of a described PMOS.
4. power-off delay circuit as claimed in claim 1, is characterized in that, described hysteresis comparator comprises that initial state setting resistance connects the output of described hysteresis comparator, sets the initial logic state of described control signal.
5. power-off delay circuit as claimed in claim 1, is characterized in that, described hysteresis comparator comprises:
First and second input transistors, described the first input transistors has gate and connects described external power source input;
Magnetic hysteresis is connected to resistance between the gate of described the second input and described the second input transistors;
The source-series described magnetic hysteresis resistance of electric current for magnetic hysteresis;
Wherein, described magnetic hysteresis produces pressure drop to determine the magnetic hysteresis size of described hysteresis comparator with resistance.
6. power-off delay circuit as claimed in claim 1, is characterized in that, the capacitance of described electric capacity defines the time of delay of described power-off delay circuit.
7. a power-off delay method, is characterized in that comprising the following steps:
(A) monitor the voltage of external power source input and the voltage of internal electric source feed end;
(B) according to the voltage magnetic hysteresis of the voltage of described external power source input and described internal electric source feed end control and described external power source input connected or be free of attachment to described internal electric source feed end;
(C) during described external power source input is connected to described internal electric source feed end, to capacitor charging;
Wherein, described steps A comprises the voltage of more described external power source input and the voltage of described internal electric source feed end;
Wherein, described step B comprises:
Open PMOS transistor and described external power source input is connected to described internal electric source feed end;
The voltage of described external power source input is applied to the transistorized substrate of described PMOS.
8. a power-off delay method, is characterized in that comprising the following steps:
(A) monitor the voltage of external power source input and the voltage of internal electric source feed end;
(B) according to the voltage magnetic hysteresis of the voltage of described external power source input and described internal electric source feed end control and described external power source input connected or be free of attachment to described internal electric source feed end;
(C) during described external power source input is connected to described internal electric source feed end, to capacitor charging;
Wherein, described steps A comprises the voltage of more described external power source input and the voltage of described internal electric source feed end;
Wherein, described step B comprises:
Close PMOS transistor and cut off being connected between described external power source input and described internal electric source feed end;
The voltage of described internal electric source feed end is applied to the transistorized substrate of described PMOS.
9. power-off delay method as claimed in claim 7, is characterized in that, more comprises that setting initial state makes described external power source input be connected to described internal electric source feed end.
10. power-off delay method as claimed in claim 8, is characterized in that, more comprises that setting initial state makes described external power source input be connected to described internal electric source feed end.
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|---|---|---|---|
| CN200910151668.5A CN101958701B (en) | 2009-07-15 | 2009-07-15 | outage delay circuit, method and sound system with outage delay |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910151668.5A CN101958701B (en) | 2009-07-15 | 2009-07-15 | outage delay circuit, method and sound system with outage delay |
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| CN2013102529960A Division CN103368541A (en) | 2009-07-15 | 2009-07-15 | Power-off delay circuit and method, and sound system with power-off delay function |
| CN201410060443.XA Division CN103840805A (en) | 2009-07-15 | 2009-07-15 | Power failure delay circuit and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101958701A CN101958701A (en) | 2011-01-26 |
| CN101958701B true CN101958701B (en) | 2014-07-09 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104378094A (en) * | 2014-10-04 | 2015-02-25 | 侯舒婷 | Outage delay circuit and method for sound system |
| TWI768466B (en) * | 2020-09-10 | 2022-06-21 | 美律實業股份有限公司 | Playback device and control method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028474A (en) * | 1996-09-26 | 2000-02-22 | Yahama Corporation | Semiconductor integrated circuit |
| CN101018041A (en) * | 2007-03-08 | 2007-08-15 | 埃派克森微电子(上海)有限公司 | Frequency switching circuit for restraining the D power amplifier POP sound and its method |
| CN101071992A (en) * | 2007-04-09 | 2007-11-14 | 中兴通讯股份有限公司 | High voltage power voltage-reducing device |
| CN101087130A (en) * | 2006-06-07 | 2007-12-12 | 英业达股份有限公司 | Audio device protection system |
| CN101110569A (en) * | 2006-07-21 | 2008-01-23 | 罗姆股份有限公司 | Abnormality detection circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6631293B2 (en) * | 1997-09-15 | 2003-10-07 | Cardiac Pacemakers, Inc. | Method for monitoring end of life for battery |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028474A (en) * | 1996-09-26 | 2000-02-22 | Yahama Corporation | Semiconductor integrated circuit |
| CN101087130A (en) * | 2006-06-07 | 2007-12-12 | 英业达股份有限公司 | Audio device protection system |
| CN101110569A (en) * | 2006-07-21 | 2008-01-23 | 罗姆股份有限公司 | Abnormality detection circuit |
| CN101018041A (en) * | 2007-03-08 | 2007-08-15 | 埃派克森微电子(上海)有限公司 | Frequency switching circuit for restraining the D power amplifier POP sound and its method |
| CN101071992A (en) * | 2007-04-09 | 2007-11-14 | 中兴通讯股份有限公司 | High voltage power voltage-reducing device |
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