CN101951513A - Digital video decoding system - Google Patents
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- CN101951513A CN101951513A CN2010102864306A CN201010286430A CN101951513A CN 101951513 A CN101951513 A CN 101951513A CN 2010102864306 A CN2010102864306 A CN 2010102864306A CN 201010286430 A CN201010286430 A CN 201010286430A CN 101951513 A CN101951513 A CN 101951513A
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Abstract
The invention discloses a digital video decoding system comprising a microprocessor, a decoding calculation unit, a D/A converter, a video amplifier and a network interface, wherein the decoding calculation unit at least comprises a first algorithm decoding calculation unit and a second algorithm decoding calculation unit, and the microprocessor is also provided with a decoding pretreatment module. The digital video decoding system of the invention better solves the real-time decoding of the digital video flows of two decoding formats, i.e. the MPEG-4 standard and the H.264 standard and the self-adaptive decryption of the encrypting code stream, and can better satisfy the compatibility demand on equipment in practical application and high-safety application of the monitoring system.
Description
Technical field
The present invention relates to a kind of video decoding system of field of video monitoring, especially relate to a kind of digital video decoding system with adaptive decoding and self adaptation deciphering function.
Background technology
The ordinary numbers Video Decoder mainly partly is made up of network interface, decoding digital video module, D/A conversion, the video amplifier etc., its course of work is: the network interface of decoder receive from transmission line through MPEG-4, the digital video frequency flow behind the scheduling algorithm compressed encoding H.264, decoding digital video module invokes decoding arithmetic element is converted to the digital video frequency flow of compressed encoding the digital video frequency flow of non-compressed encoding, be converted to analog video signal by D/A, amplify back output through the video amplifier again, can be linked into analog video equipment and display the play.
The ordinary numbers Video Decoder is generally only supported a kind of decoding of compressed encoding form code stream, though some decoder is supported more than one coded format, come into force but selection of configuration is a kind of only simultaneously, when the code stream format conversion, need reconfigure the selection coded format, even can come into force after restarting decoder apparatus.And the ordinary numbers Video Decoder does not generally have special-purpose safety chip, does not possess the decipher function of encrypting code stream.
In announced GA/T669.4-2008 national sector standard, with the MPEG-4 standard and H.264 standard be decided to be two kinds of video compression coding format standards of supervision of the cities alarm network system.The ordinary numbers Video Decoder only is applicable to the single system of video compression coding form in the monitoring network, when having MPEG-4 in the system concurrently and H.264 during the video flowing of two kinds of compressed encoding forms, the use of this decoder will be very limited.
In video monitoring system,, often need to use some transmission mediums that are difficult to ensure information security, as internet, wireless channel etc. for effectively video monitoring signal being transmitted.For guaranteeing the information security of important video monitoring image, need when transmission, encrypt vision signal, at present, the cryptographic algorithm of being approved by China Password Management department is the close algorithm 1 of SM1(merchant).Common digital video decoder is not supported the SM1 algorithm and to the decipher function of encrypted video, and when the video-encryption that needs in the monitoring network transmission, the ordinary numbers Video Decoder then just can't use.
As application number is the AVS Video Decoder that the application for a patent for invention of CN200710178279.2 discloses a kind of software and hardware combined decoding, comprising: adopt DSP (digital signal processor) and the software and hardware combined decoding of coprocessor; The software decode part is finished by DSP, finish parsing to the AVS agreement, produce various parameters that decoding needs and the coprocessor decode procedure is controlled, there is complex structure in AVS Video Decoder with software and hardware combined decoding of said structure, does not possess the defective of adaptive decoding and self adaptation deciphering function.
Summary of the invention
Purpose of the present invention overcomes deficiency of the prior art exactly, provide a kind of simple in structure, function complete, can discern automatically and realize the MPEG-4 standard and H.264 two kinds of different coding format digital videos streams of standard adaptive decoding and to carry out the digital video decoding system of real time decrypting through the digital video frequency flow of SM1 algorithm for encryption.
For solving the problems of the prior art, digital video decoding system of the present invention, comprise microprocessor, be arranged on the decoding arithmetic element in the described microprocessor, the D/A converter that is connected with described microprocessor and the video amplifier that is connected with described D/A converter, also comprising is connected with described microprocessor is used for the network interface of receiving digital video stream, wherein, described decoding arithmetic element comprises first algorithm decoding arithmetic element and second algorithm decoding arithmetic element at least, also is provided with Coding Compression Algorithm that automatic discriminating digit video flowing adopted and the decoding pretreatment module of selecting corresponding with it described first algorithm decoding arithmetic element or described second algorithm decoding arithmetic element to decode in the described microprocessor.
Further, described first algorithm decoding arithmetic element meets the MPEG-4 standard, and described second algorithm decoding arithmetic element meets H
.264 standards.
Further, be provided with in the described microprocessor and be used for the encrypted bit stream identification module whether the discriminating digit video flowing encrypt, described microprocessor also is connected with the deciphering safety chip that the encrypted digital video stream of determining through described encrypted bit stream identification module is carried out decrypt operation.
Further, be provided with the SM1 algoritic module in the described deciphering safety chip.
Further, described microprocessor comprises arm processor and dsp processor.
The advantage of digital video decoding system of the present invention is:
1) system is provided with the decoding pretreatment module and meets MPEG-4 and H
.The MPEG-4 standard and the adaptive decoding of two kinds of different-format digital video frequency flows of standard H.264 can be discerned and realize to the decoding arithmetic element of 264 two kinds of standards automatically;
2) system is provided with encrypted bit stream identification module and the deciphering safety chip that is embedded with the SM1 algoritic module, can carry out real time decrypting to the digital video frequency flow through the SM1 algorithm for encryption;
3) system adopts arm processor and dsp processor to carry out software and hardware to combine, and system is flexible, power consumption is little, cost is low.
In sum, digital video decoding system of the present invention, solved MPEG-4 standard and the H.264 real-time decoding of two kinds of different coding format digital videos of standard stream and the real-time adaptive deciphering of encrypting code stream well, can better meet supervisory control system when practical application to compatibility of apparatus demand and high-security applications.
Description of drawings
Fig. 1 is the structural representation of digital video decoding system embodiment of the present invention.
Fig. 2 is the workflow diagram of digital video decoding system of the present invention.
Embodiment
The present invention will be further described in detail below in conjunction with accompanying drawing.
As shown in Figure 1, digital video decoding system 1 of the present invention, comprise the network interface 11, microprocessor 12, D/A converter 13, the video amplifier 14 that are connected successively, the video amplifier 14 external display terminals 2, microprocessor 12 also is connected with deciphering safety chip 15, file system memory 16 and program storage 17, be provided with encrypted bit stream identification module 122, decoding pretreatment module 123 and decoding arithmetic element 124 in the microprocessor 12, wherein, decoding arithmetic element 124 comprises first algorithm decoding arithmetic element 1241 and second algorithm decoding arithmetic element 1242.
In the present embodiment, described network interface 11 be used for receiving from transmission line through meeting MPEG-4 standard and the digital video frequency flow after the compression algorithm of two kinds of different coding forms of standard H.264.
In the present embodiment, what described microprocessor 12 adopted is the processor of TMS320DM6446 type, comprise ARM9 processor and dsp processor, the ARM9 processor is responsible for carrying out interface communication respectively with various external equipments such as network interface 11, D/A converter 13, deciphering safety chip 15, file system memory 16 and program storage 17, and the associative operation of actuating code stream encryption identification module 122 and decoding pretreatment module 123; Dsp processor is responsible for finishing the decoding computing of 124 pairs of compressed digital video streams of decoding arithmetic element.
In the present embodiment, the content location whether described encrypted bit stream identification module 122 has been encrypted and encrypted by the analysis of digital video frequency flow package identification being determined it when being defined as encrypted video stream, then being called deciphering safety chip 15 and is decrypted computing.
In the present embodiment, what described deciphering safety chip 15 adopted is the special-purpose safety chip of ZDTX001, and it is embedded with the SM1 algoritic module, can carry out real time decrypting to the digital video frequency flow through the SM1 algorithm for encryption.
In the present embodiment, described decoding pretreatment module 123 is discerned the Coding Compression Algorithm that it adopted automatically by the code stream format content of analyzing digital video frequency flow and is selected corresponding with it first algorithm decoding arithmetic element 1241 or second algorithm decoding arithmetic element 1242 to decode.
In the present embodiment, described decoding arithmetic element 124 adopts with double engines the driving simultaneously to load two decoding arithmetic elements, i.e. first algorithm decoding arithmetic element 1241 and second algorithm decoding arithmetic element 1242, described first algorithm decoding arithmetic element 1241 meets the MPEG-4 standard, and described second algorithm decoding arithmetic element 1242 meets H
.264 standards.
As shown in Figure 2, the course of work of digital video decoding system 1 of the present invention is specific as follows:
1) beginning;
2) digital video decoding system 1 power-up initializing;
3) network interface 11 receiving digital videos stream;
4) the stream package identification of the 122 pairs of digital videos of encrypted bit stream identification module in the microprocessor 12 is analyzed;
5) determine it is encrypted video stream, deciphering safety chip 15 is decrypted computing, and the digital video frequency flow after the deciphering is delivered to decoding pretreatment module 123; Be defined as non-encrypted video flowing, then directly be sent to decoding pretreatment module 123.
6) the code stream format content of 123 pairs of digital video frequency flows of decoding pretreatment module is analyzed and is discerned the Coding Compression Algorithm that it adopted automatically;
7) if meet the video flowing of MPEG-4 reference format, be sent to the computing of decoding of first algorithm decoding arithmetic element 1241, first algorithm decoding arithmetic element 1241 is converted to the digital video frequency flow of non-compressed encoding with the digital video frequency flow of compressed encoding, if meet H
.The video flowing of 264 reference formats then is sent to the computing of decoding of second algorithm decoding arithmetic element 1242;
8) decoded digital video frequency flow is converted to analog video signal by D/A converter 13;
9) video amplifier 14 amplifies analog video signal and outputs to display terminal 2 and plays.
In a word, what embodiments of the invention were announced is its preferred implementation, but is not limited to this.Those of ordinary skill in the art understands spirit of the present invention very easily according to the foregoing description, and makes different amplifications and variation, but only otherwise break away from spirit of the present invention, all within protection scope of the present invention.
Claims (5)
1. digital video decoding system, comprise microprocessor, be arranged on the decoding arithmetic element in the described microprocessor, the D/A converter that is connected with described microprocessor and the video amplifier that is connected with described D/A converter, also comprising is connected with described microprocessor is used for the network interface of receiving digital video stream, it is characterized in that: described decoding arithmetic element comprises first algorithm decoding arithmetic element and second algorithm decoding arithmetic element at least, also is provided with Coding Compression Algorithm that automatic discriminating digit video flowing adopted and the decoding pretreatment module of selecting corresponding with it described first algorithm decoding arithmetic element or described second algorithm decoding arithmetic element to decode in the described microprocessor.
2. digital video decoding system according to claim 1 is characterized in that: described first algorithm decoding arithmetic element meets the MPEG-4 standard, and described second algorithm decoding arithmetic element meets H
.264 standards.
3. according to claim 1 or 2 described digital video decoding systems, it is characterized in that: be provided with in the described microprocessor and be used for the encrypted bit stream identification module whether the discriminating digit video flowing encrypt, described microprocessor also is connected with the deciphering safety chip that the encrypted digital video stream of determining through described encrypted bit stream identification module is carried out decrypt operation.
4. digital video decoding system according to claim 3 is characterized in that: be provided with the SM1 algoritic module in the described deciphering safety chip.
5. digital video decoding system according to claim 1 is characterized in that: described microprocessor comprises arm processor and dsp processor.
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| CN2010102864306A CN101951513A (en) | 2010-09-19 | 2010-09-19 | Digital video decoding system |
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| CN2010102864306A CN101951513A (en) | 2010-09-19 | 2010-09-19 | Digital video decoding system |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103313096A (en) * | 2013-06-14 | 2013-09-18 | 成都思迈科技发展有限责任公司 | Network code stream converter |
| CN104378649A (en) * | 2014-08-19 | 2015-02-25 | 中国科学院信息工程研究所 | Method and system for encrypting video streams in real time through SM1 cryptographic algorithm |
| CN105592316A (en) * | 2014-10-23 | 2016-05-18 | 公安部第一研究所 | Digital video signal decoder |
| CN110933433A (en) * | 2019-10-15 | 2020-03-27 | 苏州斯普锐智能系统有限公司 | Industrial decoding module and application market based on same |
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| CN101064824A (en) * | 2006-04-28 | 2007-10-31 | 华为技术有限公司 | Method, system and apparatus for playing audio-video data |
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| CN101453640A (en) * | 2007-11-28 | 2009-06-10 | 中国科学院微电子研究所 | AVS video decoder for software and hardware combined decoding |
| CN201491188U (en) * | 2009-08-13 | 2010-05-26 | 深圳市九洲电器有限公司 | Set-top box and multiple-video format decoding device thereof |
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| CN1256840A (en) * | 1997-04-14 | 2000-06-14 | 汤姆森消费电子有限公司 | System for processing and decoding MPEG compatible data and internet information |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103313096A (en) * | 2013-06-14 | 2013-09-18 | 成都思迈科技发展有限责任公司 | Network code stream converter |
| CN104378649A (en) * | 2014-08-19 | 2015-02-25 | 中国科学院信息工程研究所 | Method and system for encrypting video streams in real time through SM1 cryptographic algorithm |
| CN104378649B (en) * | 2014-08-19 | 2018-10-09 | 中国科学院信息工程研究所 | It is a kind of that real-time encrypted method and system being carried out to video flowing using the close SM1 algorithms of state |
| CN105592316A (en) * | 2014-10-23 | 2016-05-18 | 公安部第一研究所 | Digital video signal decoder |
| CN110933433A (en) * | 2019-10-15 | 2020-03-27 | 苏州斯普锐智能系统有限公司 | Industrial decoding module and application market based on same |
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