CN101949737B - Row gating circuit of infrared focal plane array - Google Patents
Row gating circuit of infrared focal plane array Download PDFInfo
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- CN101949737B CN101949737B CN2010102579862A CN201010257986A CN101949737B CN 101949737 B CN101949737 B CN 101949737B CN 2010102579862 A CN2010102579862 A CN 2010102579862A CN 201010257986 A CN201010257986 A CN 201010257986A CN 101949737 B CN101949737 B CN 101949737B
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Abstract
The invention discloses a row gating circuit of an infrared focal plane array. The row gating circuit comprises a row gating control signal generator and two gating switches which are controlled and connected by the row gating control signal generator and positioned at the two ends of each pixel unit (Ps) respectively, and is characterized in that: the 2Kth and the (2K+1)th pixel units in each column of the infrared focal plane array are together connected with the gating switch on one side, while the (2K-1)th and the 2Kth pixel units are together connected with the gating switch on the other side, wherein K is a natural number; and the row gating circuit further comprises a corresponding reset switch in parallel connection with each pixel unit. The gating switches of the row gating circuit are reduced by multiplexing based on the gating row by row, the non-gated pixel unit can be short-connected during the row gating through the reset switch, and the influence of the parasitic charges on the non-gated pixel unit on the read signal on the gated pixel unit can be eliminated.
Description
Technical field
The present invention relates to microelectronics and photoelectron technology field, be specifically related to the capable gating circuit of infrared focal plane array in a kind of infrared imaging system.
Background technology
Infrared focal plane array seeker is a kind of detector of detectable target infrared radiation; Converting the Temperature Distribution of target object to video image through means such as opto-electronic conversion, electric signal processing, is that a kind of light harvesting, sophisticated technology such as mechanical, electrical are in the high-tech product of one.It has that strong, the hidden performance of antijamming capability is good, tracking, guidance precision advantages of higher, has obtained to use widely in the military and civilian field.
The micro-metering bolometer focal-plane array (FPA) has higher sensitivity, is most widely used a kind of non-refrigerate infrared focal plane array seeker.Its principle of work is that thermo-sensitive material absorbs temperature change behind the infrared radiation of incident, thereby causes the variation of self-resistance value, the size of the change detection infrared radiation signal through measuring its resistance value.The semi-girder micro-bridge structure that micro-metering bolometer generally adopts micromachining technology to make; Bridge floor deposits the thermo-sensitive material that one deck has high temperature coefficient of resistance (TCR); Bridge floor has excellent mechanical performances by two and is coated with the bridge leg support of conductive material; The contact point of bridge leg and substrate is a bridge pier, and bridge pier is electrically connected on the silicon sensing circuit (ROIC) under the micro-metering bolometer FPA.Through bridge leg and bridge pier, thermo-sensitive material is connected in the electricity passage of sensing circuit, forms one to responsive to temperature and be connected to the pixel cell on the sensing circuit.
For satisfying the military and civilian needs, the main development trend of non-refrigerated infrared detector is further reduced volume, increases resolution, reduces power consumption and cost etc., wherein, enlarges pel array, reduces the focus that Pixel Dimensions becomes infrared focal plane array research.The early 1990s, Honeywell company has reported the micro-metering bolometer FPA of 320 * 240 pixels, and pixel dimension is 50 * 50 μ m
2The thermal imaging system U3000 of 320 * 240 pixels of U.S. DRS technology company development, Pixel Dimensions is 51 * 51 μ m
2, calendar year 2001 is succeeded in developing the thermal imaging system U6000 that 640 * 480 focal planes are core, and Pixel Dimensions is 25.4 * 25.4 μ m
2, and in May, 2002 this thermal imaging system is demonstrated; Raytheon company has succeeded in developing 640 * 480 pixels at present, and pixel dimension is 25 * 25 μ m
2, the said firm is developing pixel dimension 20 * 20 μ m
2, the IRFPA of 640 * 512 arrays.
Small size, big array are the directions of high-performance infrared focal plane detector development.Yet; When reducing Pixel Dimensions, the bridge pier that the supporting bridge leg of micro-metering bolometer and conduct are connected with sensing circuit electricity, area can not equal proportion reduce usually; Thereby cause comparing the large scale pixel; Its effective infrared absorption area dutycycle reduces, and the explorer response rate reduces, and performance descends.For this reason; Infrared focal plane array has developed the structure of the adjacent microbridge units shared of a kind of same column bridge pier; Pixel cell uses typical semi-girder micro-bridge structure in this array; Two adjacent microbridge unit respectively have a bridge leg to be connected to jointly on the bridge pier in the same column, and a bridge leg of another bridge leg of microbridge unit and another adjacent microbridge unit is connected on second bridge pier jointly, and the N of an every row pixel cell only needs N+1 bridge pier to get final product.Compare each pixel cell of traditional focal plane arrays (FPA) and independently use two bridge piers; Each row has reduced the use of N-1 bridge pier; Thereby improved pixel infrared absorption useful area dutycycle; Make increasing pel array, when reducing Pixel Dimensions, still keep the explorer response rate in higher level.This infrared focal plane array structure needs corresponding with it capable gating circuit, accomplishes reading each picture element signal.Traditional a kind of capable gating circuit is that each pixel cell uses two gating switches controls, and pixel cell of each gating switch control needs 2N gating switch to N pixel cell of every row.On the one hand, gating switch is many more, and the non-ideal factor of introducing is just big more, and the chip area that under pel array, takies simultaneously is just big more, especially comparatively obvious under the small-sized pixel array; On the other hand, do not had short circuit by the pixel cell of gating, the spurious charge on the pixel cell etc. may be to being exerted an influence by the read output signal on the gating pixel cell.
Summary of the invention
Problem to be solved by this invention is: how a kind of capable gating circuit of infrared focal plane array is provided, and it can realize gating line by line to the focal plane arrays (FPA) that adopts the adjacent microbridge units shared of same column bridge pier structure; And realize that on this basis gating switch is multiplexing, reduce the quantity of gating switch; Further; This row gating circuit can use the CS that resets; Be expert at the choosing during short circuit not by the pixel cell of gating; Eliminate not by spurious charge on the pixel cell of gating by the influence of read output signal on the gating pixel cell, guarantee that the micro-metering bolometer of this infrared focal plane array structure can operate as normal.
Technical matters proposed by the invention is to solve like this: the capable gating circuit that a kind of infrared focal plane array is provided; What comprise capable selected control system signal generator and control linkage thereof lays respectively at each pixel cell two ends, each self-corresponding two gating switch (preposition gating switch and rearmounted gating switch); It is characterized in that: 2K is connected one one side gating switch with 2K+1 pixel cell and 2K-1 is connected an opposite side gating switch jointly with 2K pixel cell jointly in the every row of infrared focal plane array; K is a natural number; Specifically can be: 2K be connected a preposition gating switch with 2K+1 pixel cell and 2K-1 is connected a rearmounted gating switch jointly with 2K pixel cell jointly in the every row of (one) infrared focal plane array, and perhaps 2K-1 is connected a preposition gating switch with 2K pixel cell and 2K is connected a rearmounted gating switch jointly with 2K+1 pixel cell jointly in the every row of (two) infrared focal plane array.
Capable gating circuit according to infrared focal plane array provided by the present invention is characterized in that, comprises two kinds of forms:
(1) line number of said infrared focal plane array is 2N; K＜N; N is a natural number; 2K is connected one one side gating switch jointly with 2K+1 pixel cell in the every row of said infrared focal plane array, and 2K-1 is connected an opposite side gating switch jointly with 2K pixel cell, and the 1st is connected one one side gating switch separately separately with 2N pixel cell.
(2) line number of said infrared focal plane array is 2N+1; K＜N; N is a natural number, and 2K is connected one one side gating switch jointly with 2K+1 pixel cell in the every row of said infrared focal plane array, and 2K-1 is connected an opposite side gating switch jointly with 2K pixel cell; And the 1st pixel cell connects one one side gating switch separately, and 2N+1 pixel cell connects an opposite side gating switch separately.
Capable gating circuit according to infrared focal plane array provided by the present invention is characterized in that, a said side is the bias voltage side, and opposite side is the sensing circuit side; A perhaps said side is the sensing circuit side, and opposite side is the bias voltage side; Reading direction definition bias voltage VDET side gating switch by signal is that preposition gating switch, sensing circuit ROIC side gating switch are rearmounted gating switch, and specifically the infrared focal plane array with the 2N line number is an example, comprises two kinds of physical circuit forms:
1. structure (like Fig. 3) is lacked in many backs before: 2K is connected a preposition gating switch jointly with 2K+1 pixel cell in the every row of infrared focal plane array; 2K-1 is connected a rearmounted gating switch jointly with 2K pixel cell; And because 0＜K＜N, then do not have the 1st of the adjacent shared pixel of preposition gating switch unit to be connected a use preposition gating switch separately separately with 2N pixel cell;
2. few back many structures (like Fig. 4) before: 2K-1 is connected a preposition gating switch, 2K and 2K+1 pixel cell jointly with 2K pixel cell and is connected a rearmounted gating switch jointly in the every row of infrared focal plane array; And because 0＜K＜N, then do not have the 1st of the adjacent shared pixel of rearmounted gating switch unit to be connected a use rearmounted gating switch separately separately with 2N pixel cell.
Capable gating circuit according to infrared focal plane array provided by the present invention is characterized in that, this row gating circuit also comprises the corresponding reset switch with each pixel cell parallel connection.
Capable gating circuit according to infrared focal plane array provided by the present invention is characterized in that, said reset switch control end connects row selected control system signal generator.
Capable gating circuit according to infrared focal plane array provided by the present invention is characterized in that, control-signals generator includes, but are not limited to adopt the pulse-width modulation PWM module of microprocessor to realize.
Capable gating circuit according to infrared focal plane array provided by the present invention is characterized in that, the preferred field effect CMOS of said gating switch transistor.
Beneficial effect of the present invention is: 1, adopt this kind row gating circuit, can realize effectively gating line by line to the focal plane arrays (FPA) that adopts the adjacent microbridge units shared of same column bridge pier structure; 2, adopt the corresponding capable gating circuit of this kind infrared focal plane array structure, simple in structure, can realize that gating switch is multiplexing, reduce the usage quantity of gating switch; Further: 3, adopt the corresponding capable gating circuit of this kind infrared focal plane array structure, during the choosing of can being expert at short circuit not by the pixel cell of gating, elimination not by spurious charge on the pixel cell of gating to by the influence of read output signal on the gating pixel cell.
Description of drawings
Fig. 1 is the infrared focal plane array structural drawing that the present invention is directed against;
Fig. 2 is the used a kind of traditional gating circuit figure of this focal plane array array structure;
Fig. 3 is the used a kind of gating circuit figure of the present invention;
Fig. 4 is the used another kind of gating circuit figure of the present invention;
Fig. 5 is a kind of gating circuit figure with reset function of the present invention on circuit base shown in Figure 3;
Fig. 6 is a kind of sensing circuit channel architecture figure of the present invention on circuit base shown in Figure 3;
Fig. 7 is a kind of sensing circuit channel architecture figure with reset function of the present invention on circuit base shown in Figure 5;
Fig. 8 is the signal waveforms of a kind of gating circuit of the corresponding circuit shown in Figure 6 of the present invention;
Fig. 9 is a kind of gating circuit signal waveforms with reset function of the corresponding circuit shown in Figure 7 of the present invention.
Embodiment
At first, basis of the present invention and core are described:
The capable gating circuit of infrared focal plane array of the present invention; The pixel cell of this focal plane arrays (FPA) specifically uses the semi-girder micro-bridge structure; Bridge leg, bridge pier provide the electricity that is connected with sensing circuit passage for the microbridge unit, and adjacent microbridge unit adopts the design of shared bridge pier to be connected on the capable gating circuit in the same column; Adopt a kind of corresponding capable gating circuit, the row gating circuit is made up of gating switch and row selected control system signal generating circuit, gating switch be expert at closure or disconnection under the control of selected control system signal; Each pixel cell is controlled by two gating switches respectively simultaneously, and this pixel cell was connected in the signal read-out channel closed-loop path by gating when two gating switches were closed simultaneously; Each gating switch is controlled two pixel cells simultaneously and is realized switch multiplexing, and when arbitrary gating switch broke off, two pixel cells of its control were not connected in the signal read-out channel closed-loop path all not by gating.Under corresponding row selected control system signal, pel array is carried out gating line by line.
One end of above-mentioned gating switch is connected on the microbridge bridge pier, and the other end is connected in the signal read-out channel, and two ends, microbridge unit bridge pier is connected respectively on two gating switches; Line number is the focal plane arrays (FPA) of 2N; Each row needs 2N+1 gating switch S0, S1, S2 ... S2N, wherein switch S 0, S2 ... S2N control pixel cell is connected switch S 1, S3 with bias voltage VDET's ... S2N-1 control pixel cell is connected with the source electrode of MOS offset; I pixel cell controlled by gating switch Si-1 and Si jointly; When 1≤i≤2N, Si-1 and Si were closed simultaneously, i pixel cell was by gating; Be connected in the signal read-out channel closed-loop path, otherwise not by gating.
Above-mentioned gating switch S0, S1, S2 ... The closure of S2N and shutoff are by row selected control system signal SEL_0, SEL_1, SEL_2 ... The SEL_2N decision; When carrying out line by line gating; At first in first gating effective period, the SEL_0 and the SEL_1 that put every row are effective, and switch S 0, S1 are closed; The 1st pixel cell is connected respectively to the source electrode of VDET and MOS offset through switch S 0, S1; Thereby be connected in the signal read-out channel closed-loop path switch S 2, S3 ... S2N turn-offs, and the 2nd～2N pixel cell be not by gating; Next gating effective period; The SEL_1 and the SEL_2 that put every row are effective; S1, S2 closure, the 2nd pixel cell is connected respectively to the drain electrode and the VDET of MOS offset through switch S 1, S2, thereby is connected in the signal read-out channel closed-loop path; Switch S 0, S3, S4 ... S2N turn-offs, and the 1st, 3～2N pixel cell is by gating; By that analogy, gating is every successively is listed as the 3rd～2N pixel cell.
Above-mentioned capable gating circuit can use 2N reset CS SR1, SR2 at every row ... SR2N will be by the pixel cell short circuit of gating, and the two ends of switch S Ri are connected respectively to the two ends of i pixel cell, prevents that pixel cell end on electricity is unsettled; SR1, SR2 ... The closure of SR2N and shutoff are by control signal EN_1, EN_2 ... The EN_2N decision.The 1st pixel cell is during by gating, and EN_1 is invalid, and SR1 turn-offs, EN_2, EN_3 ... EN_2N is effective, SR2, SR3 ... SR2N is closed; By that analogy, when i pixel cell gating, turn-off closed all the other CSs that reset of SRi successively.
The second, in conjunction with accompanying drawing the present invention is further described:
Fig. 1 is the focal plane array array structure that the present invention is directed against; Pixel cell uses the semi-girder micro-bridge structure, and bridge floor deposits the thermo-sensitive material (like vanadium oxide or amorphous silicon etc.) that one deck has high temperature coefficient of resistance (TCR), and bridge floor is supported by two bridge legs with excellent mechanical performances; Thereby use L shaped bridge leg to increase length; Reduce thermal conductance, on the bridge pier that the bridge leg is connected to substrate contacts, bridge pier links to each other with sensing circuit on electricity.Through bridge leg and bridge pier, thermo-sensitive material is connected in the electricity passage of sensing circuit, forms one to responsive to temperature and be connected to the pixel cell on the sensing circuit.Two adjacent microbridge unit respectively have a bridge leg to be connected to jointly on the bridge pier in each row, and a bridge leg of another bridge leg of microbridge unit and another adjacent microbridge unit is connected on second bridge pier jointly; First microbridge unit of each row and last microbridge unit have a bridge leg to use a bridge pier alone respectively, the not shared bridge pier of pixel cell between row and the row.Therefore M * N pel array is only needed the individual bridge pier of M * (N+1), wherein M is the line number of pel array, and N is a columns.To 4 * 4 focal plane arrays (FPA)s, only need 4 * 5 bridge piers altogether.
Fig. 2 is the used a kind of traditional gating circuit figure of the said focal plane array array structure of Fig. 1; Rs represents the one-row pixels unit; Each pixel cell is controlled gating simultaneously by two gating switches, the gating of a pixel cell of each gating switch control, so line number is the focal plane arrays (FPA) of 2N; Total 2N the Ts of each row needs 4N gating switch altogether.Gating switch is by corresponding row selected control system signal sel0, sel1 ... The sel2N decision.First row gating effective period, when sel0 is effective, the gating first row pixel cell, sel2, sel3 ... Sel2N is invalid, breaks off the capable pixel cell of the 2nd～2N; By that analogy to pel array gating line by line.This gating structure has been used more gating switch, gating pixel cell short circuit is not resetted during the choosing of being expert at simultaneously.
Fig. 3 is the used a kind of gating circuit figure of the present invention; One-row pixels unit shown in the Rs representative graph 1; The bridge pier at each pixel cell two ends connects 1 gating switch respectively; S0, S1, S2 ... S2N is a gating switch, and an end of gating switch is connected on the microbridge bridge pier, and the other end is connected in the signal read-out channel; Line number is the focal plane arrays (FPA) of 2N, total 2N the Rs of each row, and shared 1 gating switch of the Rs that same column is adjacent is realized switch multiplexing, needs 2N+1 gating switch S0, S1, S2 altogether ... S2N.Wherein switch S 0, S2 ... S2N control pixel cell is connected with bias voltage VDET's; Switch S 1, S3 ... S2N-1 control pixel cell is connected with another part sensing circuit ROIC of read-out channel, and i pixel cell controlled by gating switch Si-1 and Si jointly, 1≤i≤2N; When Si-1 and Si are closed simultaneously; I pixel cell is connected in the signal read-out channel closed-loop path by gating, otherwise not by gating.
In like manner, reading direction definition VDET side gating switch by signal is preposition gating switch, and ROIC side gating switch is rearmounted gating switch, and order is set up the another kind of gating circuit of the present invention shown in Figure 4 before and after putting upside down, and can realize circuit identical function shown in Figure 3.
Fig. 5 is the used a kind of gating circuit figure with reset function of the present invention, compares with Fig. 3 gating circuit, and Fig. 5 gating circuit has increased a reset switch respectively for each pixel cell two ends.Every row use 2N reset CS SR1, SR2 ... By the pixel cell of gating, the two ends of switch S Ri are not connected respectively to the two ends of i pixel cell to the SR2N short circuit, prevent that pixel cell end on electricity is unsettled.The 1st pixel cell is during by gating, and SR1 turn-offs, SR2, SR3 ... SR2N is closed, makes the 2nd～2N pixel cell two terminal shortcircuits; By that analogy, when i pixel cell gating, turn-off SRi successively, closed all the other CSs that reset.
Fig. 6 is the used a kind of sensing circuit channel architecture figure of the present invention; Gating switch S0, S1, S2 ... S2N uses nmos pass transistor to realize S0, S1, S2 ... The conducting of S2N and shutoff are by row selected control system signal SEL_0, SEL_1, SEL_2 ... The SEL_2N decision; When carrying out line by line gating; At first in first gating effective period, it is effectively high to put SEL_0 and SEL_1, S0, S1 conducting; The 1st pixel cell is connected respectively to the source electrode of VDET and biasing MOS transistor NM; Thereby be connected in the signal read-out channel closed-loop path S2, S3 ... S2N turn-offs, and the 2nd～2N pixel cell be not by gating; Next gating effective period, it is high effective to put SEL_1 and SEL_2, S1, S2 conducting; The 2nd pixel cell is connected respectively to source electrode and the VDET of NM; Thereby be connected in the signal read-out channel closed-loop path S0, S3, S4 ... S2N turn-offs, and the 1st, 3～2N pixel cell is by gating; By that analogy, gating is every successively is listed as the 3rd～2N pixel cell.Be connected in the signal read-out channel closed-loop path by the pixel cell of gating, voltage VFID setovers by the Rs of gating through nmos pass transistor NM and voltage VDET, produces electric current I s; Rb is blind pixel, is used to eliminate system's dark current, and voltage Veb produces current Ib through PMOS transistor PM and voltage Vsk common bias Rb; Amplifier Op and integrating capacitor Cint constitute integrator, and Vref is a reference voltage, and the difference id of Is and Ib is an integration current; Between expiry date of points; The reset switch Reset of Cint breaks off, and id carries out integration and obtains output voltage V out on Cint, the different gating cycles; Corresponding gating respective pixel unit R s, the signal read-out channel obtains corresponding output voltage V out.
Fig. 7 is the used a kind of sensing circuit channel architecture figure with reset function of the present invention; CS SR1, SR2 reset ... SR2N uses the NMOS pipe to realize; The two ends of SRi are connected respectively to the two ends of i pixel cell, prevent that pixel cell end on electricity when the gating is unsettled.SR1, SR2 ... The conducting of SR2N and shutoff are by control signal EN_1, EN_2 ... The EN_2N decision.The 1st pixel cell is during by gating, and EN_1 is low invalid, EN_2, EN_3 ... EN_2N is effectively high, SR1 conducting, SR2, SR3 ... SR2N is closed; By that analogy, when i pixel cell gating, turn-off SRi, all the other CS conductings that reset successively.Remainder control signal sequential and function are same as shown in Figure 6.
Fig. 8 is the signal waveforms of the used a kind of gating circuit of the present invention.Signal waveform corresponding diagram 6 gating circuit part nmos switch S0, S1, S2 ... The control signal SEL_0 of S2N, SEL_1, SEL_2 ... SEL_2N; In the first row gating valid period; SEL_0 and SEL_1 are effectively high; SEL_2, SEL_3 ... SEL_2N is low invalid, thereby makes S0 and S1 conducting, S2, S3 ... S2N turn-offs; In the second row gating valid period, SEL_1 and SEL_2 are effectively high, SEL_0, SEL_3, SEL_4 ... SEL_2N is low invalid, thus S1 and S2 conducting, S0, S3, S4 ... S2N turn-offs; By that analogy, in the capable gating of the i valid period, SEL_i-1 and SEL_i are effectively high, SEL_0, SEL_1 ... SEL_i-2, SEL_i+1 ... SEL_2N is low invalid, thereby makes Si-1 and Si conducting, and all the other nmos switches turn-off.
Fig. 9 is the used gating circuit signal waveforms with reset function of the present invention.Signal waveform corresponding diagram 7 gating circuit part nmos switch S0, S1, S2 ... The control signal SEL_0 of S2N, SEL_1, SEL_2 ... SEL_2N and reset CS SR1, SR2 ... The control signal EN_1 of SR2N, EN_2 ... EN_2N.In the first row gating valid period, SEL_0 and SEL_1 are effectively high, SEL_2, SEL_3 ... SEL_2N is low invalid; S0 and S1 conducting, S2, S3 ... S2N turn-offs, and EN_1 is low invalid; EN_2, EN_3 ... EN_2N is effectively high, and SR1 turn-offs, SR2, SR3 ... The SR2N conducting; In the second row gating valid period, SEL_1 and SEL_2 are effectively high, SEL_0, SEL_3, SEL_4 ... SEL_2N is low invalid; S1 and S2 conducting; S0, S3, S4 ... S2N turn-offs, and EN_2 is low invalid, EN_1, EN_3, EN_4 ... EN_2N is effectively high; SR2 turn-offs, SR1, SR3, SR4 ... The SR2N conducting; By that analogy, in the capable gating of the i valid period, SEL_i-1 and SEL_i are effectively high; SEL_0, SEL_1 ... SEL_i-2, SEL_i+1 ... SEL_2N is low invalid, makes Si-1 and Si conducting, S0, S1 ... Si-1, Si+2 ... S2N turn-offs; EN_i is low invalid; SRi turn-offs, EN_1, EN_2 ... EN_i-1, EN_i+1 ... EN_2N is effectively high, SR1, SR2 ... SRi-1, SRi+1 ... The SR2N conducting.
Claims (9)
1. the capable gating circuit of an infrared focal plane array; What comprise capable selected control system signal generator and control linkage thereof lays respectively at each pixel cell (Rs) two ends, each self-corresponding two gating switch; It is characterized in that: 2K is connected one one side gating switch with 2K+1 pixel cell and 2K-1 is connected an opposite side gating switch jointly with 2K pixel cell jointly in the every row of infrared focal plane array, and K is a natural number.
2. capable gating circuit according to claim 1; It is characterized in that the line number of said infrared focal plane array is 2N, K＜N; N is a natural number; 2K is connected one one side gating switch jointly with 2K+1 pixel cell (Rs) in the every row of said infrared focal plane array, and 2K-1 is connected an opposite side gating switch jointly with 2K pixel cell (Rs), and the 1st is connected one one side gating switch separately separately with 2N pixel cell.
3. capable gating circuit according to claim 1 is characterized in that the line number of said infrared focal plane array is 2N+1; K＜N; N is a natural number, and 2K is connected one one side gating switch jointly with 2K+1 pixel cell (Rs) in the every row of said infrared focal plane array, and 2K-1 is connected an opposite side gating switch jointly with 2K pixel cell (Rs); And the 1st pixel cell connects one one side gating switch separately, and 2N+1 pixel cell connects an opposite side gating switch separately.
4. according to claim 2 or 3 described capable gating circuits, it is characterized in that a said side is the bias voltage side, opposite side is the sensing circuit side.
5. according to claim 2 or 3 described capable gating circuits, it is characterized in that a said side is the sensing circuit side, opposite side is the bias voltage side.
6. according to each described capable gating circuit of claim 1-3, it is characterized in that, also comprise corresponding reset switch with each pixel cell parallel connection.
7. capable gating circuit according to claim 6 is characterized in that, said reset switch control end connects row selected control system signal generator.
8. capable gating circuit according to claim 1 is characterized in that, row selected control system signal generator comprises the pulse width modulation module that adopts microprocessor.
9. capable gating circuit according to claim 1 is characterized in that said gating switch is a field effect transistor.
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| CN102707226A (en) * | 2012-07-06 | 2012-10-03 | 电子科技大学 | Detection circuit of line control circuit of infrared focal plane readout circuit |
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| CN110940419B (en) * | 2019-08-30 | 2021-04-30 | 上海集成电路研发中心有限公司 | Infrared detector and preparation method thereof |
| CN110487420B (en) * | 2019-09-11 | 2021-06-08 | 昆明物理研究所 | Fast and stable uncooled infrared focal plane reading circuit |
| CN116086621B (en) * | 2023-03-31 | 2023-07-25 | 杭州海康微影传感科技有限公司 | Infrared reading circuit and control method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100490497C (en) * | 2007-01-26 | 2009-05-20 | 东南大学 | Read-out circuit of infrared focal plane |
| CN101231191B (en) * | 2008-02-27 | 2010-07-14 | 东南大学 | Open window reading circuit of focal plane |
| CN101354288B (en) * | 2008-09-08 | 2010-06-30 | 北京大学 | High speed low power consumption double-row line infrared focal plane read-out circuit |
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| CN102707226A (en) * | 2012-07-06 | 2012-10-03 | 电子科技大学 | Detection circuit of line control circuit of infrared focal plane readout circuit |
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