CN101944906A - Frequency divider based on phase rotator - Google Patents
Frequency divider based on phase rotator Download PDFInfo
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- CN101944906A CN101944906A CN2009100546397A CN200910054639A CN101944906A CN 101944906 A CN101944906 A CN 101944906A CN 2009100546397 A CN2009100546397 A CN 2009100546397A CN 200910054639 A CN200910054639 A CN 200910054639A CN 101944906 A CN101944906 A CN 101944906A
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Abstract
The invention discloses a frequency divider based on a phase rotator, which comprises a sampling circuit and a two-input logic gate, wherein the sampling circuit is triggered by a second trigger edge, the input end of the sampling circuit is connected with the output end of a first D flip-flop, the trigger signal input end of the sampling circuit is connected with the output end of a buffer, and the sampling circuit is used for sampling an output signal of the first D flip-flop under the trigger of the second trigger edge; and one input end of the two-input logic gate is connected with the output end of the buffer, the other input end is connected with the output end of a second D flip-flop, the output end of the two-input logic gate is connected with a frequency controller, and the two-input logic gate is used for generating a corresponding edge trigger signal according to the output signal of the buffer so that the frequency controller is triggered when the output of the second D flip-flop is just the level as required. The invention has the advantage of effectively solving the problem of unstable frequency division of the frequency divider.
Description
Technical field
The present invention relates to a kind of frequency divider, particularly the stable frequency divider of a kind of frequency division based on phase rotation device based on phase rotation device.
Background technology
The frequency synthesizer (Synthesizer) that is used for radio frequency (RF) circuit needs the adjustable frequency divider of divider ratio.Yet because the frequency of carrier wave is more and more higher in the radio communication, the frequency of voltage controlled oscillator (VCO) is more and more higher, and is also more and more higher to the requirement of frequency divider.
See also Fig. 1, Fig. 1 is the circuit theory schematic diagram that removes pulse (Pulse Swallow) structure frequency divider that gulps down of prior art.Gulp down and remove pulse (Pulse Swallow) structure frequency divider and comprise pre-divider (Prescaler), program counter (ProgramCounter) and swallow counter (Swallow Counter), be widely used in integer type frequency synthesizer and the decimal type frequency synthesizer.Its operation principle is: the divider ratio of pre-divider is that P+1 is full until swallow counter number (mould is A); To change the divider ratio of pre-divider be P to rest-set flip-flop then, and program counter (mould is B) works on, and swallow counter quits work and begins until frequency division next time, and the divider ratio of whole frequency divider is PB+A.For guaranteeing to gulp down except that the pulse frequency divider operate as normal, the mould B of program counter must be greater than the mould A of swallow counter.Because program counter and swallow counter feed back to mould control signal (the Modulus Control of pre-divider, write a Chinese character in simplified form MC) output signal (being the input signal of program counter and Swallow counter) the existence time-delay of pre-divider relatively, and the speed of removing the pulse structure frequency divider that gulps down of prior art is subjected to certain restriction when process voltage temperature conditions (PVT) changes, for this reason, 2000, Christopher Lam and BehzadRazavi propose a kind of frequency divider, its structure as shown in Figure 2, (can be referring to IEEE JSSC, VOL.35, NO.5, MAY 2000, A 2.6-Ghz/5.2-GHz Frequency Synthesizer in 0.4-um CMOS Technology), promptly insert a d type flip flop that triggers by rising edge again by the pre-divider output signal at the output of rest-set flip-flop, eliminate the time-delay of counter thus, thereby improve the speed of frequency divider, frequency divider divider ratio after the improvement is PB+A+1, yet its frequency division speed still is difficult to satisfy the requirement of ever-increasing carrier frequency.
See also Fig. 3, Fig. 3 is the dual-modulus prescaler of prior art, and it is 128/129 to be example with divider ratio, also can adopt other divider ratio, such as removing 4/5, removes 8/9, removes 16/17 etc.The speed of the dual-modulus prescaler of this prior art is still limited, and main cause is that the output buffer buffer of VCO need drive the NAND gate in three first d type flip flops and the first d type flip flop feedback loop.And, to locate owing to have three first d type flip flops to be operated in full rate (VCO frequency) simultaneously, its power consumption is bigger.
For this reason, Jan Craninckx and Michiel S.J.Steyaert have proposed in 1996 to realize that with phase rotation device 128/129 pre-divider at a high speed (sees IEEE JSSC, VOL.31, NO.7, July 1996, A 1.75-GHz/3-VDual-Modulus Divide-by-128/129 Prescaler in 0.7-um CMOS), i.e. 128/129 pre-divider that removes as shown in Figure 4 based on phase rotation device, its input Fin connects the output of voltage controlled oscillator (VCO), output Fout linker counter and swallow counter, above-mentioned two counters feedback a mould control signal MC give pre-divider.The high-frequency signal process two-stage of VCO promptly differs the one-period of VCO output signal except that 2 circuit produces the phase place that 4 phase places differ 90 ° successively.Mould control signal MC and output Fout by the NAND Logic door produce frequency controller (Frequency Control) along triggering signal FC, have only when mould control signal MC is high level, just can produce the clock edge along triggering signal FC, frequency controller changes state when each clock edge (rising edge or trailing edge), select the phase place of contiguous time-delay, the similar finite state machine of its operation principle.If the signal of the current selection of phase rotation device is F4.I, then when MC was high level, through a clock edge, F4 selected the F4.Q signal, thereby the pre-divider divider ratio is 129 (being P+1).If mould control signal MC is a low level.The signal that F4 selects is constant, and the divider ratio of pre-divider is 128 (being P).The output signal of VCO only drives the first order and removes 2 frequency divider generation F2 signal, reduces the power consumption of the driving Buffer of VCO.The frequency of F2 signal has only half of VCO, produces the clock of four phases again except that 2 frequency divider through one-level.Therefore, compare traditional structure based on the pre-divider of phase rotation device (Phase Rotator) and can realize higher frequency division speed, and when same frequency division speed, lower circuit power consumption is arranged.
At present, decimal type (Frac-N) frequency synthesizer is because of its high-resolution and good noiseproof feature, and the application in the RF circuit is more and more wider.Because decimal type frequency synthesizer reference frequency height, frequency divider (Divider) divider ratio is little, thereby the mould of pre-divider can be very not big, is generally and removes 4/5, removes 8/9 and remove 16/17.So, can bring a problem, when the VCO signal frequency very high, the value of the mould of pre-divider hour, pre-divider with after can an existence tighter sequential relationship (Timing) between the counter that connects.Remove 8/9 pre-divider and the frequency divider of counter is an example to comprise, see also Fig. 5, when the output frequency of VCO was relatively low, the total divider ratio of frequency divider was 8B+A+1, but when the output frequency of VCO was higher, the total divider ratio of frequency divider was 8B+A.The reason that produces this phenomenon is: the selection of phase rotation device is controlled by frequency controller (FrequencyControl).Consider that from the angle of the stability of a system frequency controller generally is designed to along triggering, frequency controller shown in Figure 5 is designed to rising edge and triggers, and it is FC along triggering signal.Because the consideration of speed, noise, chip area and power consumption aspect, pre-divider generally adopts the structure of CML (CML) to realize, program counter and swallow counter generally adopt the CMOS logic realization, and the output signal Fpreout of pre-divider need connect counter modules such as buffer (Buffer) driver counter and swallow counter.Pre-divider is different to power requirement with counter module, therefore needs different locally supplied power source in the chip, and often spacing is bigger because locally supplied power source distributes, and causes pre-divider and counter module that certain distance is arranged in chip each other.The adding of buffer and the distance of intermodule cause the output signal Fpreout of pre-divider to there being bigger time-delay Td between the input signal Fcount of counter module.When the speed of VCO was higher, time-delay Td can be near half of Fpreout cycle of the output signal of pre-divider, thereby caused the logic generation deviation of circuit, frequency divider occurred and removed one phenomenon less.If B equals 5, A equals 2.As time-delay Td during less than half (T/2) in the output signal Fpreout cycle of pre-divider, as shown in Figure 6, in the cycle of each mould control signal MC, produce the pulse (Pulse) that A+1 (3) rise along triggering signal FC, thereby the total divider ratio of frequency divider is 8B+A+1.As time-delay Td during, as shown in Figure 7, in the cycle of each mould control signal MC, produces the pulse of A (2) rising along triggering signal FC, thereby the total divider ratio of frequency divider is 8 * B+A greater than half (T/2) in the output signal Fpreout cycle of pre-divider.This time-delay is influenced by technology, temperature and supply voltage.When the speed of VCO was very high, particularly to decimal type frequency synthesizer, this frequency division instability was very big to the systematic function influence, so a kind of frequency divider based on phase rotation device need be provided, can eliminate above-mentioned unsettled phenomenon.
Summary of the invention
Technical scheme to be solved of the present invention provides a kind of frequency divider based on phase rotation device, to solve the deficiencies in the prior art.
For solving technique scheme, the invention provides a kind of frequency divider based on phase rotation device, comprise: comprise phase rotation device at least and be used to control the pre-divider of the frequency controller of described phase rotation device, input connects the buffer of described pre-divider output, input all connects the program counter and the swallow counter of the output of described buffer, input connects the rest-set flip-flop of described program counter and described swallow counter, input connects the output of described rest-set flip-flop and the output that clock signal input terminal connects described buffer, and by first d type flip flop of first kind of triggering along triggering, its output connects described swallow counter, described frequency divider based on phase rotation device also comprises: by the sample circuit of second kind of triggering along triggering, its input connects the output of described first d type flip flop, its triggering signal input connects the output of described buffer, is used for the output signal of described first d type flip flop being sampled under triggering in described second kind of triggering; Two input logic gates, one input end connect the output of described buffer, another input connects the output of described second d type flip flop, its output connects described frequency controller, be used for when described second d type flip flop is output as required level, its output signal according to described buffer produces and along triggering signal described frequency controller is triggered accordingly, and then makes the frequency control signal of the described phase rotation device of described frequency controller output control.
Preferable, described sample circuit is one second d type flip flop.
Preferable, described first kind of triggering is along being rising edge, described second kind of triggering is trailing edge along signal.
Preferable, described required level is a high level, described two input logic gates are and door inclusive NAND door.
Preferable, described first kind of triggering is along being trailing edge, described second kind of triggering edge is a rising edge.
Preferable, described required level is a low level, described two input logic gates are or door or NOR gate.
Preferable, described first d type flip flop connects described sample circuit by one first not gate, and described employing circuit connects described or door or NOR gate by one second not gate.
Beneficial effect of the present invention is: the problem that efficiently solves frequency divider frequency division shakiness.
Description of drawings
Fig. 1 is the circuit theory schematic diagram that removes the pulse structure frequency divider that gulps down of prior art.
Fig. 2 is the circuit theory schematic diagram that removes the pulse structure frequency divider that gulps down of the MC Synchronization Control of prior art.
Fig. 3 is the circuit theory schematic diagram of the dual-modulus prescaler of prior art.
Fig. 4 is the circuit theory schematic diagram based on the pre-divider of phase rotation device of prior art.
Fig. 5 is the circuit theory schematic diagram based on the frequency divider of phase rotation device of prior art.
Fig. 6 for time-delay hour pre-divider output signal Fpreout, mould control signal MC, and along the sequential schematic diagram of triggering signal FC.
Fig. 7 is for output signal Fpreout, the mould control signal MC of time-delay pre-divider when big, and along the sequential schematic diagram of triggering signal FC.
Fig. 8 is the circuit theory schematic diagram of the frequency divider based on phase rotation device provided by the invention.
Fig. 9 is counting and control module circuit theory schematic diagram.
Figure 10 is output signal Fpreout, the first d type flip flop output signal MC, the second d type flip flop output signal MC1 of pre-divider, and along the sequential schematic diagram of triggering signal FC.
Figure 11 is output signal Fpreout, the first d type flip flop output signal MC and the burr schematic diagram that produces of pre-divider.
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Embodiment one
See also Fig. 8 and Fig. 9, the frequency divider based on phase rotation device provided by the invention comprises except that 8/9 pre-divider, reaches counting and control module.
The full speed (Full Speed) that comprises connection in turn except that 8/9 pre-divider is removed Unit two, is reached the frequency controller that is connected and is used for the signal selection of control phase circulator with phase rotation device except that Unit two, phase rotation device, low speed (Low Speed) except that Unit two, Half Speed (Half Speed).The input that removes at full speed Unit two connects the output signal Fin of voltage controlled oscillator (VCO), after output signal Fin removes Unit two through two-stage, become signal F4.I, F4.Q that 4 phase places differ 90 ° successively,
And
Input phase circulator, frequency controller be along under the control of triggering signal FC, the control phase circulator circulate successively select signal F4.I, F4.Q,
, and
After the output signal F4 of phase rotation device removes Unit two through low speed, become the output signal Fpreout of pre-divider.
Counting and control module comprise the counter module that comprises program counter and swallow counter, drive the buffer of described counter module, and generate the control module along triggering signal FC that is used for the control frequency controller.Control module comprise in turn the rest-set flip-flop that connects, first d type flip flop, second d type flip flop, and with an And.The clock signal input terminal of the output linker counter input of buffer, swallow counter input, first d type flip flop, the second d type flip flop clock signal input terminal reach an input with door And, make the output signal Fpreout of pre-divider count for program counter and swallow counter by the output signal Fcount as buffer behind the buffer, and as the clock signal of first d type flip flop and second d type flip flop, and as with the input signal of door And.The output of program counter and swallow counter connects two inputs of rest-set flip-flop respectively, so that replacement rest-set flip-flop, the output signal of rest-set flip-flop is imported first d type flip flop, the output signal MC of first d type flip flop imports second d type flip flop, and feed back to swallow counter, the output signal MC1 of second d type flip flop imports another input with door And, is connected the control end of frequency controller with the output of door And, and output is along triggering signal FC.
See also Figure 10, the present invention with the output signal MC1 of the output signal Fcount of buffer and second d type flip flop with, produce along triggering signal FC.The period T * of the output signal MC pulse duration=Fcount signal of first d type flip flop gulps down the mould A of pulse trigger.Same, with MC as input signal and adopt the Fcount signal to be equal to the pulse duration of MC as the pulse duration of the output signal MC1 of second d type flip flop of clock signal equally, yet, because the clock of second d type flip flop is along being different from first d type flip flop, promptly the clock of first d type flip flop edge is a rising edge, the clock edge of second d type flip flop is a trailing edge, then signal MC1 relative signal MC postpones T/2, it is the time-delay of signal MC1 relative signal Fcount time of delay=T/2+ second d type flip flop itself, because the time-delay of second d type flip flop is stable less than T/2, MC1 and Fcount and gained along triggering signal FC a frequency division in the cycle umber of pulse of gained constant be the value of mould A, and the pulse duration of FC almost is equal to the pulse duration of Fcount, thereby has solved the frequency division problem of unstable.
Present embodiment do not adopt Fcount signal and MC signal directly with the scheme of generation along triggering signal FC, see also Figure 11, because the time-delay that circuit has, the relative Fcount of MC has a little time-delay, if MC and Fcount carry out the logical AND effect and will produce the very narrow burr of pulse duration (glitch), burr is unsettled to the triggering of frequency controller.
In the present embodiment, rising edge is first kind of triggering edge, and trailing edge is second kind of triggering edge, second d type flip flop is actually a sample circuit, and its clock signal input terminal is essentially a triggering signal input, second kind of triggering under trigger, the MC signal is sampled, obtain the MC1 signal.Also can be NAND gate with door And.
Embodiment two
Present embodiment is with the different of embodiment one, employing or door have substituted and door, and corresponding one first not gate that between first d type flip flop and second d type flip flop, inserts, second d type flip flop and or door between insert one second not gate, changing trailing edge is first kind of triggering edge, and rising edge is second kind of triggering edge.Because present embodiment has adopted or door substitutes and door, then required level becomes low level by high level, when Fcount and MC1 are low level simultaneously, or an output low level.Or door also can be NOR gate.
The invention solves the frequency division problem of unstable that output frequency as VCO produces when very high.The method that solves is in technology and control module place mould control signal MC to be done sequential processing, and with the output signal Fcount of buffer and the signal MC1 after the sequential processing by two input logic gates, what produce frequency controller is transferred to pre-divider along triggering signal FC, rather than directly passes mould control signal MC to pre-divider.Because being the local signal that stability is high, time-delay is little, FC produces, its anti-interference is good especially, be not subjected to technology, supply voltage and variation of temperature, and the FC signal from two input logic gates transfer to frequency controller time-delay do not influence the result of frequency divider, thereby the frequency division of frequency divider is highly stable.
Above embodiment is the unrestricted technical scheme of the present invention in order to explanation only.Any modification or partial replacement that does not break away from spirit and scope of the invention, such as, will be revised as the pre-divider of other divider ratios except that 8/9 pre-divider; The clock edge of FC is revised as the rising edge and the trailing edge of the control section of trailing edge and corresponding change generation FC signal; To replace to other gates with door, as with or the door etc.; Call the position of first d type flip flop and second d type flip flop and the clock edge of corresponding modify miscellaneous part etc.; All should be encompassed in the middle of the claim scope of the present invention.
Claims (7)
1. frequency divider based on phase rotation device, comprise: comprise phase rotation device at least and be used to control the pre-divider of the frequency controller of described phase rotation device, input connects the buffer of described pre-divider output, input all connects the program counter and the swallow counter of the output of described buffer, input connects the rest-set flip-flop of described program counter and described swallow counter, input connects the output of described rest-set flip-flop and the output that clock signal input terminal connects described buffer, and by first d type flip flop of first kind of triggering along triggering, its output connects described swallow counter, it is characterized in that described frequency divider based on phase rotation device also comprises:
By second kind of triggering along the sample circuit that triggers, the output that its input connects described first d type flip flop, its triggering signal input connects the output of described buffer, is used for the output signal of described first d type flip flop being sampled under triggering in described second kind of triggering;
Two input logic gates, one input end connect the output of described buffer, another input connects the output of described second d type flip flop, its output connects described frequency controller, be used for when described second d type flip flop is output as required level, its output signal according to described buffer produces and along triggering signal described frequency controller is triggered accordingly, and then makes the frequency control signal of the described phase rotation device of described frequency controller output control.
2. the frequency divider based on phase rotation device as claimed in claim 1 is characterized in that: described sample circuit is one second d type flip flop.
3. the frequency divider based on phase rotation device as claimed in claim 1 is characterized in that: described first kind of triggering is along being rising edge, and described second kind of triggering is trailing edge along signal.
4. the frequency divider based on phase rotation device as claimed in claim 3 is characterized in that: described required level is a high level, and described two input logic gates are and door inclusive NAND door.
5. the frequency divider based on phase rotation device as claimed in claim 1 is characterized in that: described first kind of triggering is along being trailing edge, and described second kind of triggering edge is a rising edge.
6. the frequency divider based on phase rotation device as claimed in claim 5 is characterized in that: described required level is a low level, and described two input logic gates are or door or NOR gate.
7. the frequency divider based on phase rotation device as claimed in claim 6 is characterized in that: described first d type flip flop connects described sample circuit by one first not gate, and described employing circuit connects described or door or NOR gate by one second not gate.
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| CN2009100546397A CN101944906A (en) | 2009-07-10 | 2009-07-10 | Frequency divider based on phase rotator |
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| CN2009100546397A CN101944906A (en) | 2009-07-10 | 2009-07-10 | Frequency divider based on phase rotator |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103959654A (en) * | 2011-11-28 | 2014-07-30 | 高通股份有限公司 | Dividing a frequency by 1.5 to produce a quadrature signal |
| CN105811967A (en) * | 2014-12-31 | 2016-07-27 | 北京华大九天软件有限公司 | Circuit for generating fractional frequency-division clock based on HDMI standard |
| CN106249016A (en) * | 2015-06-11 | 2016-12-21 | 安立股份有限公司 | Sample circuit, the method for sampling, sampling oscilloscope and method for displaying waveform |
| CN112953530A (en) * | 2021-01-28 | 2021-06-11 | 厦门星宸科技有限公司 | Frequency eliminator circuit |
-
2009
- 2009-07-10 CN CN2009100546397A patent/CN101944906A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103959654A (en) * | 2011-11-28 | 2014-07-30 | 高通股份有限公司 | Dividing a frequency by 1.5 to produce a quadrature signal |
| CN103959654B (en) * | 2011-11-28 | 2016-08-24 | 高通股份有限公司 | For frequency being carried out 1.5 frequency dividings with the method and apparatus producing orthogonal signalling |
| CN105811967A (en) * | 2014-12-31 | 2016-07-27 | 北京华大九天软件有限公司 | Circuit for generating fractional frequency-division clock based on HDMI standard |
| CN105811967B (en) * | 2014-12-31 | 2018-08-07 | 北京华大九天软件有限公司 | Circuit in HDMI standard for generating fractional frequency division clock |
| CN106249016A (en) * | 2015-06-11 | 2016-12-21 | 安立股份有限公司 | Sample circuit, the method for sampling, sampling oscilloscope and method for displaying waveform |
| CN112953530A (en) * | 2021-01-28 | 2021-06-11 | 厦门星宸科技有限公司 | Frequency eliminator circuit |
| CN112953530B (en) * | 2021-01-28 | 2024-02-23 | 星宸科技股份有限公司 | Frequency divider circuit |
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Application publication date: 20110112 |