CN101938645A

CN101938645A - Video-compression intra-frame prediction 4*4 mode hardware parallel realization structure

Info

Publication number: CN101938645A
Application number: CN 200910108171
Authority: CN
Inventors: 王明江; 张爱平; 颜琥; 刘辉
Original assignee: Shenzhen Graduate School Harbin Institute of Technology
Current assignee: Shenzhen Graduate School Harbin Institute of Technology
Priority date: 2009-07-03
Filing date: 2009-07-03
Publication date: 2011-01-05

Abstract

In an H.262/AVC (Advanced Video Coding) system, an intra-frame prediction 4*4 mode is an important mode for reducing space relevant information. The intra-frame prediction 4*4 mode requires nine calculation modes comprising vertical prediction, horizontal prediction, DC prediction, left lower opposite-angle prediction, right lower opposite-angle prediction, vertical right lower angle prediction, horizontal inclined lower angle prediction, vertical left lower angle prediction and horizontal inclined upper angle prediction. An intra-frame prediction module requires a large quantity of operations, if the serial calculation is carried out, a great quantity of clock periods can be consumed. A large-capacity FPGA (Field Programmable Gata Array) or ASIC (Application Specific Integrated Circuit) mode is adopted for a higher-definition video coding system, and utilizing a hardware parallel structure for realizing the H.264/AVC system is a good selection for overcoming calculating bottlenecks. The invention adopts the parallel system structure for accomplishing intra-frame 4*4 prediction and adopts a plurality of Wallace array structures for realizing each prediction mode in parallel, thereby achieving higher performance.

Description

Video compression infra-frame prediction 4 * 4 pattern hardware Parallel Implementation structures

Technical field

The present invention relates to a kind of video compression intra-frame 4 * 4 forecasting model hardware Parallel Implementation method and framework.Belong to the digital video decoding technical field.

Background technology

In video coding system H.264/AVC, estimation, infra-frame prediction, transform/quantization, block elimination filtering etc. need a large amount of computings.Existing market to more than the high definition H.264/AVC the video coding demand constantly increase, and adopt high-end DSP mode to realize that H.264/AVC bottleneck constantly appears calculating in the scheme of video coding.Adopt big capacity FPGA or ASIC mode, utilize the hardware parallel organization to realize more than the high definition that H.264/AVC video coding system is the fine selection of some market products.

Infra-frame prediction 4 * 4 patterns need be calculated nine kinds of patterns altogether, comprise that vertical prediction, horizontal forecast, DC prediction, the prediction of diagonal angle, lower-left, lower-right diagonal position prediction, the prediction of vertical right inferior horn, the oblique inferior horn prediction of level, the prediction of vertical left inferior horn and level tiltedly go up the angle prediction.If serial computing will consume a large amount of clock cycle, and FPGA or ASIC implementation has enough hardware resources, adopt parallel architecture to finish intra-frame 4 * 4 forecasting model and can realize superior performance.

Summary of the invention

The present invention is a kind of implementation method of video compression infra-frame prediction 4 * 4 pattern hardware Parallel Implementation structures.

4 * 4 frame modes select to divide following several steps to finish:

1, selects a kind of 4 * 4 patterns, and generate 4 * 4 prediction piece;

2, calculate Cost4 * 4.Adopt SAD to handle residual error data.

3, to 9 pattern repeating steps 1～2 of all 4 * 4 predictions, choose have minimum Cost4 * pattern of 4 values is the best 4 * 4 patterns.

4, to all 16 4 * 4 repeating steps 1～3 in the current macro, each Cost4 * 4 additions.

5, calculate last 4 * 4 patterns of selecting and the value of Cost4 * 4 (SSD) between the coded picture block;

The present invention finishes 9 patterns in 1,2,3 steps by hardware Parallel Implementation mode, then by relatively calculating minimum Cost4 * 4 values; Adopt the mode of serial computing to finish 16 4 * 4 cost function in the macro block for step 4.

Description of drawings

Fig. 1 is 4 * 4 frame mode parallel computation hardware structure diagrams.

Fig. 2 is the vertical prediction hardware structure diagram.

Fig. 3 is the horizontal forecast hardware structure diagram.

Fig. 4 is a DC prediction hardware structure chart.

Fig. 5 is diagonal angle, a lower-left prediction hardware structure chart.

Fig. 6 is a lower-right diagonal position prediction hardware structure chart.

Fig. 7 is a vertical right inferior horn prediction hardware structure chart.

Fig. 8 is the oblique inferior horn prediction hardware of a level structure chart.

Fig. 9 is a vertical left inferior horn prediction hardware structure chart.

Figure 10 is that level tiltedly goes up angle prediction hardware structure chart.

Embodiment

The present invention is based on following method realizes.Infra-frame prediction 4 * 4 optimal modes select step as follows:

Referring to Fig. 1, read in data line of the end of top adjacent macroblocks, preceding 4 pixel datas of the minimum delegation of upper right side macro block, the adjacent macroblocks rightmost side, left side pixel value by external memory storage.Utilize nine kinds of prediction mode parallel computations to obtain nine prediction pieces respectively.Calculate the residual error between prediction piece and original 4 * 4, ask for sad value; Table look-up by quantization parameter Qp and to obtain λ _ModeAnd R (s, c, mode/Qp); Go up according to this three calculation of parameter Cost4 * 4=SAD+ λ _Mode* R (s, c, mode/Qp); Cost4 * 4 of comparing nine kinds of patterns, selecting that minimum pattern is current 4 * 4 the best 4 * 4 patterns.To in the current macro all 16 4 * 4 repeat above-mentioned steps, each Cost4 that obtains * 4 is finished adds up.Calculate last 4 * 4 patterns of selecting and the value of Cost4 * 4 (SSD) between the coded picture block;

The hardware Parallel Implementation structure of nine kinds of predictive modes is seen Fig. 2～10.

Claims

1. video compression infra-frame prediction 4 * 4 pattern hardware Parallel Implementation structures is characterized in that nine kinds of predictive modes to 4 * 4 adopt parallel hardware architecture, promptly calculate the cost value of nine kinds of predictive modes simultaneously, relatively and select the minimum cost value; The minimum cost value of one 16 * 16 macro block is the result of all minimum cost value additions of 4 * 4 in the macro block.

2. the parallel hardware architecture of nine kinds of predictive modes to 4 * 4 according to claim 1 is characterized in that at every kind of predictive mode, all adopts a plurality of Wallace array structure Parallel Implementation.Nine kinds of predictive mode hardware configurations comprise that vertical prediction hardware configuration, horizontal forecast hardware configuration, DC prediction hardware structure, diagonal angle, lower-left prediction hardware structure, lower-right diagonal position prediction hardware structure, vertical right inferior horn prediction hardware structure, the oblique inferior horn prediction hardware of level structure, vertical left inferior horn prediction hardware structure and level tiltedly go up angle prediction hardware structure.

3. DC predict according to claim 2, but it is characterized in that when the top and left side neighbor time spent, above adopting and the left side mean value of totally 8 pixels as prediction, but when the left side neighbor time spent, adopt the left side mean value of totally 4 pixels as prediction, but when the top neighbor time spent, above the employing mean value of totally 4 pixels as prediction.Three kinds of situations adopt three cover hardware to walk abreast and finish.

4. diagonal angle, lower-left according to claim 2 prediction hardware structure, it is characterized in that adopting 16 Wallace array Parallel Implementation, all Wallace arrays are input as the pixel value that three adjacent blocks are used to predict, 16 predicted values that the output of all arrays obtains walking abreast through 2 gts.

5. lower-right diagonal position prediction hardware structure according to claim 2, it is characterized in that adopting 16 Wallace array Parallel Implementation, all Wallace arrays are input as the pixel value that three adjacent blocks are used to predict, 16 predicted values that the output of all arrays obtains walking abreast through 2 gts.

6. vertical right inferior horn prediction hardware structure according to claim 2 is characterized in that adopting 4 adders, 12 Wallace array Parallel Implementation.Adder and the input of Wallace array are the pixel values that adjacent block is used to predict, adder result of calculation moves to right one and produces 4 predicted values, and the output of Wallace array obtains 12 predicted values through 2 gts.

7. the oblique inferior horn prediction hardware of level according to claim 2 structure is characterized in that adopting 7 adders, 9 parallel finishing of Wallace array.Adder and the input of Wallace array are the pixel values that adjacent block is used to predict, adder result of calculation moves to right one and produces 7 predicted values, and the output of Wallace array obtains 9 predicted values through 2 gts.

8. vertical left inferior horn prediction hardware structure according to claim 2 is characterized in that adopting 8 adders, 8 parallel finishing of Wallace array.Adder and the input of Wallace array are the pixel values that adjacent block is used to predict, adder result of calculation moves to right one and produces 8 predicted values, and the output of Wallace array obtains 8 predicted values through 2 gts.

9. level according to claim 2 tiltedly goes up angle prediction hardware structure, it is characterized in that adopting 4 adders, 12 parallel finishing of Wallace array.Adder and the input of Wallace array are the pixel values that adjacent block is used to predict, adder result of calculation moves to right one and produces 4 predicted values, and the output of Wallace array obtains 12 predicted values through 2 gts.