CN101938348B - Clock regeneration method taking standard clock/data as reference - Google Patents
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- CN101938348B CN101938348B CN 201010240835 CN201010240835A CN101938348B CN 101938348 B CN101938348 B CN 101938348B CN 201010240835 CN201010240835 CN 201010240835 CN 201010240835 A CN201010240835 A CN 201010240835A CN 101938348 B CN101938348 B CN 101938348B
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Abstract
The invention discloses a clock regeneration method taking a standard clock/data as reference, which comprises the following steps of: generating a regeneration clock by a local high-speed processing clock, setting an expected phase for the regeneration clock, tracking and compensating the error phase between the current phase and the expected phase for the regeneration clock, and continually adjusting the phase of the regeneration clock output by the local high-speed processing clock according to the compensating result. The invention has the advantages of providing a new clock regeneration method, solving the problem that clock regeneration cannot be performed due to non-uniform duty ratio of reference signals, strictly ensuring a phase relationship between the reference input and the regeneration clock without relating with relative frequency deviation, ensuring the accuracy of the regenerative data and the reliability of link transmission and setting the relative phases of the regeneration clock and the input reference.
Description
Technical field
The present invention relates to a kind of communication technology, relate in particular to a kind of clock regeneration method take clock/data as reference.
Background technology
In the communications field, some interfaces communicated data signal, interface does not comprise clock signal, such as the HDB3 code, clock information transmits by data; Some interfaces, while communicated data signal and clock signal, such as B interface, clock information directly transmits by clock signal; On various interface, data are subject to the outer signals interference certain shake often, and interface circuit need to pass through analog circuitry processes simultaneously, and this duty ratio that can cause reference signal is inhomogeneous, process therefore need interface circuit to carry out clock regeneration, so that data are recovered and subsequent treatment.
Therefore, the target of clock regeneration utilizes reference signal to carry out clock regeneration exactly, overcomes the inhomogeneous impact of duty ratio of shake and reference signal, and the docking port data are carried out correct sampling and decoding, guarantees the correctness of playback of data and the reliability of link transmission.
Generally adopt XOR circuit to carry out phase demodulation with clock as the clock regeneration circuit with reference to input, as shown in Figure 2, in order to accelerate locking time and to realize simple, the interface clock regenerative circuit adopts first-order loop, but this method, require the reference clock duty ratio even, affect loop performance if the inhomogeneous phase characteristic of reference clock duty ratio changes thereupon.
Generally adopt the double edge detection circuit to carry out phase demodulation with data as the clock regeneration circuit with reference to input, as shown in Figure 3, in order to accelerate locking time and to realize simple, first-order loop is adopted in interface clock regeneration, same, if the inhomogeneous phase characteristic of reference data duty ratio will change, thereby affects loop performance thereupon.
Traditional clock regeneration circuit produces regeneration time clock by bidirectional counter in addition, utilize direction and the stepping amount that subtract pulse is adjusted counter that add of phase discriminator generation, because the precision problem of counter causes the phase accuracy of regeneration time clock relatively poor, the regeneration time clock shake is larger.
Summary of the invention
for solving prior art existence reference clock (data) duty ratio is had relatively high expectations, the relative phase of regeneration time clock and input reference changes with frequency deviation, the problems such as the phase accuracy of regeneration time clock is relatively poor, the present invention proposes a kind of clock regeneration method take clock/data as reference, by local high speed processing clock generating regeneration time clock, for regeneration time clock is set expectation phase place (the expectation phase place refers to the relative phase between reference input and regeneration time clock), the current phase place of regeneration time clock and the error phase between the expectation phase place are followed the tracks of and compensated, according to compensation result, constantly adjust the regeneration time clock of local high speed processing clock output.
The method concrete steps are:
1) set the expectation phase theta
set, described expectation phase theta
setValue be 0 °～360 °.
2) determine reference clock/data phase reference point, extract current phase place corresponding to regeneration time clock, calculation expectation phase theta at phase reference point
setAnd the error phase θ between current phase place
e(i), comprising:
1] reference clock/data are carried out the edge and detect, choose 0 ° of phase point of reference clock/data as the phase reference point;
2] extract the current phase place of regeneration time clock corresponding phase reference point and be designated as θ (i-1);
3] calculation expectation phase theta
setError phase θ with current phase place
e(i), θ
e(i)=θ
set-θ (i-1); I=1,2,3...n.
3) to error phase θ
e(i) carry out successively loop gain processing, cumulative Phase Processing and phase accumulator and process, comprising:
1] loop gain is processed: K* θ
e(i); K is the gain multiple, and the K value is less than 2
-8
2] cumulative Phase Processing: Δ θ (i)=θ
0+ K* θ
e(i); θ
0Be fixing accumulation amount; θ
0=2
m* (f
in/ f
s), wherein, m is the precision of phase accumulator, more than getting 16bit; f
inIt is the frequency of reference signal; f
sIt is local high speed processing clock frequency.
3] phase accumulator is processed: θ (i)=θ (i-1)+Δ θ (i);
θ (i) is the i time phase accumulator result, and θ (i-1) is the current phase place of the regeneration time clock corresponding phase reference point extracted when last time calculating; I=1,2,3...n; When i=1, θ (i-1)=θ (0)=0.
4) according to phase accumulator result θ (i) place quadrant, local high speed processing clock output regeneration time clock, comprise: as phase accumulator result θ (i) one, during two quadrant, the regeneration time clock of local high speed processing clock output low level, when the phase accumulator result three, during four-quadrant, the regeneration time clock of local high speed processing clock output high level.
Completing steps 4) after processing, repeating step 2) to 4), continue subsequent treatment.
Previously described reference clock/data are: clock, RZ code or NRZ code.
Useful technique effect of the present invention is: a kind of new clock regeneration method is provided, overcome because of the inhomogeneous problem that can't carry out clock regeneration of reference signal duty ratio of transmitting or the signal processing causes, but the docking port data are carried out correct sampling and decoding, setting by the expectation phase place, can the strict guarantee reference input and regeneration time clock between phase relation, and and relative frequency deviation irrelevant; Guaranteed the correctness of playback of data and the reliability of link transmission, the relative phase of regeneration time clock and input reference can be set, and the phase place that produces regeneration time clock by digital controlled oscillator can obtain higher phase accuracy.
Description of drawings
Fig. 1, realize the present invention program's clock regeneration circuit;
XOR phase discriminator take clock as reference in Fig. 2, prior art;
Double edge detection phase discriminator take data as reference in Fig. 3, prior art;
Fig. 4, the edge sense circuit take the RZ code as reference data;
Fig. 5, the edge sense circuit take the NRZ code as reference data;
Fig. 6, the edge detection waveform schematic diagram take clock as reference
Fig. 7, the edge detection waveform schematic diagram take data (RZ code) as reference;
Fig. 8, the edge detection waveform schematic diagram take data (NRZ code) as reference;
The regeneration time clock design sketch of Fig. 9, the XOR phase discriminator take clock as reference;
The regeneration time clock design sketch of Figure 10, the XOR phase discriminator take the RZ code as reference;
Figure 11, take clock as reference, the regeneration time clock design sketch of processing through the present invention program;
Figure 12, take the RZ code as reference, the regeneration time clock design sketch of processing through the present invention program;
Figure 13, Figure 14, take the RZ code as reference, but the expectation phase place is different, through the regeneration time clock design sketch of the present invention program's processing.
Embodiment
Referring to Fig. 1, the present invention program is: by local high speed processing clock generating regeneration time clock, for regeneration time clock is set the expectation phase place, the current phase place of regeneration time clock and the error phase between the expectation phase place are followed the tracks of and compensated, according to compensation result, constantly adjust the phase place of the regeneration time clock of local high speed processing clock output.Its concrete steps are:
1) set the expectation phase theta
set, 2) and determine reference clock/data phase reference point, extract current phase place (also namely extracting the current phase place of regeneration time clock corresponding phase reference point) corresponding to regeneration time clock, calculation expectation phase theta at phase reference point
setAnd the error phase θ between current phase place
e(i), 3) to error phase θ
e(i) carry out successively that loop gain is processed, cumulative Phase Processing and phase accumulator process, 4) according to phase accumulator result θ (i) place quadrant, the regeneration time clock after local high speed processing clock output is processed; Repeating step 2) to 4); Whole processing procedure consists of a closed-loop control reponse system.
The present invention program's principle is: by step 2) link is to error phase θ
e(i) carry out Continuous Tracking, and by step 3) link to error phase θ
e(i) carry out real-Time Compensation, at last by step 4) link adjusts output, and then returns to step 2) carry out circular treatment; The solution of the present invention has not only avoided prior art because of the inhomogeneous problem that can't carry out clock regeneration of reference signal duty ratio, and can be to error phase θ
e(i) carry out Continuous Tracking, adjust in real time, guaranteed the correctness of playback of data and the reliability of link transmission.
Step 1) in, the expectation phase theta
setCan be selected 0 °～360 ° scopes according to actual needs, the expectation phase theta
setIn general, no longer adjust in the follow-up operation process, only change has been occured the needs of regeneration time clock phase place.
Step 2) concrete treatment step is:
1] standard time clock/data are carried out the edge and detect, 0 ° of phase point of selection standard clock/data is as the phase reference point;
2] extract the current phase place of regeneration time clock corresponding phase reference point and be designated as θ (i-1);
3] calculation expectation phase theta
setError phase θ with current phase place
e(i), θ
e(i)=θ
set-θ (i-1); I=1,2,3...n.
Described reference clock/data are: clock, RZ code or NRZ code, reference clock/data are carried out the edge detects and phase demodulation output is processed (referring to Fig. 4,5, be respectively the exemplary circuit of the edge sense circuit of RZ code and NRZ code shown in figure for reference input), choose the phase reference point from phase demodulation output; For the ease of calculating and subsequent treatment, the preferred phase reference point of standard time clock/data that the present invention chooses is 0 ° of phase point, can also choose other phase points as the reference phase point, but need to introduce correction, relative complex in processing.
Referring to Fig. 6,7, if reference signal is clock or RZ code, the upper jumping edge of a reference signal detection, i.e. 0 of corresponding reference signal ° of phase point, utilize high-frequency clock that reference signal is latched, export the pulse signal that a width equals the high-frequency clock cycle and export as phase demodulation; Referring to Fig. 8, if reference signal is the NRZ code, need upper jumping and the lower jumping edge of reference signal detection, two edges are 0 ° of phase point of corresponding reference signal all, utilize high-frequency clock that reference signal is latched, export the pulse signal that a width equals the high-frequency clock cycle and export as phase demodulation.
Step 3) in, to error phase θ
e(i) carrying out successively loop gain processing, cumulative Phase Processing and phase accumulator processes:
Described loop gain is treated to K* θ
e(i); K is the gain multiple; Large loop gain can be accelerated locking time, but also can introduce larger regeneration time clock shake simultaneously, and the inventor has proposed a kind of preferred scheme, makes the shake of locking time and regeneration time clock all more satisfactory, and namely the K value is less than 2
-8
Described cumulative Phase Processing is Δ θ (i)=θ
0+ K* θ
e(i); θ
0Be fixing accumulation amount; Cumulative Phase Processing result when Δ θ (i) is the i time calculating, i=1,2,3...n; Wherein, θ
0=2
m* (f
in/ f
s), m is the precision of phase accumulator, more than getting 16bit; f
inIt is the frequency of reference signal; f
sIt is local high speed processing clock frequency.Fixing accumulation amount θ
0Determined the free oscillation frequency of the output regeneration time clock of phase accumulator.
Described phase accumulator is processed (being phase accumulator): θ (i)=θ (i-1)+Δ θ (i); θ (i) is the i time phase accumulator result, and θ (i-1) is the current phase place of the regeneration time clock corresponding phase reference point extracted when last time calculating; I=1,2,3...n; When i=1 when computing (carry out for the 1st time phase accumulator processes), θ (i-1)=θ (0) gets θ (0)=0 this moment.
Cumulative Phase Processing and phase accumulator are processed the effect that in fact these two parts have realized digital controlled oscillator (DCO).
Step 4) in, according to phase accumulator result θ (i), control the regeneration time clock after local high speed processing clock output is processed; Specifically be treated to: when the phase accumulator result one, during two quadrant, the regeneration time clock of local high speed processing clock output low level, when the phase accumulator result three, during four-quadrant, the regeneration time clock of local high speed processing clock output high level.
Step 4) after the end, return to step 2), again extract the current phase place of regeneration time clock corresponding phase reference point, and continue subsequent step.
Come the further bright the solution of the present invention of analysing below by complete treatment step, take the 1st time and the n time processing procedure as example:
1, take standard time clock/data as benchmark, choose the phase reference point;
2, extract the current phase theta (0) of regeneration time clock corresponding phase reference point;
3, calculation expectation phase theta
setError phase θ with current phase place
e(1), θ
e(1)=θ
set-θ (0);
4, to error phase θ
e(1) carrying out loop gain processes: K* θ
e(1);
5, to the loop gain result Phase Processing that adds up: Δ θ (1)=θ
0+ K* θ
e(1);
6, cumulative Phase Processing being carried out phase accumulator processes: owing to being the 1st calculating, namely the value of θ (0) is 0, therefore θ (1)=θ (0)+Δ θ (1)=Δ θ (1);
7, according to the corresponding quadrant of θ (1), the output of local high speed processing clock is adjusted; Return to step 2, continue to process ... begin the n time and process:
The current phase theta (n-1) of n2, extraction regeneration time clock corresponding phase reference point;
N3, calculation expectation phase theta
setError phase θ with current phase place
e(n), θ
e(n)=θ
set-θ (n-1);
N4, to error phase θ
e(n) carrying out loop gain processes: K* θ
e(n);
N5, to the loop gain result Phase Processing that adds up: Δ θ (n)=θ
0+ K* θ
e(n);
N6, cumulative Phase Processing is carried out phase accumulator process: θ (n)=θ (n-1)+Δ θ (n);
N7, according to the corresponding quadrant of θ (n), the output of local high speed processing clock is adjusted; Return to step 2, continue to process ...;
Below by comparing to analyze the present invention program with prior art, Fig. 9 is directly to observe reference input and regeneration time clock by oscilloscope to the waveform of Figure 14, in figure, following waveform is reference input, and in figure, the waveform of top is regeneration time clock, and regeneration time clock is as trigger source:
Fig. 9,10 is depicted as respectively take clock and RZ data as reference signal, adopts XOR circuit to carry out the regeneration time clock design sketch of phase demodulation, and the relative frequency deviation scope of reference input is-and 50ppm is to 50ppm.The phase relation that can find out regeneration time clock and reference source when frequency deviation changes also changes thereupon.May cause the docking port data can not carry out correct sampling and decoding, the correctness of playback of data and the reliability of link transmission are reduced.
Being respectively shown in Figure 11,12 take clock and RZ data as reference signal, adopting the present invention program to carry out the regeneration time clock design sketch of phase demodulation, the relative frequency deviation scope of reference input is-50ppm is to 50ppm.When as can be seen from the figure frequency deviation changes, the phase relation of regeneration time clock and reference source remains unchanged.Can the docking port data carry out correct sampling and decoding, guarantee the correctness of playback of data and the reliability of link transmission.
Shown in Figure 13,14, reference source is the RZ data, employing the present invention program's of the expectation phase value that correspondence is different respectively regeneration time clock design sketch, as can be seen from the figure, can expect by change the phase relation of phase value and then change regeneration clock and reference source, carry out correct sampling and decoding to guarantee the docking port data, guarantee the correctness of playback of data and the reliability of link transmission.
In sum, the present invention program does not have strict requirement to the duty ratio of reference signal, and reference input can be clock or data, and is not subject to the frequency deviation impact.By thereby the different expectation phase places clock phase relation different with reference source that obtain regenerating is set, and the setting by the expectation phase place (can't arrange phase place in prior art, there is not the concept of expectation phase place) yet, can the strict guarantee reference input and regeneration time clock between phase relation, and and relative frequency deviation irrelevant; Have simple in structure, convenient, flexible, the characteristics that strong adaptability and reliability are high.
Claims (4)
1. clock regeneration method take standard time clock/data as reference, by local high speed processing clock generating regeneration time clock, it is characterized in that: for regeneration time clock is set the expectation phase place, the current phase place of regeneration time clock and the error phase between the expectation phase place are followed the tracks of and compensated, according to compensation result, constantly adjust the phase place of the regeneration time clock of local high speed processing clock output;
The method concrete steps are: 1) set the expectation phase theta
set, 2) and determine reference clock/data phase reference point, extract current phase place corresponding to regeneration time clock, calculation expectation phase theta at phase reference point
setAnd the error phase θ between current phase place
e(i), 3) to error phase θ
e(i) carry out successively that loop gain is processed, cumulative Phase Processing and phase accumulator process, 4) according to phase accumulator result θ (i) place quadrant, local high speed processing clock output regeneration time clock; Repeating step 2) to 4);
Step 2) comprising:
1] reference clock/data are carried out the edge and detect, choose 0 ° of phase point of reference clock/data as the phase reference point;
2] extract the current phase place of regeneration time clock corresponding phase reference point and be designated as θ (i-1);
3] calculation expectation phase theta
setError phase θ with current phase place
e(i), θ
e(i)=θ
set-θ (i-1); I=1,2,3...n;
Described reference clock/data are: clock, RZ code or NRZ code.
2. the clock regeneration method take standard time clock/data as reference according to claim 1 is characterized in that: in step 1), and described expectation phase theta
setValue be 0 °～360 °.
3. the clock regeneration method take standard time clock/data as reference according to claim 1, it is characterized in that: step 3) comprises:
1] loop gain is processed: K* θ
e(i); K is the gain multiple, and the K value is less than 2
-8
2] cumulative Phase Processing: Δ θ (i)=θ
0+ K* θ
e(i); θ
0Be fixing accumulation amount; θ
0=2
m* (f
in/ f
s), wherein, m is the precision of phase accumulator, more than getting 16bit; f
inIt is the frequency of reference signal; f
sIt is local high speed processing clock frequency;
3] phase accumulator is processed: θ (i)=θ (i-1)+Δ θ (i);
θ (i) is the i time phase accumulator result, and θ (i-1) is the current phase place of the regeneration time clock corresponding phase reference point extracted when last time calculating; I=1,2,3...n; When i=1, θ (i-1)=θ (0)=0.
4. the clock regeneration method take standard time clock/data as reference according to claim 1, it is characterized in that: step 4) comprises, as phase accumulator result θ (i) one, during two quadrant, the regeneration time clock of local high speed processing clock output low level, when the phase accumulator result three, during four-quadrant, the regeneration time clock of local high speed processing clock output high level.
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| CN101938348B true CN101938348B (en) | 2013-05-22 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1117220A (en) * | 1993-12-25 | 1996-02-21 | 日本电气株式会社 | Clock signal regeneration method and apparatus |
| CN101207436A (en) * | 2007-12-12 | 2008-06-25 | 上海华为技术有限公司 | Apparatus and method of feedback time-delay phase locking as well as phase error detection unit |
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| JP4725445B2 (en) * | 2006-07-14 | 2011-07-13 | ソニー株式会社 | Playback device and tracking control method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1117220A (en) * | 1993-12-25 | 1996-02-21 | 日本电气株式会社 | Clock signal regeneration method and apparatus |
| CN101207436A (en) * | 2007-12-12 | 2008-06-25 | 上海华为技术有限公司 | Apparatus and method of feedback time-delay phase locking as well as phase error detection unit |
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