CN101937931B - High performance field effect transistor and manufacturing method thereof - Google Patents
High performance field effect transistor and manufacturing method thereof Download PDFInfo
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- CN101937931B CN101937931B CN201010268632A CN201010268632A CN101937931B CN 101937931 B CN101937931 B CN 101937931B CN 201010268632 A CN201010268632 A CN 201010268632A CN 201010268632 A CN201010268632 A CN 201010268632A CN 101937931 B CN101937931 B CN 101937931B
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Abstract
The invention provides a high performance field effect transistor, comprising a substrate, a grid pile arranged above the substrate, a source/drain region which is arranged at the two sides of the grid pile and in the substrate as well as a carbon containing thin layer which is arranged between the source/drain region and the substrate. The invention adopts the carbon containing thin layer such as Si: C thin layer or SiGe: C thin layer, impurity in the source/drain region can be effectively inhibited from spreading to a channel and the substrate, thus improving the property of device.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of high performance field effect transistors and forming method thereof.
Background technology
At present, along with constantly dwindling of field-effect transistor characteristic size, the impurity that the source/drain regions middle and high concentration mixes in the technology of follow-up high annealing will be diffused in the raceway groove, thereby causes that transistor performance worsens.Therefore, the doping content of impurity is restricted in the source/drain regions at present, and for example, the concentration of impurity B is lower than 10 in the PMOS of strain Si
21Cm
-3In addition, if polycrystalline Si of adopt mixing or polycrystal SiGe as grid, then the thickness along with gate dielectric layer is more and more thinner, the impurity of high concentration is B or P etc. for example, be easy to penetrate gate dielectric layer and arrive channel region, thus the deterioration of aggravation device performance.
Summary of the invention
The object of the invention is intended to solve at least one of above-mentioned technological deficiency, particularly solves the impurity that mixes in the prior art source/drain regions defective to the raceway groove diffusion.
For achieving the above object, one aspect of the present invention proposes a kind of high performance field effect transistors, comprising: substrate; The grid that are positioned on the said substrate pile up; Be positioned at said grid and pile up the source/drain regions among both sides and the said substrate; And the carbon containing thin layer between said source/drain regions and said substrate.
The present invention has also proposed a kind of formation method of high performance field effect transistors on the other hand, may further comprise the steps: substrate is provided; On said substrate, forming grid piles up and side wall; The said substrate of etching forms the source/drain regions groove to pile up both sides at said grid; In said source/drain regions groove, form the carbon containing thin layer; With in said groove and on the said carbon containing thin layer, form source/drain regions.
The present invention is through the carbon containing thin layer, and for example Si:C thin layer or SiGe:C thin layer can suppress in the source/drain regions impurity effectively to the diffusion of raceway groove and substrate, thereby improve device performance.In addition; The doping content of source/drain regions can be provided through the present invention; Thereby reduce the series resistance of source/drain regions, for example, can the doping content of B in the PMOS device source/drain regions be brought up to 21 powers from 20 original powers through the embodiment of the invention; Even 22 powers, thereby significantly improve device performance.
In a preferred embodiment of the invention, if adopt polycrystalline Si or polycrystal SiGe gate, also can in grid pile up, increase grid carbon containing thin layer, thereby can prevent that the impurity in polycrystalline Si or the polycrystal SiGe gate from spreading to raceway groove, thereby further improve device performance.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize through practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously with easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1-3 is the high performance field effect transistors sketch map of the embodiment of the invention;
Fig. 4-6 is the structural representation of the intermediate steps of the formation method of the high performance field effect transistors of formation embodiment.
Embodiment
Describe embodiments of the invention below in detail, the example of said embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Be exemplary through the embodiment that is described with reference to the drawings below, only be used to explain the present invention, and can not be interpreted as limitation of the present invention.
Disclosing of hereinafter provides many various embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between various embodiment that discuss of institute and/or the setting.In addition, various specific technology and the examples of material that the invention provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.In addition; First characteristic of below describing second characteristic it " on " structure can comprise that first and second characteristics form the embodiment of direct contact; Can comprise that also additional features is formed on the embodiment between first and second characteristics, such first and second characteristics possibly not be direct contacts.
As shown in Figure 1, be the high performance field effect transistors sketch map of the embodiment of the invention.This device architecture comprises substrate 100, be positioned at grid on the substrate 100 piles up 200, is positioned at grid and piles up the source/drain regions 400 among 200 both sides and the substrate 100, and the carbon containing thin layer 300 between source/drain regions 400 and substrate 100.In one embodiment of the invention, this carbon containing thin layer 300 comprises Si:C thin layer or SiGe:C thin layer, and wherein C content is about 0.1% to 10%, and its thickness is about 0.5nm to 10nm, is preferably 1nm to 5nm.This carbon containing thin layer 300 can suppress in the source/drain regions impurity effectively to the diffusion of raceway groove and substrate, thereby improves device performance.In addition; The doping content of source/drain regions can be provided through the present invention; Thereby reduce the series resistance of source/drain regions, for example, can the doping content of B in the PMOS device source/drain regions be brought up to 21 powers from 20 original powers through the embodiment of the invention; Even 22 powers, thereby significantly improve device performance.In addition, the existence of carbon containing thin layer 300 also can not destroy the lattice structure that is right after epitaxial loayer.Wherein, in an embodiment of the present invention, source/drain regions 400 is Si, SiGe or Ge source/drain regions.
In one embodiment of the invention; As shown in Figure 2; Grid pile up 200 and comprise gate dielectric layer 210, are positioned at the grid carbon containing thin layer 220 on the gate dielectric layer 210 and are positioned at polycrystalline Si grid or the polycrystal SiGe grid 230 on the grid carbon containing thin layer 220, and the cover layer 240 that covers polycrystalline Si grid or polycrystal SiGe grid 230.Through the grid carbon containing thin layer 220 that increases, thereby can prevent that the impurity in polycrystalline Si or the polycrystal SiGe gate from spreading to raceway groove, thereby further improve device performance.
In one embodiment of the invention, as shown in Figure 3, source/drain regions 400 can have the structure of raising.
For the clearer above-mentioned semiconductor structure of understanding embodiment of the invention proposition; The invention allows for the embodiment of the method that forms above-mentioned semiconductor structure; It should be noted that those skilled in the art can select kinds of processes to make for example dissimilar product lines according to above-mentioned semiconductor structure; Different processes flow process or the like; If but the semiconductor structure that these technologies are made adopts and the essentially identical structure of said structure of the present invention, reach essentially identical effect, so also should be included within protection scope of the present invention.In order clearerly to understand the present invention; Below will specifically describe the method and the technology that form said structure of the present invention, need to prove that also following steps only are schematic; Be not limitation of the present invention, those skilled in the art also can realize through other technologies.
Shown in Fig. 4-6, be the structural representation of the intermediate steps of the formation method of the high performance field effect transistors that forms embodiment, this method may further comprise the steps:
S11 provides substrate 100.In an embodiment of the present invention, substrate 100 is the Si substrate.
S12 forms grid and piles up 200 and one or more layers side wall on substrate 100, as shown in Figure 4.Particularly, earlier on the Si substrate, form gate dielectric layer, then deposit polysilicon gate (can be in-situ doped, or deposit is carried out polysilicon after intact and injected), deposit one deck tetrem oxygen is posted silane (TEOS) then.Utilize photoetching and combine lithographic method, define grid and pile up pattern.Wherein, utilize dry etching that oxide layer is removed, and in the etching process of polysilicon, this oxide layer can also be served as the effect of hard mask.On this basis, deposit one deck TEOS or SiN layer utilize reactive ion etching (reactive ion etching) to form the side wall of grid stacked structure then again.
In a preferred embodiment of the invention, can on gate dielectric layer, form grid carbon containing thin layer.In an embodiment of the present invention, grid carbon containing thin layer can pass through ald (ALD), chemical treatment, rpcvd (RPCVD) or high vacuum chemical vapour deposition (UHVCVD) formation.
Wherein, preferably, adopt chemical treatment to form.Particularly, if adopt the chemical treating process method, then need carry out the hydrogen passivation to silicon face.Wherein, the connotation of hydrogen passivation is that the silicon layer outer surface contains hydrogen atom, i.e. formation-Si-H key.This method that can cause the hydrogen passivation can adopt hydrofluoric acid or any similar solution that the hydrogen passivation can be provided of dilution.
After silicon surface is carried out the hydrogen Passivation Treatment; Again through an iodine/alcohol solution (iodine/alcohol) treatment process; To form the carbon containing thin layer in silicon surface, the thickness of this carbon containing thin layer is an atomic monolayer or several atomic monolayers, and this thin layer also possibly contain a spot of oxygen.Particularly, this treatment process has adopted a kind of solution of being made up of iodine and alcohols, and the preparation method of this solution is added on both together and then mixing fully.Wherein, the method for using of iodine/alcohol solution comprises submergence, brushes, soaks and mould, spray or any similar coating processes.In addition, this solution also can be evaporated and become the gas phase amalgam.Usually at room temperature (20 ℃) are used iodine/alcohol solution, can certainly under high slightly temperature, carry out.The processing time of this solution and silicon face is depended on iodine and the alcohols content in solution.Typically, the processing time is about 5 minutes to 90 minutes, preferred 15 minutes to 45 minutes.The content of iodine in solution is about 1 * 10
-5To 1 * 10
-2Mole, preferred 5 * 10
-4Mole.
After silicon face is handled through iodine/alcohol solution; Be processed the structure that finishes and adopt alcohol solution flushing and dry; The alcohols content that wherein is used to wash is not limited to the content of iodine/alcohol solution; Can adopt common drying process to comprise typical surface tension drying means, promptly adopt a kind of mist that constitutes by isopropyl alcohol (isopropanol) and water.
In another embodiment of the present invention, can also adopt chemical gaseous phase depositing process, for example the method for UHCVD precipitates grid carbon containing thin layer on gate medium, and in this embodiment, gate medium both can be the SiO that uses always
2, also can adopt the gate dielectric material of high k dielectric constant, for example, HfO
2, Al
2O
3, Ta
2O
5Deng, perhaps any other similar gate dielectric layers.On gate medium, deposit very thin and have the polycrystalline Si of device grade quality: C or SiGe:C layer, the content of its C is about 0.1% to 10%.The thickness of this polycrystalline Si: C or SiGe:C layer is about 0.5nm to 10nm, preferred 1nm to 5nm.This grid carbon containing thin layer both can prevent the N type impurity (for example P) in the polysilicon gate effectively, also can prevent p type impurity (for example B) effectively, penetrated gate medium and entered into raceway groove, thereby make the performance of device worsen.
S13, etched substrate 100 forms source/drain regions groove 1100 to pile up 200 both sides at grid, and is as shown in Figure 5.In an embodiment of the present invention, the formation of source/drain regions groove 1100 can be adopted has the very lithographic method of high selectivity to substrate 100 and spacer material, HCl for example, and it is higher than SiO far away the etch rate of silicon
2Etch rate.Particularly, in an exemplary embodiments of the present invention, etching technics is 900 ℃ of following etchings 500 seconds, at H
2The dividing potential drop of HCl is 50mTorr in the atmosphere.
S14 removes the Cl atom on source/drain regions groove 1100 surfaces.In an exemplary embodiments of the present invention, adopt high temperature to cure and remove the Cl atom, for example 900 ℃ were cured 2 minutes.
S15 forms carbon containing thin layer 300 in source/drain regions groove 1100, as shown in Figure 6.Equally, can pass through ald (ALD), chemical treatment or high vacuum chemical vapour deposition (UHVCVD) forms.
S16, epitaxial source/drain 400 optionally on carbon containing thin layer 300, for example the SiGe source/drain regions 400, carry out in-situ doped, as shown in Figure 1 simultaneously.For example for the PMOS transistor, can in-situ doped B, its concentration can be from 1 * 10
18To 1 * 10
22Cm
-3
The present invention is through the carbon containing thin layer, and for example Si:C thin layer or SiGe:C thin layer can suppress in the source/drain regions impurity effectively to the diffusion of raceway groove and substrate, thereby improve device performance.In addition; The doping content of source/drain regions can be provided through the present invention; Thereby reduce the series resistance of source/drain regions, for example, can the doping content of B in the PMOS device source/drain regions be brought up to 21 powers from 20 original powers through the embodiment of the invention; Even 22 powers, thereby significantly improve device performance.
In a preferred embodiment of the invention, if adopt polycrystalline Si or polycrystal SiGe gate, also can in grid pile up, increase grid carbon containing thin layer, thereby can prevent that the impurity in polycrystalline Si or the polycrystal SiGe gate from spreading to raceway groove, thereby further improve device performance.
Although illustrated and described embodiments of the invention; For those of ordinary skill in the art; Be appreciated that under the situation that does not break away from principle of the present invention and spirit and can carry out multiple variation, modification, replacement and modification that scope of the present invention is accompanying claims and be equal to and limit to these embodiment.
Claims (10)
1. a field-effect transistor is characterized in that, comprising:
Substrate;
The grid that are positioned on the said substrate pile up, and said grid pile up and comprise: gate dielectric layer, be positioned at grid carbon containing thin layer on the said gate dielectric layer, be positioned at polycrystalline Si grid or polycrystal SiGe grid on the said grid carbon containing thin layer;
Be positioned at said grid and pile up the source/drain regions among both sides and the said substrate; With
Carbon containing thin layer between said source/drain regions and said substrate, said carbon containing thin layer comprises Si:C thin layer or SiGe:C thin layer.
2. field-effect transistor as claimed in claim 1 is characterized in that, the thickness of said carbon containing thin layer is 0.5nm-10nm.
3. field-effect transistor as claimed in claim 1 is characterized in that said source/drain regions has the structure of raising.
4. field-effect transistor as claimed in claim 1 is characterized in that, said source/drain regions is Si, SiGe or Ge source/drain regions.
5. the formation method of a field-effect transistor is characterized in that, may further comprise the steps:
Substrate is provided;
On said substrate, form grid and pile up and side wall, wherein, form said grid and pile up and comprise:
On said substrate, form gate dielectric layer;
On said gate dielectric layer, form grid carbon containing thin layer;
On said grid carbon containing thin layer, form polycrystalline Si grid or polycrystal SiGe grid, and said polycrystalline Si grid or polycrystal SiGe grid are mixed; The said substrate of etching forms the source/drain regions groove to pile up both sides at said grid;
In said source/drain regions groove, form the carbon containing thin layer, said carbon containing thin layer comprises Si:C thin layer or SiGe:C thin layer; With
In said groove and on the said carbon containing thin layer, form source/drain regions.
6. the formation method of field-effect transistor as claimed in claim 5 is characterized in that, the thickness of said carbon containing thin layer is 0.5nm-10nm.
7. the formation method of field-effect transistor as claimed in claim 5; It is characterized in that said carbon containing thin layer and said grid carbon containing thin layer form through ald ALD, chemical treatment, rpcvd RPCVD or high vacuum chemical vapour deposition UHVCVD.
8. the formation method of field-effect transistor as claimed in claim 7 is characterized in that, said chemical treatment further comprises:
Carry out surperficial hydrogen passivation;
At surface-coated iodine/alcohol solution; With
After 5-90 minute, adopt alcohol solution to clean and drying.
9. the formation method of field-effect transistor as claimed in claim 7 is characterized in that, said source/drain regions is Si, SiGe or Ge source/drain regions.
10. the formation method of field-effect transistor as claimed in claim 5 is characterized in that, said source/drain regions forms through selective epitaxial.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202305A (en) * | 2006-12-13 | 2008-06-18 | 恩益禧电子股份有限公司 | Semiconductor device with improved source and drain and method of manufacturing the same |
| CN101241936A (en) * | 2007-02-07 | 2008-08-13 | 国际商业机器公司 | Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof |
| CN101621071A (en) * | 2008-07-04 | 2010-01-06 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor device and manufacturing method thereof |
| CN101740513A (en) * | 2008-11-18 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | MOS (Metal Oxide Semiconductor) transistor and fabricating method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101202305A (en) * | 2006-12-13 | 2008-06-18 | 恩益禧电子股份有限公司 | Semiconductor device with improved source and drain and method of manufacturing the same |
| CN101241936A (en) * | 2007-02-07 | 2008-08-13 | 国际商业机器公司 | Semiconductor structure including doped silicon carbon liner layer and method for fabrication thereof |
| CN101621071A (en) * | 2008-07-04 | 2010-01-06 | 中芯国际集成电路制造(上海)有限公司 | Metal oxide semiconductor device and manufacturing method thereof |
| CN101740513A (en) * | 2008-11-18 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | MOS (Metal Oxide Semiconductor) transistor and fabricating method thereof |
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