CN101930744B - Handshake protocol method for AAC audio coding - Google Patents

Abstract

The invention relates to a handshake protocol method for AAC audio coding, which comprises the following steps: transferring voice signals to an FPGA after the voice signals are sampled by an analog-to-digital chip (AD), and caching the voice signals in a first-in first-out data buffer (FIFO) of the FPGA; when data stored by an FIFO1 is more than data of one frame for AAC coding, setting indication signals 1 to high, otherwise setting the indication signals to low; if a DSP detects that the indication signals 1 are low, continuing the detection, and if the DSP detects that the indication signals 1 are high, taking away the data of one frame for coding; and after coding, utilizing the DSP to detect indication signals 2 at the FPGA end (whether FIFO2 is half-full), if the indication signals 2 are high, sending a long frame to the FPGA, and if the indication signals 2 are low, sending a short frame, wherein the constant rate of the output code stream for an AAC coding is ensured by the FIFO caching and the long/short frame mechanism.

Description

A Handshake Protocol Method for AAC Audio Coding

(1) Technical field:

The invention relates to a handshake protocol method, in particular to a handshake protocol method of AAC audio coding. belongs to the field of communication.

(two) background technology:

The AAC (Advanced Audio Coding) standard was completed in 1997. It has been used and tested by BBC (British Broadcasting Corporation) and NHK (Japan Broadcasting Corporation) to show that it can provide quite high sound quality for low bit rate multi-channel coding. In the case of the same sound quality, the compression rate of AAC is 30% higher than that of MP3, and under the stereo 128kbps, it can reach the sound quality close to CD.

In the practical application of AAC, there are usually certain requirements on the sampling rate of the sound signal and the coded stream rate, but the sound sampling clock and the output stream clock may be non-homologous, and it is difficult to guarantee the constant output stream rate; and because The compression rate of AAC encoding is related to the input. In the case of changes in the input sound signal, if there is no corresponding adjustment mechanism, it is difficult to guarantee the constant rate of the output code stream.

(3) Contents of the invention:

The purpose of the present invention is to propose a handshake protocol method for AAC audio coding, so as to solve the problem that the output code stream is required to maintain a constant rate at a specific sampling rate in the actual application of the prior art.

The technical scheme of the present invention is summarized as: voice signal enters FPGA after sampling by analog-to-digital conversion chip (AD), and is buffered in the first-in-first-out data buffer (FIFO) of FPGA, when FIFO storage data amount is greater than AAC encoding required The number of one frame, set the indicator signal 1 to high, otherwise set it to low; if the DSP detects that the indicator signal 1 is low, it will continue to detect, if it detects that the indicator signal 1 is high, then take a frame of data and encode ; After encoding, the DSP detects the FPGA terminal indication signal 2 (whether the FIFO storing the encoded data in the FPGA is half full), if it is high, it sends a long frame to the FPGA, if it is low, it sends a short frame to the FPGA, and caches it through the FIFO And the long and short frame mechanism ensures that the rate of the AAC encoded output stream is constant.

A kind of handshake protocol method of AAC audio coding of the present invention, its concrete steps are as follows:

step 1:

After the voice signal is collected by the analog-to-digital conversion chip, the obtained PCM code enters the FPGA and is stored in the FIFO in the FPGA. When the data stored in the FIFO reaches the number of one frame required by the AAC code, the corresponding indicator signal of the FIFO is set to High; if the amount of data in the FIFO is less than the number of frames required for AAC encoding, the corresponding indicator signal is set to low.

Step 2:

DSP detects the indication signal 1 of storing the data FIFO to be encoded in the FPGA, and the indication signal 1 represents the data quantity of the data FIFO after encoding in the FPGA, if the indication signal is low, then continue to detect the signal; if the indication signal is high, from A frame of data is taken from the FIFO, and then the DSP encodes the frame of data.

Step 3:

After the encoding is completed, the DSP detects the indication signal 2 of the FPGA. The indication signal 2 represents the data quantity of the FIFO storing the encoded data in the FPGA. If the data volume in the FIFO storing the encoded data is greater than half of the FIFO capacity, the indication signal 2 is set to low. ; Otherwise, set indicator signal 2 high. If the DSP detects that the indication signal 2 is high, it sends long-frame data to the FPGA, and if it detects that the indication signal 2 is low, it sends short-frame data to the FPGA.

Step 4:

The FPGA sends the encoded data stored in the FIFO at a constant rate, and the DSP continues to detect the indication signal of the FIFO storing the data to be encoded in the FPGA.

The advantages and effects of the present invention are: by buffering the data stream and using long and short frames through the handshake mechanism to ensure the constant rate of the output code stream, it is suitable for the requirements of AAC audio coding.

(4) Description of drawings:

FIG. 1 is a hardware architecture diagram of the present invention.

Fig. 2 is the handshake flowchart of DSP of the present invention.

(5) Specific implementation methods:

The technical scheme of the present invention is summarized as: speech signal enters FPGA after sampling by analog-to-digital conversion chip (AD), and is buffered in the first-in-first-out data buffer (FIFO) of FPGA, when FIFO1 storage data amount is greater than AAC encoding required For one frame of data, set the indicator signal 1 to high, otherwise set it to low; if the DSP detects that the indicator signal 1 is low, it will continue to detect, if it detects that the indicator signal 1 is high, it will take a frame of data and encode ;After encoding, the DSP detects the FPGA terminal indication signal 2 (whether FIFO2 is half full), if it is high, it sends a long frame to the FPGA, if it is low, it sends a short frame, and the AAC code output is guaranteed through the FIFO buffer and the long and short frame mechanism The stream rate is constant.

The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings. The main steps are as follows:

step 1:

As shown in Figure 1, connect hardware devices. After the voice signal is collected by AD, the obtained PCM (pulse code modulation) is coded into FPGA and stored in FIFO1 in FPGA. Among them, the AD chip adopts PCM4204 of TI Company, the sampling frequency is 44100Hz, works in the main mode, and the data format is I2S; the FPGA adopts CycloneEP1C12Q240C8 of Altera Company; the depth of FIFO is 1024, the width is 32, and the stored data is 16-bit PCM code. When the data stored in the FIFO reaches the number of one frame required by AAC encoding, the corresponding indicator signal 1 of the FIFO is set to high; if the amount of data in the FIFO is less than the number of one frame required by AAC encoding, the corresponding indicator signal is set to low. Among them, one frame of data required by AAC encoding is 1024 sampling points, and 16-bit PCM encoding.

Step 2:

As shown in the upper part of Figure 2, the DSP detects the indication signal 1 corresponding to the FIFO1 storing the data to be encoded in the FPGA. If the indication signal is low, continue to detect the signal; if the indication signal is high, take a Frame data, and then DSP encodes the frame data. DSP adopts TMS320C6727 of TI Company, reads data from FIFO1 through EMIF mouth (DSP's external memory interface).

Step 3:

As shown in the lower part of Figure 2, after the encoding is completed, the DSP detects the indicating signal 2 of the FPGA. This signal represents the data quantity of the encoded data FIFO2 stored in the FPGA. If the amount of data in FIFO2 is greater than half of the FIFO capacity, the signal is set to is low; otherwise, the signal is set high. If the DSP detects that the indication signal 2 is high, it sends the long-frame encoded data to the FPGA, and if it detects that the indication signal is low, it sends the short-frame encoded data to the FPGA. Among them, the depth of FIFO2 in FPGA is 512, and the width is 32 bits; DSP writes data into FIFO2 through EMIF port; the length of long frame data is 372 bytes, and the length of short frame data is 360 bytes. Through the buffer mechanism and the long and short frame mechanism, it is guaranteed that a certain amount of data is always buffered in FIFO2, and FIFO2 will not appear empty or full.

Step 4:

FPGA sends out the coded data stored in FIFO2 at a constant rate, and DSP continues to detect the indicating signal 1 of FPGA. Among them, the rate at which the FPGA sends encoded data is 128kbps. Since a certain amount of data is always buffered in FIFO2, there will be no empty or full situation, which can ensure a constant output stream rate.

The meanings of the English abbreviations appearing in the accompanying drawings of this manual are as follows:

PCM: pulse code modulation;

FIFO: first-in-first-out data buffer;

AD: Analog-to-digital conversion chip.

Claims (5)

1. A handshake protocol method of AAC audio encoding, characterized in that, comprising the following steps: step 1: After the voice signal is collected by the analog-to-digital conversion chip, the obtained pulse code modulation code to be encoded enters the FPGA and is stored in the first-in-first-out data buffer in the FPGA. When the data stored in the first-in-first-out data buffer reaches the AAC encoding The number of frames required, the corresponding indicator signal of the first-in-first-out data buffer is set to high; if the number of data in the first-in-first-out data buffer is less than the number of frames required by AAC encoding, the corresponding indicator signal is set to Low; Step 2: DSP detects the indication signal of the first-in-first-out data buffer storing the pulse code modulation code to be encoded in the FPGA, if the indication signal of the first-in first-out data buffer storing the pulse code modulation code to be encoded in the FPGA is low, then continue to detect This signal; if the indication signal of the first-in-first-out data buffer storing the pulse code modulation code to be encoded in the FPGA is high, a frame of data is taken from the first-in first-out data buffer, and then the DSP encodes the frame of data ; Step 3: If the amount of data in the first-in-first-out data buffer for storing encoded data in the FPGA is greater than half of the capacity, then the indication signal of the first-in-first-out data buffer for storing encoded data in the FPGA is set to low; The indication signal of the first-in-first-out data buffer of the encoded data is set high; the DSP detects the indication signal of the first-in-first-out data buffer of the encoded data stored in the FPGA, and if the first-in first-out data of the encoded data stored in the FPGA is detected When the indication signal of the buffer is high, the data after the long frame encoding is sent to the FPGA, and if the indication signal of the first-in-first-out data buffer storing the encoded data in the FPGA is detected to be low, then the data after the short frame encoding is sent to the FPGA; Step 4: The FPGA sends the coded data stored in the first-in-first-out data buffer at a constant rate, and the DSP continues to detect the indication signal stored in the first-in-first-out data buffer of the pulse code modulation code to be encoded in the FPGA. 2. according to the described method of claim 1, wherein: analog-to-digital conversion chip adopts PCM4204 of TI company, and sampling frequency is 44100Hz, works in master mode, and data format is I2S; FPGA adopts Cyclone EP1C12Q240C8 of Altera company; First-in-first-out data cache The depth of the device is 1024, the width is 32, and the stored data is a 16-bit pulse code modulation code; AAC encoding requires a frame of data with 1024 sampling points and a 16-bit pulse code modulation code. 3. The method according to claim 1, wherein: the DSP adopts TMS320C6727 of TI Company, and reads data from the first-in-first-out data buffer through the external memory interface of the DSP. 4. method according to claim 1, wherein: DSP writes data in first-in-first-out data buffer by EMIF mouth, the depth of first-in-first-out data buffer in FPGA is 512, and width is 32 bits; Long frame data The length is 372 bytes, and the length of the short frame data is 360 bytes. 5. The method according to claim 1, wherein: the rate at which the FPGA sends encoded data is constant at 128kbps.

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