CN101930744B

CN101930744B - Handshake protocol method for AAC audio coding

Info

Publication number: CN101930744B
Application number: CN2010102745097A
Authority: CN
Inventors: 毛峡; 姜磊
Original assignee: Beihang University
Current assignee: Beihang University
Priority date: 2010-09-07
Filing date: 2010-09-07
Publication date: 2012-06-06
Anticipated expiration: 2030-09-07
Also published as: CN101930744A

Abstract

The invention relates to a handshake protocol method for AAC audio coding, which comprises the following steps: transferring voice signals to an FPGA after the voice signals are sampled by an analog-to-digital chip (AD), and caching the voice signals in a first-in first-out data buffer (FIFO) of the FPGA; when data stored by an FIFO1 is more than data of one frame for AAC coding, setting indication signals 1 to high, otherwise setting the indication signals to low; if a DSP detects that the indication signals 1 are low, continuing the detection, and if the DSP detects that the indication signals 1 are high, taking away the data of one frame for coding; and after coding, utilizing the DSP to detect indication signals 2 at the FPGA end (whether FIFO2 is half-full), if the indication signals 2 are high, sending a long frame to the FPGA, and if the indication signals 2 are low, sending a short frame, wherein the constant rate of the output code stream for an AAC coding is ensured by the FIFO caching and the long/short frame mechanism.

Description

A kind of handshake protocol method of AAC audio coding

(1) technical field:

The present invention relates to a kind of handshake protocol method, especially a kind of handshake protocol method of AAC audio coding.Belong to the communications field.

(2) background technology:

AAC (Advanced Audio Coding) standard was accomplished in 1997, used and its multi-channel encoder to low bit rate of test shows can provide quite high sound quality through BBC (British Broadcasting Corporation) and NHK (Japan Broadcasting Corporation).Under identical tonequality situation, the AAC compressibility is higher by 30% than MP3, and under stereo 128kbps, can reach the tonequality near CD.

In the practical application of AAC, usually the sampling rate of voice signal and the stream rate behind the coding are had certain requirement, and sampled voice clock and output code flow clock possibly be non-homogeneous, the output code flow constant rate is difficult to guarantee; And because the compressibility of AAC coding is relevant with input, under the situation that input audio signal changes, if no corresponding regulation mechanism, the constant rate of output code flow also is difficult to guarantee.

(3) summary of the invention:

The objective of the invention is to propose a kind of handshake protocol method of AAC audio coding,, require output code flow to keep the problem of constant rate to solve in the prior art practical application under the particular sample rate.

Technical scheme of the present invention is summarised as: voice signal gets into FPGA after modulus conversion chip (AD) sampling; Be buffered in the data buffer (FIFO) of the FIFO of FPGA; When FIFO stores data volume greater than the required number of frames of AAC coding; Indicator signal 1 is set to height, otherwise is changed to low; DSP then continues to detect if detect indicator signal 1 for low, if detect indicator signal 1 for high, then takes frame data away, encodes; Coding back DSP detects FPGA end indicator signal 2 (whether the FIFO of FPGA stored coding back data reaches half-full); If high, then send long frame, if low to FPGA; Then send short frame, guarantee AAC coding output code flow constant rate through FIFO buffer memory and length frame mechanism to FPGA.

The handshake protocol method of a kind of AAC audio coding of the present invention, its concrete steps are following:

Step 1:

Voice signal is after modulus conversion chip is gathered, and the pcm encoder that obtains gets into FPGA and also is stored among the FIFO in the FPGA, and when the data of FIFO stored reach the encode quantity of a required frame of AAC, the indicator signal that this FIFO is corresponding is changed to height; If data bulk is less than the required number of frames of AAC coding in the FIFO, corresponding indicator signal is changed to low.

Step 2:

DSP detects the indicator signal 1 of FPGA stored data to be encoded FIFO, and indicator signal 1 characterizes the data bulk of FPGA stored coding back data FIFO, if this indicator signal is low, then continues to detect this signal; If this indicator signal is high, from FIFO, take frame data away, DSP carries out encoding operation to these frame data then.

Step 3:

After the coding completion, DSP detects the indicator signal 2 of FPGA, and the data bulk of indicator signal 2 sign FPGA stored coding back data FIFO as if half greater than the FIFO capacity of data volume in the data FIFO behind the memory encoding, then is changed to indicator signal 2 low; Otherwise, indicator signal 2 is changed to height.DSP then sends long frame data to FPGA if detect indicator signal 2 for high, if detect indicator signal 2 for low, then sends short frame data to FPGA.

Step 4:

The data that FPGA will be stored in behind the coding among the FIFO send with constant rate of speed, and DSP continues to detect the indicator signal of FPGA stored data to be encoded FIFO.

Advantage of the present invention and effect are: through data are flow to row cache, and use the length frame to guarantee the output code flow constant rate through handshake mechanism, be applicable to the requirement of AAC audio coding.

(4) description of drawings:

Fig. 1 is hardware structure figure of the present invention.

Fig. 2 is the handshake procedure figure of DSP of the present invention.

(5) practical implementation method:

Technical scheme of the present invention is summarised as: voice signal gets into FPGA after modulus conversion chip (AD) sampling; Be buffered in the data buffer (FIFO) of the FIFO of FPGA; When FIFO1 stores data volume greater than the required frame data of AAC coding; Indicator signal 1 is set to height, otherwise is changed to low; DSP then continues to detect if detect indicator signal 1 for low, if detect indicator signal 1 for high, then takes frame data away, encodes; Behind the coding, DSP detects FPGA end indicator signal 2 (it is half-full whether FIFO2 reaches), if high, then sends long frame to FPGA, if low, then sends short frame, guarantees AAC coding output code flow constant rate through FIFO buffer memory and length frame mechanism.

Below in conjunction with accompanying drawing technical scheme of the present invention is done further to describe in detail.Key step is following:

Step 1:

As shown in Figure 1, connection hardware equipment.Voice signal is after AD gathers, and the PCM that obtains (pulse code modulation (PCM)) coding gets into FPGA and is stored among the FIFO1 in the FPGA.Wherein the AD chip adopts the PCM4204 of TI company, and SF is 44100Hz, is operated in holotype, and data layout is I2S; FPGA adopts the CycloneEP1C12Q240C8 of altera corp; The degree of depth of FIFO is 1024, and width is 32, and the data of storage are 16 pcm encoders.When the data of FIFO stored reach the AAC required number of frames of encoding, the indicator signal 1 that this FIFO is corresponding is changed to height; If data bulk is less than the AAC required number of frames of encoding in the FIFO, corresponding indicator signal is changed to low.Wherein, the AAC required frame data of encoding are 1024 sampled points, 16 pcm encoders.

Step 2:

Shown in Fig. 2 the first half, DSP detects the corresponding indicator signal 1 of FPGA stored data to be encoded FIFO1, if this indicator signal is low, then continues to detect this signal; If this indicator signal is high, from FIFO, take frame data away, DSP carries out encoding operation to these frame data then.DSP adopts the TMS320C6727 of TI company, through EMIF mouth (external memory interface of DSP) reading of data from FIFO1.

Step 3:

Shown in Fig. 2 the latter half, after the completion of encoding, the indicator signal 2 of DSP detection FPGA, the data bulk of this characterization FPGA stored coding back data FIFO 2, as if the interior data volume of FIFO2 half greater than the FIFO capacity, then this signal is changed to low; Otherwise this signal is changed to height.DSP then sends long frame coding back data to FPGA if detect indicator signal 2 for high, if it is low detecting this indicator signal, then sends short frame coding back data to FPGA.Wherein the degree of depth of FIFO2 is 512 among the FPGA, and width is 32; DSP writes data through the EMIF mouth in FIFO2; Long frame data length is 372 bytes, and short frame data length is 360 bytes.Through buffering and length frame mechanism, guarantee in the FIFO2 data of buffer memory some all the time, sky or full situation can not appear in FIFO2.

Step 4:

The data that FPGA will be stored in behind the coding among the FIFO2 send with constant rate of speed, and DSP continues to detect the indicator signal 1 of FPGA.Wherein the speed of the data behind the FPGA transmission coding is 128kbps.Because sky or full situation can not appear in the data of buffer memory some all the time among the FIFO2, can guarantee the constant rate of output code flow.

The english abbreviation that occurs in the Figure of description, its implication is following:

PCM: pulse code modulation (PCM);

FIFO: the data buffer of FIFO;

AD: analog-to-digital conversion chip.

Claims

1. the handshake protocol method of an AAC audio coding is characterized in that, comprises following several steps:

Step 1:

Voice signal is after modulus conversion chip is gathered; The impulse coding modulation code to be encoded that obtains gets among the FPGA; Be stored in the FIFO data buffering device in the FPGA; When the data of FIFO data buffer stored reach the required number of frames of AAC coding, the indicator signal that this FIFO data buffering device is corresponding is changed to height; If data bulk is less than the required number of frames of AAC coding in the FIFO data buffering device, corresponding indicator signal is changed to low;

Step 2:

DSP detects the indicator signal of the FIFO data buffering device of FPGA stored impulse coding modulation code to be encoded, and the indicator signal of the FIFO data buffering device of the impulse coding modulation code to be encoded as if the FPGA stored is low, then continues to detect this signal; If the indicator signal of the FIFO data buffering device of the impulse coding modulation code that the FPGA stored is to be encoded is high, from the FIFO data buffer, take frame data away, DSP carries out encoding operation to these frame data then;

Step 3:

If data volume half the greater than capacity in the FIFO data buffering device of FPGA stored coding back data, then the indicator signal with the FIFO data buffering device of FPGA stored coding back data is changed to low; Otherwise, the indicator signal of the FIFO data buffering device of data behind the FPGA stored coding is changed to height; DSP detects the indicator signal of the FIFO data buffering device of FPGA stored coding back data; Be height if detect the indicator signal of the FIFO data buffering device of FPGA stored coding back data; Then send long frame coding back data to FPGA; If it is low detecting the indicator signal of the FIFO data buffering device of FPGA stored coding back data, then send short frame coding back data to FPGA;

Step 4:

The data that FPGA will be stored in behind the coding in the FIFO data buffering device send with constant rate of speed, and DSP continues to detect the indicator signal of FPGA stored impulse coding modulation code FIFO data buffering device to be encoded.

2. according to the said method of claim 1, wherein: modulus conversion chip adopts the PCM4204 of TI company, and SF is 44100Hz, is operated in holotype, and data layout is I2S; FPGA adopts the Cyclone EP1C12Q240C8 of altera corp; The degree of depth of FIFO data buffering device is 1024, and width is 32, and the storage data are 16 digit pulse coded modulation codes; The AAC required frame data of encoding are 1024 sampled points, 16 digit pulse coded modulation codes.

3. according to the said method of claim 1, wherein: DSP adopts the TMS320C6727 of TI company, through external memory interface reading of data from the FIFO data buffer of DSP.

4. according to the said method of claim 1, wherein: DSP writes data through the EMIF mouth in the FIFO data buffering device, and the degree of depth of FIFO data buffering device is 512 among the FPGA, and width is 32; The length of long frame data is 372 bytes, and the length of short frame data is 360 bytes.

5. according to the said method of claim 1, wherein: the constant rate that FPGA sends coding back data is 128kbps.