CN101930356B - Method for group addressing and read-write controlling of register file for floating-point coprocessor - Google Patents
Method for group addressing and read-write controlling of register file for floating-point coprocessor Download PDFInfo
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Abstract
The invention discloses a method for group addressing and read write controlling of a register file for a floating-point coprocessor. The method comprises the steps of the group addressing of the register file and the read write controlling of the register file, wherein the group addressing of the register file means converting a one-dimensional linear address into a two-dimensional rank structure; the read write controlling of the register file means providing a set of read write control signals, address signals and data signals for each group of register; each group of address signals correspond to the top bit to the third bit of a register address to be accessed, namely rs [n: 2]; the data signals and the read write control signals are exclusive for each group; the read write control signals generate operation type signals indicating single, dual, quadruple precision operation according to instruction operation type coding; and a type selected by a register group is judged by applying the operation type signals.
Description
Technical field
The present invention relates to the implementation structure of grouping addressing, read/writing control method and a kind of circuit of flating point register file in a kind of 32 risc processors.
Background technology
Reduced instruction set computer (RISC) processor generally adopts the computation schema based on register, and its source operand is from register or several immediately, and the result who carries out generally also will write back in the register.Based on such design feature, for support multioperand time access, the register of risc processor must provide read port and a write port of at least two.In concrete processor design, two kinds of typical mentalities of designing are arranged: the 1) design of full customization: document " A Small; Fast and Low-PowerRegister File by Bit-Partitioning " (Proceedings of the 11th InternationalSymposium on High-Performance Computer Architecture (HPCA-112005)) and " among The Alpha 21264 Microprocessor (IEEE MICRO; Vol.19 (2)) this design is introduced; the full Custom Design take the Alpha series processors of former DEC as representative is by the customization register file; thus a plurality of read ports and write port are provided; this method is in the Superscalar RISC processor designs, for adapt to many instructions time access, register file even designed the read port more than eight; 2) based on the semi-custom designs of cell library: the multiport memory module that this design applying unit storehouse provides to realize that by structural design the port of demand guarantees, the two piece dual-ported memories of the LEON series processors (www.gaisler.com) of GaislerResearch company by using cell library to provide, write port shares, the register file structure that read port is separate to be realized " two read writes ".In these two kinds of mentalities of designing, full Custom Design has higher technical threshold, and along with the port of design increases, design complexity sharply rises, and design difficulty is large; And realized the simplicity of design in the mode of structure replication based on the semi-custom designs of cell library.
Be the address tissue of register outside port design, extensively adopt at present unified linear addressing pattern.Fig. 1 has provided the project organization synoptic diagram that the RAM piece [Fig. 1 (b)] of using a read port, a write port is realized unified linear addressable register file structure [Fig. 1 (a)], and writing and read respectively by to two block RAMs the time to provide " two the read one writes " port organization that needs.
In 32 risc processors, all register bit wides all are 32, like this for the method for taking above the data layout of 32 bit wides to preserve with a plurality of registers.For example, 32 single precision floating datum adopts a register holds; 64 double-precision floating points aligns with 2 integral multiple with the register holds of two continuation addresses, register address; 128 four accuracy floating-point numbers then adopt the register of 4 continuation addresses to preserve, and register address aligns with 4 integral multiple.For present register file structure, corresponding typical case be 32 risc processors when carrying out two or four accuracy floating-point computings, must spend two or four cycles just can obtain complete operand and send into execution unit; Simultaneously, result of calculations two or four precision need two or four cycles just can write back register.This computation schema that an operand is provided jointly by a plurality of registers, cause and repeatedly to read and write register file, in high-performance microprocessor design, thisly write back and the multiregister access cycle of coming have larger impact for the performance of processor for preparing operand and result.
How unifying the register access time of different operating number format, is high performance processor design, and the problem that especially must solve in the floating-point coprocessor design through retrieval pertinent literature and patent, still finds no the method that addresses this problem.
Summary of the invention
Operand preparation and operating result are deposited back the problem that register needs a plurality of clock period when the present invention is directed to floating-point coprocessor high precision Floating-point Computation, propose a kind of additionally not increasing in the situation of register quantity, can realize register addressing, read and write access control method and the circuit structure of the unified monocycle access of single, double or the different bit wide operands of four precision.
For reaching above purpose, the present invention takes following technical scheme to be achieved:
A kind of register file grouping addressing, read/writing control method for floating-point coprocessor comprise following two large steps:
(1) register file grouping addressing
Register file is divided into four groups, and namely each maximum register access number is 4, simultaneously, changes the addressing pattern of register, changes the linear pattern that addresses of originally unification the addressing of into packet-based " it " font, that is, and and for 2
N+1Individual flating point register, its address is the binary address of n+1 position, be divided into after four groups, adopt unified linear addressing in each group, be called group bias internal address, this group bias internal address is corresponding to raw address rs[n:0] rs[n:2] part, raw address rs[n:0] rs[1:0] part occurs as the group number of four groups of registers, like this linear address of an one dimension changed the row-column configuration for a bidimensional; For the access of single-precision number certificate then corresponding to the access to a register in the register group among RAM0, RAM1, RAM2 or the RAM3; The access of double precision datum is then corresponding to the access of same offset address in RAM0 and RAM1 or RAM2 and the RAM3 register grouping in pairs; The access of four accuracy datas is then corresponding to same offset address time access in four groupings;
(2) read-write of register file control
In the situation of step (1) grouping addressing, for each group register all provides cover read-write control signal, address signal and a data-signal, wherein the address signal of each group is corresponding to three of the most significant digits to the of wanting the access register address, be rs[n:2], data-signal, read-write control signal be every group exclusive, wherein, read-write control signal generates according to following step:
1) according to the decoding of command operating type, produces the action type signal that indication is single, double, four precision operate;
2) the application operating type signal is judged the type of register group selection, wherein during single precision by minimum two rs[1:0 that want the access register address] respective value determine register group gating and provide to read or write control signal; During double precision by the second rs[1 that wants the access register address] determine register group gating and provide to read or write control signal; All four register groups gating and provide and read or write control signal all during four precision;
For the floating-point coprocessor of, four precision single, double for supporting, it is maximum, and to process bit wide be 128, and its source operand and operation result all are spliced into 128 pattern before entering data routing, for single precision, and its low 96 benefits " 0 "; Low 64 benefits " 0 " then are 128 corresponding data during four precision during double precision, and according to such data structure, the generation step of the data-signal of each register group is as follows:
3) during data reading, reading the register group that enables all sends data, according to the action type indicator signal, during single precision, the data of register group output are spliced mutually with low 96 " 0 ", the data of register group output are spliced mutually with low 64 " 0 " during double precision, and the data of register group output directly obtain 128 operand during four precision;
4) data are write fashionable, carry out the distribution that writes of 128 bit data according to action type indicator signal and register group selection signal, during single precision, on high 32 data-signals of all delivering to four groups of registers of 128, cooperate the register group to write to enable with the group selection signal and finish rs[n:2 to the register group of selecting] the writing of address; With on high 64 data-signals of delivering to RAM0 and RAM1 or RAM2 and RAM3 register group in pairs according to the address align pattern of 128, cooperate the register group to write to enable with the group selection signal each data of 32 of height of 64 results to be write the rs[n:2 of two groups of registers of selection during double precision] in; During four precision, 128 results are divided into 4 32 bit data according to the address align pattern, and deliver to respectively on the data-signal of four registers, cooperate the register group to write and enable to realize rs[n:2 in 4 groups of register files with the group selection signal] write.
A kind of realize aforementioned for the register file grouping addressing of floating-point coprocessor, the register circuit structure of read/writing control method, comprise that one writes back data generation module, write address and control signal generation module, two block register RAM, reads address and control signal generation module and two operand generation modules for two;
Wherein the first block register is divided into RAM0～RAM3 register group, and the second block register is divided into RAM4～RAM7 register group, and the size of each register group is 1/4th of register file;
The input that writes back data generation module connects 128 and writes back the result, and output connects respectively the 32 bit data input of each register group; Write address is connected input and is connected the rd[n:0 that comprises that come by Instruction decoding with the control signal generation module] address signal, write control signal and action type select signal, and output connects respectively the control inputs of writing of each register group;
The RAM0 of described the first block register～RAM3 register group is by the first source operand of 128 of first operand generation module outputs; The control inputs of reading of RAM0～RAM3 register group connects the first output of reading address and control signal generation module, and first reads the address is connected input and connects rs1[n:0 with the control signal generation module] address signal, read control signal and action type select signal;
The RAM4 of described the second block register～RAM7 register group is by the second source operand of 128 of second operand generation module outputs; The control inputs of reading of RAM4～RAM7 register group connects the second output of reading address and control signal generation module, and second reads the address is connected input and connects rs2[n:0 with the control signal generation module] address signal, read control signal and action type select signal.
Compared with prior art, advantage of the present invention is:
1, monocycle access two, four precision operands can be realized, thereby two, six can be saved respectively because the clock period expense that data read and the result writes back;
2, can continue to use existing register port design structure, need not additionally carry out the Custom Design of register, not increase simultaneously extra register quantity;
So 3, compare before in the design owing to will read the multicycle or write and will provide data register to keep the front cycle to read or the project organization of data to be write back, monocycle of the present invention can be realized reading and writing back of single, double, four accuracy datas, so no longer need the register of corresponding temporal data;
4, except the control signal that provides for many group registers, line expense that data-signal comes, do not increase extra hardware spending;
5, adopt the mechanism of action type control group gating, can avoid the invalid action of register, thereby the income of low-power consumption is provided from structure.
Can the normalization risc architecture processor operations numerical digit wide access duration when inconsistent of the present invention, thereby the clock periodicity that the access of minimizing processor source operand and result write back, so that the operation of long bit wide operands is not subjected to the impact that operand is prepared and the result writes back, thereby promote the performance of processor
Description of drawings
The present invention is described in further detail below in conjunction with the drawings and the specific embodiments.
Fig. 1 is the register file structure of the unified linear addressing of employing of prior art.Wherein Fig. 1 (a) is register file structure; Fig. 1 (b) is register file RAM block structure.
Fig. 2 is register file grouping and the address addressing structure synoptic diagram among the present invention.
Fig. 3 accesses the flating point register circuit structure of duration for the different pieces of information unified in bit width that adopts the inventive method.
Fig. 4 is the physical circuit schematic diagram of two operand generation modules among Fig. 3.
Fig. 5 writes back the data generation module circuit theory diagrams among Fig. 3.
Embodiment
A kind of register file grouping addressing, read/writing control method for floating-point coprocessor comprise following two large steps:
(1) register file grouping addressing
During the high precision Floating-point Computation operand prepare and the result to deposit back the reason of register a plurality of clock period of needs be that the register bit wide is 32, read/write is a register at every turn, two and four registers and two, four precision need read/write respectively, such needs read/write repeatedly.In order to reduce the read-write cycle number, read and write when needing to realize to a plurality of register, original unified register file is divided into groups, each group uses the RAM piece of " one reads one a writes " port to realize, when each access, can realize access to a plurality of registers by corresponding read/writing control method like this, thereby realize the expansion of data bit width, according to list, two, the register address alignment strategy of four accuracy data forms, when read/write, provide the data reading of corresponding register by different groups or write, thereby realize the unified read-write of monocycle of different bit wides.
The present invention is based on this thought, because the operation of four accuracy datas is once to access the maximum bit wide that needs, so register file is divided into four groups, namely each maximum register access number is 4.Simultaneously, changing the addressing pattern of register, is the addressing of packet-based " it " font with the linear schema modification that addresses of originally unification, that is, and and for 2
N+1The flating point register of individual (n is natural number), its address is the binary address of n+1 position, be divided into after four groups, adopt unified linear addressing in each group, be called group bias internal address, this address is corresponding to raw address rs[n:0] rs[n:2] part, the rs[1:0 of raw address] part occurs as the group number of four groups of registers, like this linear address of an one dimension is changed the row-column configuration for a bidimensional, detailed structural representation is seen Fig. 2.Like this, for the access of single-precision number certificate then corresponding to the access for a register in the register group among RAM0, RAM1, RAM2 or the RAM3; The access of double precision datum is then corresponding to the access of same offset address in RAM0 and RAM1 or RAM2 and the in pairs register grouping of RAM3; The access of four accuracy datas is then corresponding to same offset address time access in four groupings.Based on such grouping addressing pattern, the access of unifying duration for different data format from the tissue of register file provides assurance.
(2) read-write of register file control
In the situation of step (1) grouping addressing, corresponding read and write access method is different from the read and write access method that adopts unified linear addressing.In the situation of original unified linear addressing, whole register file is used a cover control signal, after adopting grouping addressing, for each group register all provides cover read-write control signal, address signal and a data-signal, wherein the address signal of each group is corresponding to three of the most significant digits to the of wanting the access register address, be rs[n:2], data-signal and read-write control signal be every group exclusive.Read-write control signal generates according to following pattern:
1) according to the decoding of command operating type, produces the action type signal that indication is single, double, four precision operate;
2) the application operating type signal is judged the type of group selection, wherein during single precision by minimum two rs[1:0 that want the access register address] respective value determine register group gating and provide to read or write control signal, during double precision by the second rs[1 that wants the access register address] determine register group gating and provide to read or write control signal all register group gating and provide and read or write control signal all during four precision.
For the floating-point coprocessor of, four precision single, double for supporting, it is maximum, and to process bit wide be 128, so its source operand and operation result all are spliced into 128 pattern before entering data routing, and for single precision, its low 96 benefits " 0 "; Double precision is hanged down 64 benefits " 0 ", and four precision then are 128 corresponding data.According to such structure, the generate pattern of the data-signal of each register group is as follows:
1) at the data reading end, reading the register group that enables all sends data, according to the action type indicator signal, during single precision, the data of register group output are spliced mutually with low 96 " 0 ", the data of register group output are spliced mutually with low 64 " 0 " during double precision, and the data of register group output directly obtain 128 operand during four precision;
5) data are write fashionable, carry out the distribution that writes of 128 bit data according to action type indicator signal and register group selection signal, during single precision, on high 32 data-signals of all delivering to four groups of registers of 128, cooperate to write to enable to finish rs[n:2 to the register group of selecting with the group selection signal] the writing of address; With on high 64 data-signals of delivering to RAM0 and RAM1 or RAM2 and RAM3 group in pairs according to the address align pattern of 128, cooperate the register group to write to enable with the group selection signal each data of 32 of height of 64 results to be write the rs[n:2 of two groups of registers of selection during double precision] in; During four precision, 128 results are divided into 4 32 bit data and delivering to respectively on the data-signal of four registers according to the address align pattern, cooperate the register group to write and enable to realize rs[n:2 in 4 groups of register files with the group selection signal] write.
According to above-mentioned grouping addressing and read/writing control method, the unified monocycle to flating point register in the time of can realizing the operation of single, double, four accuracy floating-point data layouts accesses.
As shown in Figure 3, the present invention also provides a kind of concrete register circuit structure that realizes aforementioned register file grouping addressing for floating-point coprocessor, read/writing control method.Comprise that one writes back data generation module, write address and control signal generation module, two block register RAM, reads address and control signal generation module and two operand generation modules for two;
Wherein the first block register is divided into RAM0～RAM3 register group, and the second block register is divided into RAM4～RAM7 register group, and the size of each register group is 1/4th of register file;
The input that writes back data generation module connects 128 and writes back the result, and output connects respectively the 32 bit data input of each register group; Write address is connected input and is connected the rd[n:0 that comprises that come by Instruction decoding with the control signal generation module] address signal, write control signal and action type select signal, and output connects respectively the control inputs of writing of each register group;
The RAM0 of described the first block register～RAM3 register group is by the first source operand of 128 of first operand generation module outputs; The control inputs of reading of RAM0～RAM3 register group connects the first output of reading address and control signal generation module, and first reads the address is connected input and connects rs1[n:0 with the control signal generation module] address signal, read control signal and action type select signal;
The RAM4 of described the second block register～RAM7 register group is by the second source operand of 128 of second operand generation module outputs; The control inputs of reading of RAM4～RAM7 register group connects the second output of reading address and control signal generation module, and second reads the address is connected input and connects rs2[n:0 with the control signal generation module] address signal, read control signal and action type select signal.
Grouping addressing and access control that Fig. 3 adopts the RAM piece of " one reads one writes " port to realize, two block RAM pieces are originally substituted for the register group of register file 1/4th scales by four groups of sizes respectively.
Select in the action type of being come by the Instruction decoding structure under the control of signal, read address and control signal generation module with the source operand address rs[n:0 of n+1 position] be divided into two parts, one is the address rs[n:2 in each group RAM piece] and rs[1:0], rs[n:2 wherein] be used for the access to the group particular register, rs[1:0] for when single, double precision operand, carrying out group selection, all groups all will read during four precision, need not to carry out group selection.According to action type signal and group selection signal rs[1:0] determine only to send the register read write control signal to specific group, can avoid unnecessary saltus step like this.
The operand generation module forms spliced 128 bit data according to the group gating signal, the value of selecting concrete splicing to obtain according to action type is again exported as operand, select and the data splicing construction forms the generation of operand with such two-stage, circuit structure as shown in Figure 4, comprise one 4 the tunnel and select module, 2 the tunnel select module, 128 bit data concatenation module, 64 bit data concatenation module.Wherein, the input of 4 tunnel selection modules is respectively 32 outputs of RAM0, RAM1, RAM2 or RAM3, according to rs[1:0] select one of them value of 32 to export data concatenation module 1 to.Data concatenation module 1 output 128 bit data, its high-order 32 bit data for input, low 96 benefits " 0 ";
64 bit data concatenation module are spliced into two 64 outputs with RAM0 and RAM1, RAM2 and the RAM3 of input respectively, and 2 the tunnel select modules according to rs[1] select one of them 64 place value to export data concatenation module 2 to.Data concatenation module 2 outputs 128 bit data, its high-order 64 bit data for input, low 64 benefits " 0 ";
128 bit data concatenation module are spliced into 128 with the data of RAM0, RAM1, RAM2 and RAM3 output, export 3 the tunnel to and select module.3 the tunnel select modules to select 128 bit data, data that the output data are spliced the output of 1 module to splice in 128 bit data of 128 bit data of 2 modules output or the output of 128 bit data concatenation module one as output according to action type, wherein select the data of splicing 1 module output as output during the single precision operation; Select the data of splicing 2 modules as output during double precision; Select the output of 128 bit data concatenation module as output during four precision.
Write data generation module according to 128 results are intercepted, replicate run forms that operation is single, double, write back data during four precision to the grouping RAM piece, be strobed into data on the grouping RAM data writing port according to action type, determine writing of particular group by write control signal.Its circuit structure as shown in Figure 5, for as writing back result's 128 bit data, four times are copied four times of high 32 bit data of 128 bit data when copying and form 128 data writings; The twice replication module is with high 64 bit data of 128 bit data, and twice copies and forms 128 data writings; 3 the tunnel select two 128 bit data that modules will above-mentioned two modules output to write back three 128 bit data of result data with 128, export according to action type selection one.128 bit data of output are split as on the data writing port that 4 32 bit data are connected respectively to RAM0, RAM2, RAM3, RAM4.It should be noted that according to the large end that defines in the processor architecture or the difference of little end structure, double precision and four precision result may need the inverted order of register address when writing back.
The present invention has been applied in the RSIC processor of a compatible SPARC V8 structure, by using the flating point register file that designs among the present invention, can finish operations single, double, four accuracy data different pieces of information bit wides by a register access, can shorten respectively 2 and 6 register access cycles in two, four precision when operating, in the situation that does not affect processor frequencies, improve the execution efficient of instruction, thereby improved the performance of whole processor.Because the RAM block size of this grouping is 1/4th of an original block RAM piece, made things convenient for the dirigibility of placement-and-routing when physical Design, the line hardware spending that increases owing to many group control signals and data-signal, placement-and-routing's dirigibility that can be brought by little RAM piece to a certain extent remedies, with regard to the specific implementation result, chip area does not improve.
Claims (1)
1. register file grouping addressing, read/writing control method that is used for floating-point coprocessor, wherein, the register bit wide in the register file is 32, it is characterized in that, comprises following two large steps:
(1) register file grouping addressing
Register file is divided into four groups, and namely each maximum register access number is 4, simultaneously, changes the addressing pattern of register, changes the linear pattern that addresses of originally unification the addressing of into packet-based " it " font, that is, and and for 2
N+1Individual flating point register, its address is the binary address of n+1 position, be divided into after four groups, adopt unified linear addressing in each group, be called group bias internal address, this group bias internal address is corresponding to raw address rs[n:0] rs[n:2] part, raw address rs[n:0] rs[1:0] part occurs as the group number of four groups of registers, like this linear address of an one dimension changed the row-column configuration for a bidimensional; For the access of single-precision number certificate then corresponding to the access to a register in the register group among RAM0, RAM1, RAM2 or the RAM3; The access of double precision datum is then corresponding to RAM0 and RAM1, or the access of same offset address in RAM2 and the RAM3 register grouping in pairs; The access of four accuracy datas is then corresponding to same offset address time access in four groupings;
(2) read-write of register file control
In the situation of step (1) grouping addressing, for each group register all provides cover read-write control signal, address signal and a data-signal, wherein the address signal of each group is corresponding to three of the most significant digits to the of wanting the access register address, be rs[n:2], data-signal, read-write control signal be every group exclusive, wherein, read-write control signal generates according to following step:
1) according to the decoding of command operating type, produces the action type signal that indication is single, double, four precision operate;
2) the application operating type signal is judged the type of register group selection, wherein during single precision by minimum two rs[1:0 that want the access register address] respective value determine register group gating and provide to read or write control signal; During double precision by the second rs[1 that wants the access register address] determine register group gating and provide to read or write control signal; All four register groups gating and provide and read or write control signal all during four precision;
For the floating-point coprocessor of, four precision single, double for supporting, it is maximum, and to process bit wide be 128, and its source operand and operation result all are spliced into 128 pattern before entering data routing, for single precision, and its low 96 benefits " 0 "; Low 64 benefits " 0 " then are 128 corresponding data during four precision during double precision, and according to such data structure, the generation step of the data-signal of each register group is as follows:
1) during data reading, reading the register group that enables all sends data, according to the action type indicator signal, during single precision, the data of register group output are spliced mutually with low 96 " 0 ", the data of register group output are spliced mutually with low 64 " 0 " during double precision, and the data of register group output directly obtain 128 operand during four precision;
2) data are write fashionable, carry out the distribution that writes of 128 bit data according to action type indicator signal and register group selection signal, during single precision, on high 32 data-signals of all delivering to four groups of registers of 128, cooperate the register group to write to enable with the group selection signal and finish rs[n:2 to the register group of selecting] the writing of address; During double precision 128 high 64 are delivered to RAM0 and RAM1 according to the address align pattern, or on the data-signal of RAM2 and RAM3 register group in pairs, cooperation register group is write the rs[n:2 that enables with the group selection signal each data of 32 of height of 64 results to be write two register groups of selection] in; During four precision, 128 results are divided into 4 32 bit data according to the address align pattern, and deliver to respectively on the data-signal of four registers, cooperate the register group to write and enable to realize rs[n:2 in 4 groups of register files with the group selection signal] write.
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| US20120254589A1 (en) * | 2011-04-01 | 2012-10-04 | Jesus Corbal San Adrian | System, apparatus, and method for aligning registers |
| CN102629190A (en) * | 2012-02-29 | 2012-08-08 | 华为技术有限公司 | Read-write method and device of register |
| CN103984524B (en) * | 2014-05-15 | 2016-07-06 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of three port floating-point register towards risc processor |
| CN110187919B (en) * | 2019-05-27 | 2021-07-20 | 眸芯科技（上海）有限公司 | Device, method and system for configuring register |
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| CN101539850A (en) * | 2008-03-21 | 2009-09-23 | 富士通株式会社 | Single-precision floating-point data storing method and processor |
| US20100095099A1 (en) * | 2008-10-14 | 2010-04-15 | International Business Machines Corporation | System and method for storing numbers in first and second formats in a register file |
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