CN101930221A - Data acquisition system based on BIST (Built-In Self-Test) and method for realizing acquisition and self-tests - Google Patents
Data acquisition system based on BIST (Built-In Self-Test) and method for realizing acquisition and self-tests Download PDFInfo
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Abstract
The invention relates to a data acquisition system based on a BIST (Built-In Self-Test) and a method for realizing acquisition and self-tests, belonging to the field of data acquisition technology and solving the problems of poor testability and reliability of the traditional data acquisition unit. The data acquisition system mainly comprises an FPGA (Field Programmable Gate Array) control module, a DSP (Digital Signal Processor) main controller, a mixed boundary scanning chip, a boundary scanning control chip and a test signal generator. The method mainly comprises the following steps that: the FPGA control module completes the data acquisition function, the DSP main controller realizes the switching control of the main controller between data acquisition and self-tests, the test signal generator realizes the generation of test signals, and the boundary scanning control chip realizes tests on FPGA. The invention provides a basis for increasing the testability development of the data acquisition system.
Description
Technical field
The present invention relates to the data acquisition technology field, be specifically related to a kind of based on BIST data acquisition system (DAS) and realize the method for data acquisition, self-test.
Background technology
The product that data acquisition unit is used as the typical case, has very broad application background, its measurability, reliability and maintenanceability are problems anxious to be solved always, existing data acquisition unit measurability and reliability are low, the quality that this has greatly influenced product itself has also reduced the whole life cycle of product, has increased the overall life cycle cost expense of product simultaneously.
Summary of the invention
In order to solve the problem that existing data acquisition unit measurability is low, reliability is low, the invention provides that a kind of data acquisition system (DAS) and realizing based on BIST is gathered, the method for self-test.
Data acquisition system (DAS) based on BIST of the present invention, it comprises zero cross detection circuit, the advance signal amplifying circuit, wave filter, the A/D modular converter, first phaselocked loop, the FPGA control module, DSP Peripheral storage module and DSP master controller, it also comprises the first analog channel switch, compound boundary scanning chip, the second analog channel switch, the 3rd analog channel switch, the D/A modular converter, the boundary scan control chip, measuring signal generator, computing machine, liquid crystal display and keyboard, inputed to the signal input part of advance signal amplifying circuit and the signal input part of zero cross detection circuit by acquired signal through the first analog channel switch, described advance signal amplifying circuit output signal inputs to the signal input part of wave filter through compound boundary scanning chip, described wave filter inputs to first signal input part of A/D modular converter through the 3rd analog channel switch, the signal output part of described A/D modular converter connects first signal input part of FPGA control module, the secondary signal input end of described FPGA control module connects the signal output part of first phaselocked loop, the 3rd signal input part of described FPGA control module connects the signal output part of DSP master controller by the SPI/UART bus, first signal output part of described FPGA control module connects the secondary signal input end of A/D modular converter, the secondary signal output terminal of described FPGA control module connects the 3rd signal input part of A/D modular converter, the 3rd signal output part of described FPGA control module connects first signal input part of DSP master controller, first signal output part of described DSP master controller connects the signal input part of computing machine, the secondary signal output terminal of described DSP master controller connects the signal input part of liquid crystal display, the 3rd signal output part of described DSP master controller connects the signal input part of DSP Peripheral storage module, the secondary signal input end of described DSP master controller connects the data output end of keyboard, the signal input part of the 4th signal output part fillet scanning control chip of described DSP master controller, the 5th signal output part of described DSP master controller connects the signal input part of D/A modular converter, the 6th signal output part of described DSP master controller connects the signal input part of measuring signal generator, the signal output part of D/A modular converter all with a controlled end of the first analog channel switch, a controlled end of the second analog channel switch and a controlled end of the 3rd analog channel switch are connected, the analog channel switching signal control end of FPGA control module all with another controlled end of the 3rd analog channel switch, another controlled end of the second analog channel switch is connected with another controlled end of the first analog channel switch, the signal output part of measuring signal generator is connected to the signal input part that compound boundary scans chip by the hybrid circuit test bus, and the signal output part of zero cross detection circuit is connected to the signal input part of first phaselocked loop through the second analog channel switch.
Data acquisition system (DAS) realization based on BIST of the present invention is gathered, the method for self-test, and its detailed process is:
By the keyboard input of control commands, the DSP master controller receives described control command, if described control command is a data acquisition command, then the DSP master controller is assigned data acquisition command to the FPGA control module, send the analog channel switch closure command simultaneously, and by each analog channel switch closure of FPGA module controls, and the FPGA control module is sent the sequential control order to the A/D modular converter, control described A/D modular converter to waited sampling clock of cycle sampling by acquired signal, amplified by the advance signal amplifying circuit by acquired signal and filter filtering after transferred to digital signal by the A/D modular converter, and be admitted to the FPGA control module and be stored in its internal RAM, described FPGA control module is according to the control command of DSP master controller, the image data that is stored in its internal RAM is sent to the DSP master controller, described DSP master controller is sent to DSP Peripheral storage module with the data of sending here and stores, while DSP master controller also is sent to liquid crystal display with the data of sending here and shows, and is sent to computing machine and handles; If the control command that the DSP master controller receives is the boundary scan testing order, then the DSP master controller sends boundary scan command to the boundary scan control chip, described boundary scan control chip carries out boundary scan testing to the FPGA control module, and shows test results on liquid crystal display; If the control command that the DSP master controller receives is the circuit test order, then described DSP master controller is assigned described circuit test order to the FPGA control module, described circuit test order comprises the modular converter to A/D, wave filter, the advance signal amplifying circuit, the test command that first phaselocked loop and zero cross detection circuit are tested, described FPGA control module is to the 3rd analog channel switch, the second analog channel switch and the first analog channel switch send the order of analog channel Switch Control, switch each analog channel switch, the DSP master controller sends the test and excitation signal to the D/A modular converter simultaneously, described test and excitation signal passes through the 3rd analog channel switch after the D/A modular converter is converted to analogue stimulus signal, the A/D modular converter, FPGA control module and DSP master controller show test results on liquid crystal display; If the control command that the DSP master controller receives is compound boundary sweep test order, then described DSP master controller sends test command to measuring signal generator, described measuring signal generator sends test signal, described test signal index comprises electric current and voltage, described test signal scans chip, wave filter, the 3rd analog channel switch, A/D modular converter, FPGA control module and DSP master controller by compound boundary, shows test results on liquid crystal display.
Beneficial effect of the present invention is: the invention provides and a kind ofly can carry out data acquisition, self-test
Data acquisition system (DAS) and realize the method for data acquisition, self-test; The present invention compares with the available data collector, has increased boundary scan control chip and measuring signal generator and each analog channel switch, is beneficial to measurability, has effectively improved the reliability of data acquisition system (DAS) simultaneously; DSP master controller of the present invention has realized that data acquisition system (DAS) carries out the management of data acquisition and self-test.
Description of drawings
Fig. 1 is the data acquisition system (DAS) synoptic diagram based on BIST of the present invention, and Fig. 2 is the structural representation of FPGA control module 11 of the present invention.
Embodiment
Embodiment one: specify present embodiment according to Figure of description 1, the described data acquisition system (DAS) of present embodiment based on BIST, it comprises zero cross detection circuit 2, advance signal amplifying circuit 3, wave filter 6, A/D modular converter 9, first phaselocked loop 10, FPGA control module 11, DSP Peripheral storage module 13 and DSP master controller 14, it is characterized in that it also comprises the first analog channel switch 1, compound boundary scanning chip 4, the second analog channel switch 5, the 3rd analog channel switch 7, D/A modular converter 8, boundary scan control chip 12, measuring signal generator 15, computing machine 16, liquid crystal display 17 and keyboard 18
Inputed to the signal input part of advance signal amplifying circuit 3 and the signal input part of zero cross detection circuit 2 by acquired signal through the first analog channel switch 1, described advance signal amplifying circuit 3 output signals input to the signal input part of wave filter 6 through compound boundary scanning chip 4, described wave filter 6 inputs to first signal input part of A/D modular converter 9 through the 3rd analog channel switch 7, the signal output part of described A/D modular converter 9 connects first signal input part of FPGA control module 11, the secondary signal input end of described FPGA control module 11 connects the signal output part of first phaselocked loop 10, the 3rd signal input part of described FPGA control module 11 connects the signal output part of DSP master controller 14 by the SPI/UART bus, first signal output part of described FPGA control module 11 connects the secondary signal input end of A/D modular converter 9, the secondary signal output terminal of described FPGA control module 11 connects the 3rd signal input part of A/D modular converter 9, the 3rd signal output part of described FPGA control module 11 connects first signal input part of DSP master controller 14, first signal output part of described DSP master controller 14 connects the signal input part of computing machine 16, the secondary signal output terminal of described DSP master controller 14 connects the signal input part of liquid crystal display 17, the 3rd signal output part of described DSP master controller 14 connects the signal input part of DSP Peripheral storage module 13, the secondary signal input end of described DSP master controller 14 connects the data output end of keyboard 18, the signal input part of the 4th signal output part fillet scanning control chip 12 of described DSP master controller 14, the 5th signal output part of described DSP master controller 14 connects the signal input part of D/A modular converter 8, the 6th signal output part of described DSP master controller 14 connects the signal input part of measuring signal generator 15, the signal output part of D/A modular converter 8 all with a controlled end of the first analog channel switch 1, a controlled end of the second analog channel switch 5 and a controlled end of the 3rd analog channel switch 7 are connected, the analog channel switching signal control end of FPGA control module 11 all with another controlled end of the 3rd analog channel switch 7, another controlled end of the second analog channel switch 5 is connected with another controlled end of the first analog channel switch 1, the signal output part of measuring signal generator 15 is connected to the signal input part that compound boundary scans chip 4 by the hybrid circuit test bus, and the signal output part of zero cross detection circuit 2 is connected to the signal input part of first phaselocked loop 10 through the second analog channel switch 5.
Embodiment two: specify present embodiment according to Figure of description 2, present embodiment is further specifying embodiment one, FPGA control module 11 in the embodiment one comprises ram in slice module 11-1, RAM read/write address maker 11-2, top layer control state machine 11-3, UART receiver module 11-4, UART sending module 11-5, the clock frequency division module 11-6 and the second phaselocked loop 11-7, the signal output part of the described second phaselocked loop 11-7 connects the signal input part of clock frequency division module 11-6, another signal output part of the described second phaselocked loop 11-7 connects the signal input part of RAM read/write address maker 11-2, another signal input part of described RAM read/write address maker 11-2 connects first signal output part of top layer control state machine 11-3, the signal output part of described RAM read/write address maker 11-2 connects the signal input part of ram in slice module 11-1, the signal output part of described ram in slice module 11-1 connects first signal input part of UART sending module 11-5, the secondary signal input end of described UART sending module 11-5 connects the secondary signal output terminal of top layer control state machine 11-3, the 3rd signal input part of described UART sending module 11-5 connects first signal output part of clock frequency division module 11-6, the secondary signal output terminal of described clock frequency division module 11-6 connects the signal input part of top layer control state machine 11-3, the 3rd signal output part of described clock frequency division module 11-6 connects the signal input part of UART receiver module 11-4, another signal input part of described UART receiver module 11-4 connects the 3rd signal output part of top layer control state machine 11-3, clock frequency division module 11-6 is used for doubled clock is carried out frequency division;
The second phaselocked loop 11-7 is used for clock signal is carried out frequency multiplication; Ram in slice module 11-1 is used to store data; RAM read/write address maker 11-2 is used for variation according to read-write state and generates RAM and read address and write address accordingly; UART receiver module 11-4 is used to receive data, realizes that simultaneously UART receiver module clock and each receive the synchronous of character; UART sending module 11-5 is used to send data, realizes that simultaneously UART sending module clock and each send the synchronous of character; Top layer control state machine 11-3 is used for entering data acquisition and RAM write data state receiving external command when being data acquisition command, receiving external command when sending data command, enters data and sends and RAM read data state.
Embodiment three: present embodiment is to realize according to the data acquisition system (DAS) based on BIST described in embodiment one or two, the described data acquisition system (DAS) realization based on BIST of present embodiment is gathered, the method for self-test, and its detailed process is:
By keyboard 18 input of control commands, DSP master controller 14 receives described control command,
If described control command is a data acquisition command, then DSP master controller 14 is assigned data acquisition command to FPGA control module 11, send the analog channel switch closure command simultaneously, and by FPGA module 11 each analog channel switch closure of control, and FPGA control module 11 is sent the sequential control order to A/D modular converter 9, control 9 pairs of sampling clocks that waited the cycle sampling by acquired signal of described A/D modular converter, amplified by advance signal amplifying circuit 3 by acquired signal and wave filter 6 filtering after transferred to digital signal by A/D modular converter 9, and be admitted to FPGA control module 11 and be stored in its internal RAM, described FPGA control module 11 is according to the control command of DSP master controller 14, the image data that is stored in its internal RAM is sent to DSP master controller 14, described DSP master controller 14 is sent to DSP Peripheral storage module 13 with the data of sending here and stores, while DSP master controller 14 also is sent to liquid crystal display 17 with the data of sending here and shows, and is sent to computing machine 16 and handles;
If the control command that DSP master controller 14 receives is the boundary scan testing order, then DSP master controller 14 sends boundary scan command to boundary scan control chip 12,12 pairs of FPGA control modules of described boundary scan control chip 11 are carried out boundary scan testing, and show test results on liquid crystal display 17; If the control command that DSP master controller 14 receives is the circuit test order, then described DSP master controller 14 is assigned described circuit test order to FPGA control module 11, described circuit test order comprises A/D modular converter 9, wave filter 6, advance signal amplifying circuit 3, the test command that first phaselocked loop 10 and zero cross detection circuit 2 are tested, described FPGA control module 11 is to the 3rd analog channel switch 7, the second analog channel switch 5 and the first analog channel switch 1 send the order of analog channel Switch Control, switch each analog channel switch, DSP master controller 14 sends the test and excitation signal to D/A modular converter 8 simultaneously, described test and excitation signal passes through the 3rd analog channel switch 7 after D/A modular converter 8 is converted to analogue stimulus signal, A/D modular converter 9, FPGA control module 11 and DSP master controller 14 show test results on liquid crystal display 17; If the control command that DSP master controller 14 receives is compound boundary sweep test order, then described DSP master controller 14 sends test command to measuring signal generator 15, described measuring signal generator 15 sends test signal, described test signal index comprises electric current and voltage, described test signal shows test results on liquid crystal display 17 by compound boundary scanning chip 4, wave filter 6, the 3rd analog channel switch 7, A/D modular converter 9, FPGA control module 11 and DSP master controller 14.
Embodiment four: present embodiment is further specifying embodiment three, FPGA control module 11 is sent the sequential control order to A/D modular converter 9 in the embodiment three, controls 9 pairs of described A/D modular converters and is waited the detailed process of the sampling clock of cycle sampling to be by acquired signal:
Obtained by the clock frequency of acquired signal to zero passage testing circuit 2 backs through the first analog channel switch 1 by acquired signal, describedly entered first phaselocked loop 10 by the clock frequency of acquired signal through the second analog channel switch 5 and carry out frequency multiplication, be admitted to the sampling clock of A/D modular converter 9 by the clock frequency of acquired signal by FPGA control module 11 after the described frequency multiplication, realize that 9 pairs of described A/D modular converters are waited the cycle sampling by acquired signal.
In the present embodiment, the different test points that order relates to according to circuit test and each channel switch present position, according to certain testing sequence, parts in the system are tested:
At first, DSP master controller 14 is accepted the keyboard input command A/D modular converter 9 is tested, described DSP master controller 14 order FPGA control modules 11 controls this moment the 3rd analog channel switch 7 switches to the input end of analog signal of D/A modular converter 8, and the signal that cuts off wave filter 6 is imported, the first analog channel switch 1 and the second analog channel switch 5 all switch to the no signal input state, the test and excitation signal is loaded into the input end of A/D modular converter 9 through the 3rd analog channel switch 7, through 11 storages of FPGA control module and processing, be sent to DSP master controller 14, and on liquid crystal display 17, show test results;
Secondly, when the test result of A/D modular converter 9 is non-fault, wave filter 6 is tested, FPGA control module 11 controls this moment the 3rd analog channel switch 7 switches to the input end of wave filter 6, and the simulating signal of cutting off D/A modular converter 8 is imported, the first analog channel switch 1 and the second analog channel switch 5 all switch to the no signal input state, the test and excitation signal is carried in the input end of wave filter 6 through compound boundary scanning chip 4, and through the 3rd analog channel switch 7, A/D modular converter 9, FPGA control module 11 and DSP master controller 14 show test results on liquid crystal display 17;
Once more, when the test result of wave filter 6 is non-fault, advance signal amplifying circuit 3 is tested, FPGA control module 11 controls this moment the 3rd analog channel switch 7 switches to the input end of wave filter 6, and the simulating signal of cutting off D/A modular converter 8 is imported, the first analog channel switch 1 switches to the input end of analog signal of D/A modular converter 8, allow the input of test and excitation signal, cut off simultaneously by the input channel of acquired signal, the second analog channel switch 5 switches to the no signal input state, the test and excitation signal is carried in the input end of advance signal amplifying circuit 3 through the first analog channel switch 1, and through compound boundary scanning chip 4, wave filter 6, the 3rd analog channel switch 7, A/D modular converter 9, FPGA control module 11 and DSP master controller 14 show test results on liquid crystal display 17.
Then, first phaselocked loop 10 is tested, this moment, the second analog channel switch 5 switched to the input end of analog signal of D/A modular converter 8, allow the input of test and excitation signal, cut off the signal input of zero cross detection circuit 2 simultaneously, the first analog channel switch 1 and the 3rd analog channel switch 7 all switch to the no signal input state, and the test and excitation signal shows test results on liquid crystal display 17 through the second analog channel switch 5, first phaselocked loop 10, FPGA control module 11 and DSP master controller 14.
At last, when the test result of first phaselocked loop 10 is non-fault, zero cross detection circuit 2 is tested, FPGA control module 11 controls this moment the 3rd analog channel switch 7 switches to the no signal input state, and control the input end of analog signal that the first analog channel switch 1 switches to D/A modular converter 8, allow the input of test and excitation signal, described test and excitation signal is carried in the input end of zero cross detection circuit 2 through the first analog channel switch 1, the second analog channel switch 5 switches to the output terminal of zero cross detection circuit 2 simultaneously, and through first phaselocked loop 10, FPGA control module 11 and DSP master controller 14 show test results on liquid crystal display 17.
In the present embodiment, be periodic signal by acquired signal, amplitude is 0-5V, and frequency is 0-10MHz, also can adopt fixed sampling frequency, and described sample frequency can reach 200MHz.
In the present embodiment, the model of A/D modular converter 9 is ADS805U.
The model of each analog channel switch is the 74hc4051 of TI company in the present embodiment.
In the present embodiment, DSP Peripheral storage module 13 adopts the IP kernel in the Xilinx ISE of the company software, has saved loaded down with trivial details VHDL programming, and this IP kernel is that Performance And Reliability is all than higher through the program segment of strict checking; Ram in slice module 11-1 is a dual port RAM, and the read-write process is separate.Have two to overlap independently clock, independently address and enable port, the width of inputoutput data also can be set flexibly.
In the present embodiment, the model of boundary scan control chip 12 is LVT8980, and the model of compound boundary scanning chip 4 is STA400, and DSP master controller 14 adopts TI(Texas Instruments) 32 fixed DSP TMS320F2812 of company.
In the present embodiment, the UART interface is adopted in information transmission between DSP master controller 14 and the FPGA control module 11,8 bit data structures, baud rate is 115200bps, the concrete operations sign indicating number is as shown in table 1, FPGA control module 11 provides fixed cycle sampling and two kinds of patterns such as sampling such as the cycle of grade, and DSP master controller 14 passes through output waveform, the fault detect of each module and the break-make of each analog channel switch of test macro of instruction control FPGA control module 11, finishes the control co-ordination of overall system.
The communication protocol of table 1 DSP master controller 14 and FPGA control module 11
| Order code | Operation |
| 01H | In image data is deposited in the sheet among the RAM module 11-1 |
| 02H? | Send image data to |
| 03H | Output 1KHz square wave |
| 04H? | Output 10KHz square wave |
| 05H | Output 100KHz square wave |
| 06H | Cancelling signal (square wave or high level) output |
| 0DH | Output high level ' 1 ' |
| 07H | In the FPGA control module 11 during image data with the disconnection of extraneous A/D modular converter 9 data lines |
| 08H? | Extraneous A/D modular converter 9 data lines link to each other with ram in slice module 11-1 data line, normal image data |
| 09H | Test whether first |
| 0AH | Test whether first |
| 0BH | The sampling clock of A/D modular converter 9 meets 5MHz |
| 0CH | The sampling clock of A/D modular converter 9 is received on the frequency multiplication output clock of first |
| FXH | Control (10--P53,14--P36,1-P1 pin) thread switching control that connects |
| EXH | Control (16--P2,17--P13,18--P11 pin) thread switching control that connects |
| DXH | Control (19--P8,20--P6,21--P4 pin) thread switching control that connects |
Claims (4)
1. based on the data acquisition system (DAS) of BIST, it comprises zero cross detection circuit (2), advance signal amplifying circuit (3), wave filter (6), A/D modular converter (9), first phaselocked loop (10), FPGA control module (11), DSP Peripheral storage module (13) and DSP master controller (14), it is characterized in that it also comprises the first analog channel switch (1), compound boundary scanning chip (4), the second analog channel switch (5), the 3rd analog channel switch (7), D/A modular converter (8), boundary scan control chip (12), measuring signal generator (15), computing machine (16), liquid crystal display (17) and keyboard (18)
Inputed to the signal input part of advance signal amplifying circuit (3) and the signal input part of zero cross detection circuit (2) by acquired signal through the first analog channel switch (1), described advance signal amplifying circuit (3) output signal scans the signal input part that chip (4) inputs to wave filter (6) through compound boundary, described wave filter (6) inputs to first signal input part of A/D modular converter (9) through the 3rd analog channel switch (7), the signal output part of described A/D modular converter (9) connects first signal input part of FPGA control module (11), the secondary signal input end of described FPGA control module (11) connects the signal output part of first phaselocked loop (10), the 3rd signal input part of described FPGA control module (11) connects the signal output part of DSP master controller (14) by the SPI/UART bus, first signal output part of described FPGA control module (11) connects the secondary signal input end of A/D modular converter (9), the secondary signal output terminal of described FPGA control module (11) connects the 3rd signal input part of A/D modular converter (9), the 3rd signal output part of described FPGA control module (11) connects first signal input part of DSP master controller (14), first signal output part of described DSP master controller (14) connects the signal input part of computing machine (16), the secondary signal output terminal of described DSP master controller (14) connects the signal input part of liquid crystal display (17), the 3rd signal output part of described DSP master controller (14) connects the signal input part of DSP Peripheral storage module (13), the secondary signal input end of described DSP master controller (14) connects the data output end of keyboard (18), the signal input part of the 4th signal output part fillet scanning control chip (12) of described DSP master controller (14), the 5th signal output part of described DSP master controller (14) connects the signal input part of D/A modular converter (8), the 6th signal output part of described DSP master controller (14) connects the signal input part of measuring signal generator (15), the signal output part of D/A modular converter (8) all with a controlled end of the first analog channel switch (1), a controlled end of the second analog channel switch (5) and a controlled end of the 3rd analog channel switch (7) are connected, the analog channel switching signal control end of FPGA control module (11) all with another controlled end of the 3rd analog channel switch (7), another controlled end of the second analog channel switch (5) is connected with another controlled end of the first analog channel switch (1), the signal output part of measuring signal generator (15) is connected to the signal input part that compound boundary scans chip (4) by the hybrid circuit test bus, and the signal output part of zero cross detection circuit (2) is connected to the signal input part of first phaselocked loop (10) through the second analog channel switch (5).
2. the data acquisition system (DAS) based on BIST according to claim 1, it is characterized in that FPGA control module (11) comprises ram in slice module (11-1), RAM read/write address maker (11-2), top layer control state machine (11-3), UART receiver module (11-4), UART sending module (11-5), clock frequency division module (11-6) and second phaselocked loop (11-7), a signal output part of described second phaselocked loop (11-7) connects the signal input part of clock frequency division module (11-6), another signal output part of described second phaselocked loop (11-7) connects a signal input part of RAM read/write address maker (11-2), another signal input part of described RAM read/write address maker (11-2) connects first signal output part of top layer control state machine (11-3), the signal output part of described RAM read/write address maker (11-2) connects the signal input part of ram in slice module (11-1), the signal output part of described ram in slice module (11-1) connects first signal input part of UART sending module (11-5), the secondary signal input end of described UART sending module (11-5) connects the secondary signal output terminal of top layer control state machine (11-3), the 3rd signal input part of described UART sending module (11-5) connects first signal output part of clock frequency division module (11-6), the secondary signal output terminal of described clock frequency division module (11-6) connects the signal input part of top layer control state machine (11-3), the 3rd signal output part of described clock frequency division module (11-6) connects a signal input part of UART receiver module (11-4), another signal input part of described UART receiver module (11-4) connects the 3rd signal output part of top layer control state machine (11-3), clock frequency division module (11-6) is used for doubled clock is carried out frequency division; Second phaselocked loop (11-7) is used for clock signal is carried out frequency multiplication; Ram in slice module (11-1) is used to store data; RAM read/write address maker (11-2) is used for variation according to read-write state and generates RAM and read address and write address accordingly; UART receiver module (11-4) is used to receive data, realizes that simultaneously UART receiver module clock and each receive the synchronous of character; UART sending module (11-5) is used to send data, realizes that simultaneously UART sending module clock and each send the synchronous of character; Top layer control state machine (11-3) is used for entering data acquisition and RAM write data state receiving external command when being data acquisition command, receiving external command when sending data command, enters data and sends and RAM read data state.
3. the data acquisition system (DAS) based on BIST of the data acquisition system (DAS) based on BIST according to claim 1 realizes gathering, the method for self-test
,The detailed process that it is characterized in that it is:
By keyboard (18) input of control commands, DSP master controller (14) receives described control command,
If described control command is a data acquisition command, then DSP master controller (14) is assigned data acquisition command to FPGA control module (11), and control each analog channel switch closure by FPGA module (11), and FPGA control module (11) is sent the sequential control order to A/D modular converter (9), control described A/D modular converter (9) to waited cycle sampling by acquired signal, amplified by advance signal amplifying circuit (3) by acquired signal and wave filter (6) filtering after transferred to digital signal by A/D modular converter (9), and be admitted to FPGA control module (11) and be stored in its internal RAM, described FPGA control module (11) is according to the control command of DSP master controller (14), the image data that is stored in its internal RAM is sent to DSP master controller (14), described DSP master controller (14) is sent to DSP Peripheral storage module (13) with the data of sending here and stores, while DSP master controller (14) also is sent to the data of sending here liquid crystal display (17) and shows, and is sent to computing machine (16) and handles;
If the control command that DSP master controller (14) receives is the boundary scan testing order, then DSP master controller (14) sends boundary scan command to boundary scan control chip (12), described boundary scan control chip (12) carries out boundary scan testing to FPGA control module (11), and shows test results on liquid crystal display (17); If the control command that DSP master controller (14) receives is the circuit test order, then described DSP master controller (14) is assigned described circuit test order to FPGA control module (11), described circuit test order comprises A/D modular converter (9), wave filter (6), advance signal amplifying circuit (3), the test command that first phaselocked loop (10) and zero cross detection circuit (2) are tested, described FPGA control module (11) is to the 3rd analog channel switch (7), the second analog channel switch (5) and the first analog channel switch (1) send the order of analog channel Switch Control, switch each analog channel switch, DSP master controller (14) sends the test and excitation signal to D/A modular converter (8) simultaneously, the test index of described test and excitation signal comprises the linearity, switching rate and noise, described test and excitation signal passes through the 3rd analog channel switch (7) after D/A modular converter (8) is converted to analogue stimulus signal, A/D modular converter (9), FPGA control module (11) and DSP master controller (14) show test results on liquid crystal display (17); If the control command that DSP master controller (14) receives is compound boundary sweep test order, then described DSP master controller (14) sends test command to measuring signal generator (15), described measuring signal generator (15) sends test signal, described test signal index comprises electric current and voltage, described test signal scans chip (4), wave filter (6), the 3rd analog channel switch (7), A/D modular converter (9), FPGA control module (11) and DSP master controller (14) by compound boundary, shows test results on liquid crystal display (17).
4. the method that realizes collection, self-test based on the data acquisition system (DAS) of BIST according to claim 3, it is characterized in that FPGA control module (11) sends the sequential control order to A/D modular converter (9), control described A/D modular converter (9) and be the detailed process that is waited the cycle sampling by acquired signal:
Obtained by the clock frequency of acquired signal to zero passage testing circuit (2) back through the first analog channel switch (1) by acquired signal, describedly entered first phaselocked loop (10) by the clock frequency of acquired signal through the second analog channel switch (5) and carry out frequency multiplication, be admitted to the sampling clock of A/D modular converter (9) by the clock frequency of acquired signal by FPGA control module (11) after the described frequency multiplication, realize that described A/D modular converter (9) is to being waited cycle sampling by acquired signal.
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