CN101926172A

CN101926172A - Apparatus for transmitting and receiving signal and method of transmitting and receiving signal

Info

Publication number: CN101926172A
Application number: CN200880125541XA
Authority: CN
Inventors: 高祐奭; 文相喆
Original assignee: LG Electronics Inc
Current assignee: LG Electronics Inc
Priority date: 2008-01-25
Filing date: 2008-12-19
Publication date: 2010-12-22
Also published as: EP2388943A2; EP2255529B1; EP2255529A2; DK2388942T3; CN105703886A; SI2388942T1; US8694875B2; EP2388942A3; US20150236718A1; US20160164541A1; ES2463824T3; WO2009093809A3; CN105429735B; KR100937430B1; KR20150145734A; DK2086144T3; US20140149832A1; PL2226957T3; EP2086144A2; US8370729B2

Abstract

In one aspect of the present invention, the method receiving a signal is disclosed. The method includes receiving a signal transmitted in a radio frequency (RF) band including at least one RF channel, demodulating the received signal, parsing a preamble of a signal frame including layer-1 information, from the demodulated signal, deinterleaving bits of the layer-1 information, decoding the deinterleaved bits using an error correction decoding scheme including a shortening scheme and a puncturing scheme and obtaining physical layer pipes (PLPs) from the signal frame using the error-correction-decoded layer-1 information.

Description

Send and the device of received signal and the method for transmission and received signal

Technical field

The present invention relates to send the device with method and the transmission and the received signal of received signal, and more particularly, relate to transmission and the method for received signal and the device of transmission and received signal that can improve data transmission efficiency.

Background technology

Along with the development of digital broadcasting technology, the user has received the moving image of high definition (HD:High Definition).Along with the lasting exploitation of compression algorithm and high-performance hardware, will provide better environment for the user in future.Digital Television (DTV) system can receiving digital broadcast signal, and except vision signal and audio signal are provided to the user, also provides various auxiliary activities to the user.

Along with the development of digital broadcasting technology, to the Requirement Increases such as the business of vision signal and audio signal, and the quantity of the size of data of user expectation or broadcast channel is also increasing gradually.

Summary of the invention

Technical problem

Therefore, the present invention aims to provide a kind of transmission and the method for received signal and the device of transmission and received signal, and these apparatus and method have eliminated in essence because the restriction of prior art and one or more problem that shortcoming causes.

One object of the present invention is, a kind of transmission and the method for received signal and the device of transmission and received signal are provided, and these apparatus and method can improve data transmission efficiency.

Another object of the present invention is, a kind of transmission and the method for received signal and the device of transmission and received signal are provided, and these apparatus and method can improve the error correcting capability that constitutes professional bit.

Technical scheme

In order to realize these purposes, the invention provides a kind of transmission and the method for received signal and the device of transmission and received signal.

In one aspect of the invention, the method for transmission signal may further comprise the steps: generation will be inserted into the ground floor information in the signal frame; By the error correction coding scheme described ground floor information is encoded, described error correction coding scheme comprises the shortening scheme and deletes surplus (puncturing) scheme; Bit to the ground floor information after the error correction coding interweaves; The bit of the ground floor information after will interweaving is arranged in the lead code of described signal frame, and physical layer pipe (PLP) is set in described signal frame; And, modulate described signal frame, and send signal frame after the modulation by at least one radio frequency (RF) channel.

In another aspect of the present invention, the method for received signal may further comprise the steps: be received in the signal that sends in the RF frequency band that comprises at least one radio frequency (RF) channel; Carry out demodulation to the received signal; Resolve the lead code of the signal frame that comprises ground floor information the signal after demodulation; Bit to described ground floor information carries out deinterleaving; The bit of the error correction decoding scheme that use comprises the shortening scheme and deletes surplus scheme after to deinterleaving decoded; And the ground floor information behind the use error correction decoding obtains physical layer pipe (PLP) from described signal frame.

In another aspect of the present invention, the device that sends signal comprises: the information maker, and it is constituted as generation will be inserted into ground floor information in the signal frame; The information encoder, it is constituted as and uses the error correction coding scheme that comprises the shortening scheme and delete surplus scheme to described ground floor information and executing error correction coding, and the bit of the ground floor information after the error correction coding is interweaved; The frame constructor, its bit that is constituted as the ground floor information after interweaving is arranged in the lead code of described signal frame, and physical layer pipe (PLP) is distributed in the described signal frame; Modulator, it is constituted as the described signal frame of modulation; And transmitting element, it is constituted as by the signal frame after at least one radio frequency (RF) channel transmission modulation.

In another aspect of the present invention, the device that is used for received signal comprises: receiver, and it is constituted as and is received in the signal that sends in the RF frequency band that comprises at least one radio frequency (RF) channel; Demodulator, it is constituted as and carries out demodulation to the received signal; The information decoding device, its bit that is constituted as the ground floor information that parses from the signal frame of received signal carries out deinterleaving, and carries out error correction decoding according to the bit of the error correction decoding scheme that comprises the shortening scheme and delete surplus scheme after to deinterleaving; Information extractor, it is constituted as the ground floor information after the extraction error correction coding; And frame parser, it is constituted as the ground floor information that use extracts and resolves described signal frame and obtain physical layer pipe (PLP) from described signal frame.

Described error correction coding scheme and error correction decoding scheme comprise low-density checksum (LDPC) error correction scheme.

Can use the error correction coding and the decoding scheme of the short pattern that comprises LDPC to come described ground floor information is carried out Code And Decode.

Described ground floor information can be at least a in quantity, professional modulation intelligence and sub-district (cell) identifier of the error correction coding block in protection gap length, each signal frame.

Described information encoder can comprise: first encoder, and it is constituted as carries out first error correction coding to the bit of described ground floor information; First interleaver, it is constituted as the bit after first error correction coding is interweaved; Second encoder, it is constituted as according to described shortening scheme and describedly deletes surplus scheme the bit after interweaving is carried out second error correction coding; And second interleaver, it is constituted as the bit after second error correction coding is interweaved.

Described information decoding device can comprise: first deinterleaver, and it is constituted as carries out deinterleaving to the bit of described ground floor information; First decoder, it is constituted as basis and described shortening scheme and described scheme of deleting surplus scheme contrary, and the bit after the deinterleaving is carried out error correction decoding; Second deinterleaver, it is constituted as the bit behind the error correction decoding is carried out deinterleaving; And second decoder, it is constituted as carries out error correction decoding to the bit after the deinterleaving.

Advantageous effects

According to the device of transmission of the present invention and received signal and the method for transmission and received signal, if constituting the data symbols of PLP modulates according to identical FFT pattern with the code element that constitutes lead code, then the probability by the preamble detection data symbols is lower, and detects the probability reduction of lead code mistakenly.If comprise that as analog tv signal continuous wave (CW) disturbs, and has then reduced the probability that detects lead code when association owing to the noise DC component that produces mistakenly.

According to the device of transmission of the present invention and received signal and the method for transmission and received signal, if the size of the FFT that the data symbols that constitutes PLP is used is greater than the size of the FFT that is applied to lead code, so, even be equal to or greater than in the delay spreading channel of length of useful code element part A of lead code in length, also can improve the preamble detection performance.Since in lead code, use Cyclic Prefix (B) and cyclic suffix (C) the two, so can estimate the decimal carrier frequency shift.

Because the lead code to the signal frame that can't obtain diversity gain is carried out error correction coding, therefore can correct the mistake of information included in the lead code.Therefore, can improve the receptivity of information included in the accurate lead code.

Description of drawings

Fig. 1 illustrates the figure that is used to send professional signal frame;

Fig. 2 is the figure of structure that the first pilot signal P1 of signal frame is shown;

Fig. 3 is the figure that signaling window is shown;

Fig. 4 is the schematic diagram that an execution mode of the device that is used to send signal is shown;

Fig. 5 is the figure that the example of input processor 110 is shown;

Fig. 6 is the figure that an execution mode of coding and modulating unit is shown;

Fig. 7 is the figure that an execution mode of frame constructor is shown;

Fig. 8 is the figure that first example of the code element ratio when

mapper

131a and 131b execution mixing symbol mapped is shown;

Fig. 9 is the figure that second example of the code element ratio when

mapper

131a and 131b execution mixing symbol mapped is shown;

Figure 10 is illustrated under the LDPC general mode according to the number of symbols of every unit word of symbol mapped scheme and the figure of amount of bits;

Figure 11 is the figure that is illustrated under the LDPC general mode according to another example of the number of symbols of symbol mapped method;

Figure 12 is the figure that is illustrated under the LDPC general mode according to another example of the number of symbols of symbol mapped method;

Figure 13 is the figure that is illustrated under the short pattern of LDPC according to the number of symbols of symbol mapped scheme;

Figure 14 is the figure that is illustrated under the short pattern of LDPC according to the example of the number of symbols of symbol mapped scheme;

Figure 15 is the figure that is illustrated under the short pattern of LDPC according to another example of the number of symbols of symbol mapped scheme;

Figure 16 is the figure that the execution mode of each symbol mapper 131a shown in Figure 7 and 131b is shown;

Figure 17 is the figure that another execution mode of each

symbol mapper

131a and 131b is shown;

Figure 18 is the figure that another execution mode of symbol mapper is shown;

Figure 19 is the figure that another execution mode of each

symbol mapper

131a and 131b is shown;

Figure 20 illustrates the figure that is carried out the notion of Bit Interleave by

bit interleaver

1312a and 1312b;

Figure 21 illustrates another example of carrying out the bit interleaver that interweaves;

Figure 22 illustrates the skew of using in the Bit Interleave according to the symbol mapped method;

Figure 23 is the type that illustrates according to

symbol mapper

1315a and 1315b, the figure of first example of the quantity of the row and column of the memory of

bit interleaver

1312a and 1312b;

Figure 24 is the type that illustrates according to

symbol mapper

1315a and 1315b, the figure of second example of the quantity of the row and column of the memory of

bit interleaver

1312a and 1312b;

Figure 25 is the figure of notion that another execution mode that interweaves of bit interleaver is shown;

Figure 26 is the figure that another execution mode of bit interleaver is shown;

Figure 27 is the figure that another execution mode of bit interleaver is shown;

Figure 28 is the figure that another execution mode of Bit Interleave is shown;

Figure 29 illustrates demodulation multiplexer 1313a and the 1313b figure to the notion of the demultiplexing of input bit;

Figure 30 illustrates the figure that inlet flow is carried out an execution mode of demultiplexing by demodulation multiplexer;

Figure 31 is the figure that illustrates according to an example of the demultiplexing type of symbol mapped method;

Figure 32 illustrates the figure that incoming bit stream is carried out an execution mode of demultiplexing according to the demultiplexing type;

Figure 33 is the figure that the type of the demultiplexing of determining according to the encoding rate and the symbol mapped method of error correction coding is shown;

Figure 34 illustrates the figure that represents an example of Deplexing method with equation;

Figure 35 illustrates to utilize symbol mapper to shine upon the figure of an example of code element;

Figure 36 is the figure that an example of multipath signal encoder is shown;

Figure 37 is the figure that an execution mode of modulator is shown;

Figure 38 is the figure that an execution mode of analog processor 160 is shown;

Figure 39 be illustrate can received signal the figure of an execution mode of signal receiving device of frame;

Figure 40 is the figure that an execution mode of signal receiver is shown;

Figure 41 is the figure that an execution mode of demodulator is shown;

Figure 42 is the figure that the multipath signal decoder is shown;

Figure 43 is the figure that an execution mode of frame parser is shown;

Figure 44 is the figure that the execution mode of each

symbol de-maps device

247a and 247p is shown;

Figure 45 is the figure that another execution mode of each

symbol de-maps device

247a and 247p is shown;

Figure 46 is the figure that another execution mode of each

symbol de-maps device

247a and 247p is shown;

Figure 47 is the figure that another execution mode of each

symbol de-maps device

247a and 247p is shown;

Figure 48 illustrates the figure that the sub-stream behind the demultiplexing is carried out a multiplexing execution mode;

Figure 49 is the figure that an example of decoding and demodulating unit is shown;

Figure 50 is the figure that an execution mode of output processor is shown;

Figure 51 is the figure that another execution mode of the sender unit that is used to send signal frame is shown;

Figure 52 is the figure that another execution mode of the signal receiving device that is used for the received signal frame is shown;

Figure 53 is the figure of execution mode that the structure of first pilot signal is shown;

Figure 54 illustrates the figure that detects preamble signal shown in Figure 50 and estimate the execution mode of timing slip and frequency displacement;

Figure 55 is the figure of another execution mode that the structure of first pilot signal is shown;

Figure 56 illustrates the figure that detects first pilot signal shown in Figure 55 and measure the execution mode of timing slip and frequency displacement;

Figure 57 illustrates to detect first pilot signal and use testing result to measure the figure of the execution mode of timing slip and frequency displacement;

Figure 58 is the figure that the execution mode of the method that sends signal is shown;

Figure 59 is the figure of execution mode that the method for received signal is shown; And

Figure 60 is illustrated in the flow chart of discerning first pilot signal in the demodulation process and estimating the execution mode of skew;

Figure 61 illustrates another example according to the method for transmission of the present invention and received signal;

Figure 62 is the figure that another execution mode of the device that is used to send signal is shown;

Figure 63 is the figure that the execution mode of information encoder 1303 is shown;

Figure 64 is the figure that another execution mode of the device that is used for received signal is shown;

Figure 65 is the figure that illustrates the detailed execution mode of ground floor information and second layer information decoding; And

Figure 66 illustrates the flow chart that is used to send with the method for received signal.

Embodiment

Now, will describe preferred implementation of the present invention in detail, the example illustration of these execution modes in the accompanying drawings.Whenever possible, all using identical label to represent same or analogous parts among the figure.

In the following description, the broadcasted content that term " business " expression can be sent by signal transmission/receive represents that perhaps content provides (content provision).

Before the signal transmission of describing according to embodiment of the present invention, the signal frame that earlier signal transmission according to embodiment of the present invention is sent/receives is described.

Fig. 1 illustrates the signal frame according to the transmission business of embodiment of the present invention.

Signal frame shown in Figure 1 illustrates the exemplary signal frame that is used for sending the broadcasting service that comprises audio/video (A/V) stream.In this case, multiplexing single business in time and frequency channels, and send business after multiplexing.Above-mentioned side signal transmission case is called time-frequency slicing (TFS:time-frequency slicing) scheme.Compare with the situation that only sends single business to 1 radio frequency (RF) frequency band, sender unit according to embodiment of the present invention sends signal service by at least one RF frequency band (also may be a plurality of RF frequency bands), thereby this sender unit can obtain to send the statistical multiplexing gain (statistical multiplexing gain) of more business.This signal transmission sends/receives single business on a plurality of RF channels, thereby this signal transmission can obtain frequency diversity gain.

First to the 3rd business (professional 1-3) is sent to four RF frequency bands (RF1-RF4).Yet this RF number of frequency bands and this number of services only are disclosed for illustrative purpose, therefore also can use other quantity as required.Two reference signals (that is, first pilot signal (P1) and second pilot signal (P2)) are set at the start-up portion of signal frame.For example, under the situation of RF1 frequency band, first pilot signal (P1) and second pilot signal (P2) are arranged on the start-up portion of signal frame.The RF1 frequency band comprise three with professional 1 time slot that is associated, two and professional 2 time slots that are associated and one and business 3 time slots that are associated.Also the time slot that is associated with other business can be set in place in professional 3 single time slots that are associated after other time slots (time slot 4-17) in.

The RF2 frequency band comprises first pilot signal (P1), second pilot signal (P2) and other time slots 13-17.In addition, the RF2 frequency band comprise three with professional 1 time slot that is associated, two and professional 2 time slots that are associated and one and business 3 time slots that are associated.

According to time-frequency slicing (TFS) scheme professional 1-3 is carried out multiplexingly, then they are sent to RF3 and RF4 frequency band.The modulation scheme that signal sends can be based on OFDM (OFDM) scheme.

In signal frame, make the individual service skew to RF frequency band (in signal frame, existing under the situation of a plurality of RF frequency bands) and time shaft.

If arrange the signal frame that equates with above-mentioned signal frame in time continuously, then can constitute superframe (super-frame) by a plurality of signal frames.Expansion frame in the future also can be set in these signal frames.If expansion frame in the future is arranged in the middle of these signal frames, then can finish superframe at expansion frame place in the future.

Fig. 2 illustrates first pilot signal (P1) that comprises in the signal frame according to Fig. 1 of embodiment of the present invention.

The first pilot signal P1 and the second pilot signal P2 are arranged on the start-up portion of signal frame.Modulate the first pilot signal P1 by 2K FFT pattern, and the first pilot signal P1 can comprised that 1/4 protection sends in (guard interval) at interval.In Fig. 2, the frequency band of the 7.61Mhz of the first pilot signal P1 comprises the frequency band of 6.82992Mhz.First pilot signal is utilized 256 carrier waves in 1705 active carriers.Average per 6 carrier waves use an active carriers.Data carrier can be set brokenly at interval according to 3,6 and 9 order.In Fig. 2, solid line represents to use the position of carrier wave, and shallow dotted line represents not use the position of carrier wave, and chain-dotted line represents not use the center of carrier wave.In first pilot signal, can carry out symbol mapped to using carrier wave by two-phase PSK (BPSK:Binary Phase Shift Keying), and can modulate PRBS pseudo-random bit sequence (PRBS:pseudo random bit sequence).Can represent to be used for the size of the FFT of second pilot signal by a plurality of PRBS.

Signal receiving device detects the structure of pilot signal, and utilizes detected structure recognition time frequency slicing (TFS).Signal receiving device obtains the FFT size of second pilot signal, the rough frequency displacement (coarse frequency offset) of compensation received signal, and acquisition time is synchronous.

Can be in first pilot signal signalization transport-type and transmission parameter.

Can send the second pilot signal P2 at interval according to the FFT size and the protection that equate with the FFT size and the protection interval of data symbols.In second pilot signal, serve as to use single carrier wave as pilot frequency carrier wave at interval with three carrier waves.Signal receiving device utilizes the skew of second pilot signal compensation fine frequency synchronisation, and carries out meticulous time synchronized.Second pilot signal is sent the information of ground floor (L1) in the middle of Open System Interconnection (OSI) layer.For example, second pilot signal can comprise physical parameter and frame tectonic information.The second pilot signal transmitter-receiver can be with the parameter value that visits physical layer pipe (PLP:Physical Layer Pipe) Business Stream.

L1 (ground floor) information that comprises among the second pilot signal P2 is as follows.

Ground floor (L1) information comprises the length indicator of the length of indicating the data that comprise L1 information, makes it possible to easily utilize the signaling channel of the ground floor and the second layer (L1 and L2).Ground floor (L1) information comprise frequency indicator, protection gap length, each frame of being associated with individual physical channel FEC (forward error correction) piece maximum quantity and with FEC block buffer that current/previous frame in each physical channel is associated in the quantity of the actual FEC piece that will comprise.In this case, frequency indicator indication and the corresponding frequency information of RF channel.

Ground floor (L1) information can comprise the various information that are associated with individual time slot.For example, ground floor (L1) information comprise with the professional frame number that is associated, in the OFDM code element, include the OFDM carrier wave accuracy time slot initial address, time slot length, with the corresponding time slot of OFDM carrier wave, the most last OFDM carrier wave in amount of bits, professional modulation intelligence, business model rate information and multiple-input and multiple-output (MIMO) scheme information of filling.

The quantity of the added bit that ground floor (L1) information can comprise sub-district ID, be similar to notification message business traffic flag, the present frame quantity and being used for of (for example, emergency message) is used in the future.In this case, the broadcasting area of sub-district ID indication broadcast transmitter transmission.

The second pilot signal P2 is used to carry out channel estimating, so that the code element that comprises in the P2 signal is decoded.The second pilot signal P2 can be used as the initial value at the channel estimating of next data symbols.The second pilot signal P2 can also send the second layer (L2) information.For example, second pilot signal can be described the information that is associated with transport service in the second layer (L2) information.Sender unit is decoded to second pilot signal, makes the business information that it comprises in can acquisition time frequency slicing (TFS) frame, and can effectively carry out scan channel.Simultaneously, this second layer (L2) information can be included among the specific PLP of TFS frame.According to another example, L2 information can be included among the specific PLP, and business description information also can send in this specific PLP.

For example, second pilot signal can comprise two OFDM code elements of 8k FFT pattern.Usually, second pilot signal can be any in the following: four OFDM code elements of two OFDM code elements of the single OFDM code element of 32K FFT pattern, the single OFDM code element of 16K FFT pattern, 8K FFT pattern, 4K FFT pattern and eight OFDM code elements of 2K FFT pattern.

In other words, in the second pilot signal P2, can comprise single OFDM code element with big FFT size or a plurality of OFDM code elements that have little FFT size separately, thereby can keep to send to the capacity of pilot tone.

If send to the capacity that the information of second pilot signal has exceeded the OFDM code element of second pilot signal, then can also use the OFDM code element after second pilot signal.The L1 (ground floor) and L2 (second layer) information that comprise in second pilot signal are carried out error correction coding, interweave then, even make that impulsive noise occurring also can carry out the data recovery.

As mentioned above, L2 information can also be included among the specific PLP of business transferring descriptor.

Fig. 3 illustrates the signaling window according to embodiment of the present invention.Time-frequency slicing (TFS) frame illustrates the skew notion of signaling information.The ground floor that comprises in second pilot signal (L1) information comprises the frame tectonic information and the physical layer information of the signal receiving device needs that the data code element is decoded.Therefore, be included in second pilot signal if be arranged in the information of the subsequent data code element after second pilot signal, and send resulting second pilot signal, then signal receiving device may can not be decoded to above-mentioned subsequent data code element immediately owing to the decode time of second pilot signal.

Therefore, as shown in Figure 3, the L1 information that comprises in second pilot signal (P2) comprises the information of single time-frequency slicing (TFS) frame sign, and comprises the information of being separated by and comprising in the signaling window of position of signaling window side-play amount with second pilot signal.

Simultaneously, in order to carry out channel estimating to constituting this professional data symbols, data symbols can comprise scattered pilot and continuous pilot.

Signal transmission/the receiving system that can send/receive the signal frame shown in Fig. 1-3 is described below.Can on a plurality of RF channels, send and receive separate operation.The stream that sends each professional path or send via this path is called as PLP.PLP can be distributed in the time slot according to the time division of a plurality of RF channels or single RF frequency band.Signal frame can transmit the PLP that divides according to the time at least one RF channel.In other words, can transmit single PLP by at least one RF channel with zone of dividing according to the time.Below, send/the signal transmission/receiving system of received signal frame via at least one RF frequency band open.

Fig. 4 is an illustration according to the block diagram of device that is used to send signal of an embodiment of the invention.With reference to Fig. 4, this sender unit comprise input processor 110, coding and modulating unit 120, frame constructor 130, MIMO/MISO encoder 140, MIMO/MISO encoder 140 a plurality of modulators (150a ..., 150r) and a plurality of analog processor (160a, ..., 160r).

Input processor 110 receives the stream that is equipped with a plurality of business, generates the individual base band frame of P (P is a natural number), and exports this P base band frame, and this base band frame comprises and corresponding modulation of the transmit path of separate operation and coded message.

Coding and modulating unit 120 receive the base band frame from input processor 110, and each base band frame is carried out chnnel coding and interweaved, and the delivery channel coding and the result that interweaves.

Frame constructor 130 forms the frame that the base band frame that comprises among P the PLP is sent to the individual RF channel of R (R is a natural number), and formed frame is split and split frame is outputed to path corresponding to R RF channel.A plurality of business can be multiplexing in time in single RF channel.The signal frame that generates from frame constructor 140 can comprise time-frequency slicing (TFS) structure, wherein, has carried out multiplexing to business in time domain and frequency domain.

140 pairs of signals that will send to R RF channel of MIMO/MISO encoder are encoded, and the signal after will encoding output to A (A is a natural number) the corresponding path of individual antenna on.Signal after MIMO/MISO encoder 140 will be encoded outputs on this A antenna, in the signal behind this coding the individual signals that will send to single RF channel is encoded, make it possible to send signal/from MIMO (multiple-input and multiple-output) or MISO (the single output of many inputs) structure received signal to MIMO (multiple-input and multiple-output) or MISO (the single output of many inputs) structure.

Modulator (150a ..., 150r) will be modulated into time-domain signal via the frequency-region signal of the path input corresponding with each RF channel.Modulator (150a ..., 150r) signal of input is modulated according to OFDM (OFDM) scheme, and the signal after the output modulation.

Analog processor (160a ..., 160r) input signal is converted to the RF signal, make this RF signal can output on the RF channel.

According to the sender unit of present embodiment can comprise with the modulator of the corresponding predetermined quantity of quantity of RF channel (150a ..., 150r) and with the analog processor of the corresponding predetermined quantity of RF channel quantity (160a ..., 160r).Yet under the situation of using the MIMO scheme, the quantity of analog processor must equal the product of R (that is the quantity of RF channel) and A (that is the quantity of antenna).

Fig. 5 is an illustration according to the block diagram of the input processor 110 of embodiment of the present invention.With reference to Fig. 5, input processor 110 comprise first-class multiplexer 111a, the first professional splitter 113a and a plurality of first base band (BB) frame constructor (115a ..., 115m).Input processor 110 comprise the second stream multiplexer 111b, the second professional splitter 113b and a plurality of second base band (BB) frame constructor (115n ..., 115p).

For example, first-class multiplexer 111a receives a plurality of mpeg 2 transport streams (TS), received MPEG-2TS stream is carried out multiplexing, and exports MPEG-2TS stream after multiplexing.The first professional splitter 113a receives this stream after multiplexing, each professional inlet flow split, and the stream of output after splitting.As mentioned above, suppose to be called PLP via the business that the physical channel path sends, the first professional splitter 113a splits the business that will send to each PLP, and the business after the output fractionation.

The one BB frame constructor (115a ..., 115m) structure will send to the data that comprise in the business of each PLP with the form of particular frame, and exports the data of this particular frame format.The one BB frame constructor (115a ..., 115m) structure comprises header and the frame that provides the payload of business datum.The header of each frame can comprise based on the pattern information of the modulation of business datum and coding and based on the count value of inlet flow being carried out the clock rate of synchronous modulator.

The second stream multiplexer 111b receives a plurality of streams, the stream of input is carried out multiplexing, and exports stream after multiplexing.For example, substitute MPEG-2 TS stream, the second stream multiplexer 111b can also carry out multiplexing to Internet protocol (IP) stream.These streams can encapsulate by general stream encapsulation (GSE:generic stream encapsulation) scheme.The second stream multiplexer 111b multiplexing stream can be any stream.Therefore, flowing above-mentioned and MPEG-2TS not, homogeneous turbulence is called general stream (GS stream).

General stream after the second professional splitter 113b reception is multiplexing splits received general stream according to each business (that is, the PLP type), and the GS stream after the output fractionation.

The 2nd BB frame constructor (115n ..., 115p) structure will send to the business datum of each PLP with the form of particular frame (as a signal processing unit), and exports resulting business datum.By the 2nd BB frame constructor (115n ..., 115p) Gou Zao frame format can be as required with a BB frame constructor (115a ..., 115m) Gou Zao frame format is identical.If desired, another execution mode can also be proposed.In another embodiment, by the 2nd BB frame constructor (115n ..., 115p) Gou Zao frame format can with a BB frame constructor (115a ..., 115m) Gou Zao frame format difference.The MPEG-2TS header also comprises the packet synchronization word (Packet Syncword) that does not comprise in the GS stream, causes occurring different headers.

Fig. 6 has been an illustration according to the coding of embodiment of the present invention and the block diagram of modulating unit.Coding and modulating unit comprise first interleaver 123, second encoder 125 and second interleaver 127.

First encoder 121 is used as the external encoder of input base band frame, and can carry out error correction coding.First encoder 121 utilizes BCH, and (Bose-Chaudhuri-Hocquenghem: BCH Bose-Chadhuri-Hocquengham) scheme is carried out error correction coding to input base band frame.Data behind 123 pairs of codings of first interleaver interweave, and make it can prevent to produce burst error in sending signal.Can not comprise first interleaver 123 in the above-mentioned execution mode.

Second encoder 125 is as the internal encoder of the dateout of the dateout of first encoder 121 or first interleaver 123, and can carry out error correction coding.Low-density checksum position (LDPC:low density parity bit) scheme can be used as the error correction coding scheme.Data after the error correction coding that 127 pairs second encoders of second interleaver 125 generate are mixed, and export mixed data.First interleaver 123 and second interleaver 127 can bitwise be carried out data and interweave.

Coding and modulating unit 120 relate to single PLP stream.Carry out error correction coding and modulation by coding and 120 pairs of PLP streams of modulating unit, then PLP stream is sent to frame constructor 130.

Fig. 7 is an illustration according to the block diagram of the frame constructor (builder) of embodiment of the present invention.With reference to Fig. 7, frame constructor 130 is from the stream in coding and a plurality of paths of modulating unit 120 receptions, and received stream is arranged in the individual signals frame.For example, the frame constructor can comprise the first mapper 131a and very first time interleaver 132a in first path, and can comprise the second mapper 131b and the second time-interleaved device 132b in second path.The quantity in input path equals to be used for the quantity of PLP of professional transmission or the quantity of the stream that sends via each PLP.

The first mapper 131a carries out mapping according to the first symbol mapped scheme to the data that comprise in the inlet flow.For example, the first mapper 131a can utilize QAM scheme (for example, 16QAM, 64QAM and 256QAM) that the input data are carried out mapping.

If the first mapper 131a carries out the mapping of code element, then importing data can be mapped on the multiple code element according to multiple symbol mapped scheme.For example, the first mapper 131a will import data qualification and become base band frame unit and base band frame subelement.Can mix symbol mapped to each classification back data by at least two kinds of QAM schemes (for example, 16QAM and 64QAM).Therefore, can based on different symbol mapped schemes with independently at interval with the data map that comprises in the single business on code element.

Very first time interleaver 132a receives the code element by first mapper 131a mapping, and can carry out interweaving in the time domain.The data map that the first mapper 131a will comprise from the frame unit after coding and the error correction coding that receives of modulating unit 120 is to code element.Very first time interleaver 132a receives the sequence of symhols by first mapper 131a mapping, and is that unit interweaves to received sequence of symhols with the frame through error correction.

Like this, the time-interleaved device 132p of p mapper 131p or p receives the business datum that will send to p PLP, according to p symbol mapped scheme this business datum is mapped to code element.Can in time domain, interweave to code element through mapping.Should be noted that this symbol mapped scheme is identical with symbol mapped scheme and the interleaving scheme of the very first time interleaver 132a and the first mapper 131a with this interleaving scheme.

The symbol mapped scheme of the first mapper 131a can be identical or different with the symbol mapped scheme of p mapper 131p.The first mapper 131a and p mapper 131p can utilize identical or different mixing code element mapping scheme with data map in each code element.

To the data that are positioned at the time-interleaved device on each path (promptly, by the very first time interleaver 132a business datum that interweaves and the business datum that will send to R RF channel by the time-interleaved device 132p of p) interweave, make physical channel on a plurality of RF channels, to interweave to above-mentioned data.

Be that the stream that receives in the path of quantity of PLP is associated in quantity, the TFS signal frame of TFS frame constructor 133 structure such as above-mentioned signal frames makes it possible to according to the RF channel business be carried out time shift.The business datum that receives in 133 pairs of any paths of TFS frame encoder splits, and exports the business datum of the data that are split into R RF frequency band according to the signal dispatching scheme.

TFS frame constructor 133 receives first pilot signal and second pilot signal from signaling information element (by the Ref/PL signal indication) 135, first pilot signal and second pilot signal are arranged in the signal frame, and in second pilot signal, insert the signaling-information (L1 and L2) of above-mentioned physical layer.In this case, first pilot signal and second pilot signal are as the initial signal of the signal frame that comprises in each the RF channel in the TFS signal frame that receives from signaling information element (Ref/PL signal) 135.As shown in Figure 2, first pilot signal can comprise transport-type and basic transmission parameter, and second pilot signal can comprise physical parameter and frame tectonic information.And second pilot signal comprises L1 (ground floor) signaling information and L2 (second layer) signaling information.

R frequency interleaver (137a ..., 137r) business datum to the corresponding RF channels that will send to the TFS signal frame interweaves in frequency domain.Frequency interleaver (137a ..., 137r) rank of the data cell that can comprise in the OFDM code element interweaves to this business datum.

Therefore, handle, make this business datum can in specific frequency domain, not lose carrying out frequency selective fading with the business datum that the TFS signal frame sends to each RF channel.

Fig. 8 is the figure that first example of the code element ratio when mapper 131a and 131b execution mixing symbol mapped is shown.This illustrates, when in the general mode (code length after the error correction coding is 64800 bits) in LDPC error correction coding pattern by coding and modulating unit when carrying out error correction coding, by the quantity of the bit of a subcarrier (unit) transmission.

For example, if

mapper

131a and 131b use 256QAM to carry out symbol mapped, then 64800 bits are mapped to 8100 code elements.If mapper 131a and 131b use 256QAM and 64QAM to carry out mixing symbol mapped (Hyb 128-QAM) by 3: 2 ratio, then the number of symbols by the 256QAM mapping is 4860, and the number of symbols of shining upon by 64QAM is 4320.The quantity of the bit that each subcarrier (unit) sends is 7.0588.

If use the symbol mapped method of 64QAM, then the input data map can be become 10800 code elements, and can send 6 bits in every unit.If by 64QAM and 16QAM (64QAM: 16QAM=3: 2, mixing code element mapping method Hyb32-QAM) becomes code element with data map, then can send 5 bits by a subcarrier (unit).

If by the 16QAM method data map is become code element, then data are mapped to 16200 code elements, and wherein each code element is used to send 4 bits.

Similarly, if by 16QAM and QPSK (16QAM: QPSK=2: 3, mixing code element mapping method Hyb8-QAM) becomes code element with data map, then can send 3 bits by a subcarrier (unit).

If data map is become code element by the QPSK method, then data map can be become 32400 code elements, wherein each code element is used to send 2 bits.

Fig. 9 illustrates the symbol mapped method that LDPC error correction/encoding method by short pattern (code length of error correction coding the is 16200 bits) data after to error correction are carried out, this method is equivalent to the symbol mapped method of Fig. 8, and the bit number according to every subcarrier of symbol mapped method is shown.

According to the symbol mapped method (as, 256QAM, Hyb128-QAM, 64QAM, Hyb32-QAM, 16QAM, Hyb8-QAM and QPSK), the amount of bits that is sent by subcarrier equals the quantity (64800 bit) of general mode, and still, the code element of transmission sum is different with general mode.For example,, send 16200 bits, in Hyb 128QAM, by sending 16200 bits according to 1215 code elements of 256QAM and according to 1080 code elements (2295 code elements altogether) of 64QAM by 2025 code elements at 256QAM.

Therefore, can adjust the message transmission rate of the every subcarrier (unit) that is used for each PLP according to mixing code element mapping method or single symbol mapped method.

Figure 10 is the figure that is illustrated under the LDPC general mode according to the amount of bits of the number of symbols of symbol mapped method and each unit word (cell word).If the TFS signal frame comprises at least one RF channel, then the code element that constitutes specific PLP can be distributed to the RF channel equably.Can be more effectively addressing be carried out in the position of the PLP code element of distributing to the RF channel.Therefore, when signal receiving device is selected the RF channel, can reduce the bit that is used for specific PLP is carried out addressing.

In the figure, the symbol mapped method representation of being represented by 256-QAM is according to 256QAM: 64QAM=8: the bit that 1 ratio will constitute single error correction coding block is mapped to the method for code element.According to this symbol mapped method, by the amount of bits in the single error correction coding block of 256-QAM method is 57600, by the amount of bits in the single error correction coding block of 256-QAM method is 1200, total number of symbols in the piece is 8400, and the amount of bits of each unit word is 7.714285714.

The symbol mapped method representation of being represented by Hyb 128-QAM is according to 256QAM: 64QAM=8: the bit that 7 ratio will constitute single error correction coding block is mapped to the method for code element.According to this Hyb128-QAM symbol mapped method, the quantity of the total code element in single error correction coding block is 9600, and the amount of bits of each unit word is 6.75.

According to the symbol mapped method of being represented by 64QAM, the quantity of the total code element in single error correction coding block is 10800, and the amount of bits of each unit word is 6.

The symbol mapped method representation of being represented by Hyb 32-QAM is according to 64QAM: 32QAM=5: the bit that 4 ratio will constitute single error correction coding block is mapped to the method for code element.According to this Hyb32-QAM symbol mapped method, the quantity of the total code element in single error correction coding block is 13200, and the amount of bits of each unit word is 4.9090909.

The symbol mapped method representation of being represented by 16QAM is according to 64QAM: QPSK=1: the bit that 8 ratio will constitute single error correction coding block is mapped to the method for code element.According to this 16QAM symbol mapped method, the quantity of the total code element in an error correction coding block is 15600, and the amount of bits of each unit word is 4.153846154.

The symbol mapped method representation of being represented by Hyb 8-QAM is according to 64QAM: QPSK=2: the bit that 1 ratio will constitute single error correction coding block is mapped to the method for code element.According to this Hyb8-QAM symbol mapped method, the quantity of the total code element in an error correction coding block is 21600, and the amount of bits of each unit word is 3.

According to the symbol mapped method of being represented by QPSK, the quantity of the total code element in an error correction coding block is 32400, and the amount of bits of each unit word is 2.

When the symbol allocation that will constitute PLP was given the RF channel, when the quantity of the code element of distributing to each RF channel equated, the diversity gain of frequency domain can maximize.If consider the maximum of 6 RF channels, 1 to 6 least common multiple is 60, and the greatest common divisor of quantity that is mapped to the code element of an error correction coding block is 1200.Therefore, if give each of RF channel, then code element can be distributed to equably whole RF channels with the integral multiple symbol allocation of 1200/60=20.At this moment,, so, compare, can reduce the addressing expense of log2 (20) 4.32 bits with the situation of one by one code element being carried out addressing if consider 20 code elements as one group and this group carried out addressing.

Figure 11 is the figure that is illustrated under the LDPC general mode according to another example of the number of symbols of symbol mapped method.In the example of this figure, use following method as the symbol mapped method: to use 256QAM and 64QAM code element (256QAM: 64QAM=4: 256-QAM method 1); Use 256QAM and 64QAM code element (256QAM: 64QAM=8: Hyb 128-QAM method 7); The 64QAM method; Use 64QAM and 8QAM code element (64QAM: 8QAM=3: Hyb 32-QAM method 2); Use 16QAM and QPSK code element (16QAM: QPSK=1: 16QAM method 14); Use 16QAM: the Hyb 8-QAM method of QPSK code element=2: 1; And QPSK method.Greatest common divisor (GCD) according to the quantity of total code element of the error correction coding block (general mode) of these symbol mapped methods is 720.Therefore, if give each of RF channel, then these code elements can be distributed to equably whole RF channels with the integral multiple symbol allocation of 12 (=720/60).At this moment,, so, compare, can reduce the addressing expense of log2 (12) 3.58 bits with the situation of one by one code element being carried out addressing if consider 12 code elements as one group and this group carried out addressing.Signal receiving device can be collected the PLP code element of being distributed by addressing scheme, and obtains the PLP Business Stream.

Figure 12 is the figure that is illustrated under the LDPC general mode according to another example of the number of symbols of symbol mapped method.In the example of this figure, use 256-QAM scheme, Hyb 128-QAM scheme, 64QAM scheme, Hyb 32-QAM scheme, 16QAM scheme, Hyb 8-QAM scheme and QPSK scheme as the symbol mapped method.256-QAM symbol mapped method is used 256QAM and 64QAM code element, and (256QAM: 64QAM=44: 1), Hyb 128-QAM symbol mapped method is used 256QAM and 64QAM code element (256QAM: 64QAM=28: 17).The Hyb32-QAM method is used 64QAM and 8QAM code element (64QAM: 8QAM=3: 2), 16QAM symbol mapped method is used 16QAM and QPSK code element, and (16QAM: QPSK=1: 14), Hyb8-QAM symbol mapped method is used 16QAM and QPSK code element (16QAM: QPSK=2: 1).GCD according to total number of symbols of the error correction coding block (general mode) of symbol mapped method is 240.Therefore, if give each of RF channel, then code element can be distributed to equably whole RF channels with the integral multiple symbol allocation of 240/60=4.At this moment,, so, compare, can reduce the addressing expense of log2 (4) 2 bits with the situation of one by one code element being carried out addressing if consider 4 code elements as one group and this group carried out addressing.Therefore, even the quantity of RF channel is in 1 to 6 any one in signal frame, also the PLP code element can be distributed to the RF channel equably.

Figure 13 is the figure that is illustrated under the short pattern of LDPC according to the number of symbols of symbol mapped method.As mentioned above, if carry out symbol mapped, then the PLP code element can be distributed to the RF channel equably, and can reduce the expense of PLP code element addressing according to this example.Symbol mapped method shown in this figure is identical with the symbol mapped method shown in Figure 10.But, because the amount of bits of the short pattern of LDPC is different from the amount of bits of general mode, therefore, be different from Figure 10, be 300 according to the GCD of total number of symbols of the error correction coding block (short pattern) of this symbol mapped method.Therefore, if give each of RF channel, then these code elements can be distributed to equably whole RF channels with the integral multiple symbol allocation of 300/60=5.At this moment, if with 5 code elements as one group and this group carried out addressing, so, compare with the situation of one by one code element being carried out addressing, can reduce the addressing expense of log2 (5) bit.Therefore, in this embodiment, when the PLP code element of dividing was carried out addressing, the addressing bit had been saved log2 (5) bit.

Figure 14 is the figure that is illustrated under the short pattern of LDPC according to the example of the number of symbols of symbol mapped method.The symbol mapped method of this figure is equal to the method shown in Figure 11.In this example, be 180 according to the GCD of total number of symbols of the error correction coding block of this symbol mapped method (short pattern), this can be used for the PLP symbol allocation of a RF channel and to the addressing of code element distribution.In this embodiment, the addressing bit has been saved log2 (3) bit.

Figure 15 is the figure that is illustrated under the short pattern of LDPC according to another example of the number of symbols of symbol mapped method.The symbol mapped method of this figure is equal to the method shown in Figure 12.In this example, the GCD according to total number of symbols of the error correction coding block of this symbol mapped method (short pattern) is 60.In this embodiment, the addressing bit has been saved log2 (1) bit (that is, not saving the addressing bit).

Figure 16 is the figure that the example of each symbol mapper 131a shown in Figure 7 and 131b is shown.Each

symbol mapper

131a and 131b comprise first order mapper 1315a, second level mapper 1315b, code element combiner 1317 and error correction block combiner 1318.

Bitstream parser 1311 receives the PLP Business Stream and splits the Business Stream that receives from coding and modulating unit.

The bit of the Business Stream that first order symbol mapper 1315a will split by high-order symbol mapped method is mapped to code element.The bit of the Business Stream that second level symbol mapper 1315b will be split by the symbol mapped method of low order more is mapped to code element.For example, in above-mentioned example, first order symbol mapper 1315a can be mapped to code element with bit stream according to 256QAM, and second level symbol mapper 1315b can be mapped to code element with bit stream according to 64QAM.

Code element combiner 1317 will be merged into a code element stream from the code element of

symbol mapper

1315a and 1315b output, and export this code element stream.Code element combiner 1317 can be exported the code element stream that comprises among the PLP.

Error correction block combiner 1318 can be unit with the code block of error correction coding, the code element stream that output symbol combiner 1317 merges.Error correction block combiner 1318 exportable block of symbols, feasible at least one the RF frequency band that can equably the error correction coding code block be distributed to the TFS signal frame.Error correction block combiner 1318 exportable block of symbols make the length of block of symbols of error correction coding block of general mode equal the length of block of symbols of the error correction coding block of short pattern.For example, 4 block of symbols of lacking the error correction coding block of pattern can be merged into a block of symbols.

Error correction block combiner 1318 can split code element stream according to the common multiple of RF number of frequency bands, makes the signal frame constructor equably code element is arranged into the RF frequency band.If the maximum number of the RF frequency band in the signal frame is 6, then error correction block combiner 1318 output symbol piece by this way promptly, makes the code element sum to be divided exactly by 60 (1,2,3,4,5 and 6 common multiples).

The code element that comprises in can the output symbol piece is set to distribute to equably 6 RF frequency bands.Therefore, though will merge according to the error correction mode and the symbol mapped method of code check, the code element that constitutes PLP is assigned to the RF frequency band equably.

Figure 17 is the figure that another execution mode of each

symbol mapper

131a and 131b is shown.Except also comprising first order calibration of power unit 1316a and calibration of power unit, second level 1316b, the execution mode of this figure is similar to the execution mode of Figure 16.

First order calibration of power unit 1316a calibrates the power of the code element of being shone upon by first order symbol mapper 1315a according to the size of constellation, and the code element after the output calibration.Calibration of power unit, second level 1316b calibrates the power of the code element of being shone upon by second level symbol mapper 1315b according to the size of constellation, and the code element after the output calibration.Therefore, although in a PLP, change the symbol mapped method or in a plurality of PLP, change the symbol mapped method,, then can improve the signal receiving performance of receiver if adjust power by the code element of symbol mapped method according to the size of constellation.

Code element combiner 1317 merges the code element by calibration of

power unit

1316a and 1316b calibration, and exports a code element stream.

Figure 18 is the figure that another execution mode of symbol mapper is shown.In the execution mode of this figure, symbol mapper is included in second encoder 125 and second interleaver 127 that comprises in coding and the modulating unit.That is to say that if use this execution mode, then coding and modulating unit can only comprise first encoder 121, first interleaver 123 and second encoder 125.

The execution mode of code element encoder comprises bitstream parser 1311, first order bit interleaver 1312a, second level bit interleaver 1312b, first order demodulation multiplexer 1313a, second level demodulation multiplexer 1313b, first order symbol mapper 1315a, second level symbol mapper 1315b and code element combiner 1317.

When second encoder 125 was carried out the LDPC error correction coding, the length of error correction coding block (for example, the length of the length of 64800 bits and 16200 bits) can change according to the LDPC pattern.If the bit that comprises in the error correction coding block is mapped to code element, the error correcting capability that then is included in the bit in the unit word that constitutes code element can change according to the position of bit.For example, unit word (it is a code element) can be determined according to the code check and the symbol mapped method (the symbol mapped method is high-order symbol mapped method or low order symbol mapped method) of error correction coding.If error correction coding is LDPC, then the error correcting capability of bit changes according to the position of bit in error correction coding block.For example, the reliability of having carried out the bit of coding according to the characteristic of the H matrix that is used for irregular LDPC error correction/encoding method can change according to the position of bit.Therefore, the order that constitutes the bit of the unit word that is mapped to code element is changed, thereby has adjusted the error correcting capability of the bit a little less than the error correcting capability in the error correction coding block, and can adjust the robustness of the mistake of opposing bit-level.

At first, for example, second encoder 125 utilizes the LDPC error correction/encoding method to carry out error correction coding at being included in the stream among the PLP.

Bitstream parser 1311 receives Business Stream according to PLP, and the Business Stream that receives is split.

The bit that comprises in first bit stream of first order bit interleaver 1312a to the Business Stream of fractionation interweaves.Similarly, the bit that comprises in second bit stream of bit interleaver 1312b in the second level to the Business Stream of fractionation interweaves.

First order bit interleaver 1312a and second level bit interleaver 1312b can be corresponding to second interleavers 127 as inner interleaver.To introduce the deinterleaving method of first order bit interleaver 1312a and second level bit interleaver 1312b after a while.

First order demodulation multiplexer 1313a and second level demodulation multiplexer 1313b carry out demultiplexing to the bit of the bit stream that interweaved by first order bit interleaver 1312a and second level bit interleaver 1312b.Demodulation multiplexer 1313a and 1313b are divided into incoming bit stream will be mapped to the sub-bit stream of the real axis of constellation and the imaginary axis and export this sub-bit

stream.Symbol mapper

1315a and 1315b will be mapped to corresponding code element by the sub-bit stream behind demodulation multiplexer 1313a and the 1313b demultiplexing.

Characteristic that bit interleaver 1312a and 1312b and

demodulation multiplexer

1313a and 1313b can make up the LDPC code word and characteristic according to the constellation reliability of the symbol mapped of constellation.To introduce the embodiment of first

order demodulation multiplexer

1313a and 1313b after a while.

First order symbol mapper 1315a carries out first order symbol mapped, for example, and the high-order symbol mapped, and second level symbol mapper 1315b carries out second level symbol mapped, for example, the low order symbol mapped.First order symbol mapper 1315a will be mapped to code element from the sub-bit stream of first order demodulation multiplexer 1313a output, and second level symbol mapper 1315b will be mapped to code element from the sub-bit stream of second level demodulation multiplexer 1313b output.

Code element combiner 1317 will be merged into a code element stream by the code element of first order symbol mapper 1315a and second level symbol mapper 1315b mapping, and export this code element stream.

As mentioned above, in LDPC, the error correcting capability of bit may change according to the position of bit in error correction coding block.Therefore, if come control bit interleaver and demodulation multiplexer to change the order of the bit that constitutes the unit word, then can make the maximization of bit-level error correcting capability according to the characteristic of LDPC encoder 125.

Figure 19 is the figure that another execution mode of each

symbol mapper

131a and 131b is shown.Except also comprising first order calibration of power unit 1316a and calibration of power unit, second level 1316b, the execution mode of this figure is similar to the execution mode of Figure 18.

Code element combiner 1317 merges the code element of having been carried out calibration by calibration of

power unit

1316a and 1316b, and exports a code element stream.

Figure 20 is the figure that the notion that bit interleaver 1312a by Figure 18 and 19 and 1312b interweave to bit is shown.

For example, the memory that input bit is deposited in the matrix form of the row and column with predetermined quantity is also therefrom read.When the storage input bit, at first, with first row of this bit storage at line direction, and, if first row are filled, then bit storage is listed as at another according to line direction.When reading the bit of storage, read bit according to column direction, and if read the whole bits that are stored in first row, then read the bit of another row at column direction.In other words, when stored bits, stored bits is listed as thereby fill continuously line by line.And during the bit of storing when reading, walk to last column from first and read the bit of being stored by row continuously.In the figure, MSB represents highest significant position and LSB represents least significant bit.

In order to be mapped to the code element of the equal length of error correction block unit according to the bit of various code checks after with the LDPC error correction coding, bit interleaver 1312a and 1312b can change the quantity of the row and column of memory according to the type of

symbol mapper

1315a and 1315b.

Figure 21 illustrates another example of carrying out the bit interleaver that interweaves.If

bit interleaver

1312a and 1312b be with the unit's of classifying as stored bits, then they can be in each row stored bits as follows: the memory location of bit produces skew.If

bit interleaver

1312a and 1312b be with behavior unit's stored bits, then they can be in each row and the skew of the position of reading bit stored bits as many.

In the example of Figure 21, thick point is the position of representative skew respectively.For example, bit interleaver is with the unit's of classifying as stored bits.In first row, walk to n capable (n is the line number of memory) by the suitable order stored bits from first.In secondary series, to the capable stored bits of n, walk to the capable stored bits of r1-1 from first then from the aspersus row of tool (it is capable to be called as r1).In the 3rd row, aspersus r2 walks to the capable stored bits of n from tool, walks to the capable stored bits of r2-1 from first then.Like this, according to apart from of the cyclic addressing of this row at the as many row of skew of memory location, stored bits in each row.

If

bit interleaver

1312a and 1312b read the wherein bit of storage, then they read bit according to apart from the cyclic addressing of this position with the as many row of skew from each row.For example, in first row, bit interleaver reads the bit of storage by suitable order from first row to m row (m is the columns of memory).In second row, bit interleaver reads the bit of storage from the aspersus row of tool (being called as the C1 row) to m row, reads bit from first row to (C1-1) row then.In the third line, bit interleaver reads the bit of storage from the aspersus row of tool (being called as the C2 row) to m row, and reads bit according to the cyclic addressing of row from first row to (C2-1) row.

Figure 22 illustrates the skew of using in the Bit Interleave according to the symbol mapped method.NCol represents the columns of the memory of bit interleaver.If the symbol mapped method is QPSK, then the columns of memory can be two (2).Bit interleaver can use with secondary series Col2 in the corresponding skew of second row store and read bit.

If the symbol mapped method is 16QAM, then the columns of memory can be four (4).Bit interleaver can according to secondary series Col2 in second row, the 3rd row among the Col3 fourth line and the corresponding skew of the 7th row among the 4th row Col4, store and read bit.

If the symbol mapped method is 64QAM, then the columns of memory can be six (6).Bit interleaver can according to secondary series Col2 in second the row, the 3rd row Col3 in fifth line, the 4th row Col4 in the 9th the row, the 5th row Col5 in the tenth the row and the 6th row Col6 in the corresponding skew of the tenth triplex row, store and read bit.

If the symbol mapped method is 256QAM, then the columns of memory can be eight (8).Bit interleaver can according to the 3rd row Col3 in the corresponding skew of the 7th row among the 7th row and the 8th row Col8 among fifth line, the 7th row Col7 among fourth line, the 6th row Col6 among fourth line, the 5th row Col5 in second row, the 4th row Col4, store and read bit.

As mentioned above, the columns in the memory of bit interleaver changes according to the symbol mapped method, and bit be stored and be read to bit interleaver can by change skew according to columns.Can be identical according to included bit number in the code element of symbol mapped method with columns.Therefore, after reading bit, bit interleaver can be according to the mapping method of correspondence with a bit that symbol mapped read.In this case, the bit with symbol mapped can change order.Similarly, even reduced the error correcting capability of bit in the ad-hoc location,, therefore can maximize the error correcting capability of error correction code element method owing in bit interleaver, change order with the bit of symbol mapped according to error correction code element method.

Figure 23 illustrates when the LDPC pattern is general mode, according to the type of

symbol mapper

1315a and 1315b, and the figure of the example of the quantity of the row and column of the memory of bit interleaver 1312a and 1312b.

For example, if symbol mapper 1315a is mapped to the 256QAM code element with bit, then first order interleaver 1312a comes bit is interweaved with the memory with 8100 row and 8 row.If utilize 64QAM to shine upon code element, then first order interleaver 1312a comes bit is interweaved with the memory with 10800 row and 6 row.If utilize 16QAM to shine upon code element, then first order interleaver 1312a comes bit is interweaved with the memory with 16200 row and 4 row.

For example, if

symbol mapper

1315a and 1315b are mapped to the Hyb128-QAM code element with bit, then first order interleaver 1312a comes bit is interweaved with the memory with 4860 row and 8 row, and second level interleaver 1312b comes bit is interweaved with the memory with 4320 row and 6 row.

Similarly, if

symbol mapper

1315a and 1315b shine upon code element with Hyb32-QAM, then first order interleaver 1312a comes bit is interweaved with the memory with 6480 row and 6 row, and second level interleaver 1312b comes bit is interweaved with the memory with 6480 row and 4 row.

Figure 24 illustrates when the LDPC pattern is the weak point pattern, according to the type of

symbol mapper

For example, if symbol mapper 1315a is mapped to the 256QAM code element with bit, then first order interleaver 1312a comes bit is interweaved with the memory with 2025 row and 8 row.If

symbol mapper

1315a and 1315b utilize Hyb128-QAM to shine upon code element, then first order interleaver 1312a comes bit is interweaved with the memory with 1215 row and 8 row.And second level interleaver 1312b comes bit is interweaved with the memory with 1080 row and 6 row.

If carry out Bit Interleave, then can change the bit position in the error correction coding block at error correction coding block.

Figure 25 is the figure of notion that another execution mode that interweaves of bit interleaver is shown.In the execution mode shown in this figure, when in memory, writing bit, write bit according to column direction.When reading the bit that writes, read the bit of the position of cyclic shift according to the direction of going.In each row, the bit that each row is write carries out cyclic shift.If the row or column with respect to memory writes or read bit by cyclic shift, this is called the distortion Bit Interleave.This execution mode relates to distortion Bit Interleave method, and this method is used the method that reads these bits after line direction is with bit displacement one row.Substitute the displacement that writes bit in the memory, the point that reads the point of bit or write bit in memory in memory can be shifted.

In this embodiment, N represents the length of error correction coding block, and C represents the length that is listed as.When writing bit, according to 1,2,3,4 ... and the order of C writes bit at first row (using shadow representation), according to C+1, C+2, C+3 ... order write bit at secondary series.

The direction previous column that the bit that writes is expert at is distortion one by one with being listed as.

If read the bit that writes, then on line direction, read the bit of distortion.For example, in this embodiment, according to 1, C+1 ... order in first row, read bit, and according to X1,2, C+2 ... order in second row, read bit (X1 is the bit in first row of second row).Read bit line by line, and read the bit of cyclic shift.Certainly, substitute the displacement that writes bit in memory, can the point that be used for reading in the bit that memory writes be shifted.

Figure 26 is the figure that another execution mode of Bit Interleave is shown.In this embodiment, N represents the length of error correction coding block, and C represents the length that is listed as.When writing bit, according to 1,2,3,4 ..., the order of C-1 and C writes bit in first row, according to C+1, C+2, C+3 ... order in secondary series, write bit.

Be listed as the two distortions in ground by two on the direction that the bit that writes is expert at.If read the bit that writes, then at the bit that in each row, reads on the direction of row according to two row cyclic shifts.This method can be called two distortion Bit Interleave methods.

Figure 27 is the figure that another execution mode of Bit Interleave is shown.In this embodiment, N represents the length of error correction coding block, and C represents the length that is listed as.According to 1,2,3,4 ..., the order of C-1 and C writes bit in first row, and according to C+1, C+2, C+3 .... order in secondary series, write bit.

When reading the bit that writes, in the first area of being expert at, can read bit by distortion Bit Interleave method.

In the second area of being expert at, can read bit by two distortion deinterleaving methods.

In the 3rd zone of being expert at, can read bit by distortion Bit Interleave method.

If come interleaving bits by at least a in distortion Bit Interleave method and the two distortion deinterleaving methods, then can be blended in the bit in the error correction coding block more randomly.

Figure 28 is the figure that another execution mode of Bit Interleave is shown.As another execution mode of Bit Interleave, can carry out different Bit Interleaves with Parity Check Bits to the information bit after the error correction coding.

For example, handle in error correction coding (as, the LDPC error correction coding is handled) in, as Figure 21 with shown in Figure 22 information bit is carried out Bit Interleave.If write and read bit by each row, then can carry out Bit Interleave according to the skew that in each row, is used to write and read the initial position of bit for information bit.

In error correction coding is handled,, Parity Check Bits is carried out Bit Interleave according to the distortion scheme according at least one scheme in the scheme shown in Figure 25 to Figure 27.Parity Check Bits is write in each row, twist a plurality of row then.That is the bit that writes in the being expert at precalculated position that to be shifted.Read bit after the distortion along each row.The Parity Check Bits that writes can comprise the row zone of distortion and at least one in the didromic capable zone.

If Parity Check Bits is carried out Bit Interleave, then can improve the decoding performance of Parity Check Bits by said method.For example, the Parity Check Bits of the parity matrix that uses in handling such as the error correction coding of structurized LDPC can have the double-matrix form.But if the low Parity Check Bits of reliability is continuous in parity matrix, then the error correction decoding performance may descend.Therefore, if Parity Check Bits is carried out Bit Interleave, then can improve the error correction decoding performance by said method.

Now, with the execution mode of the encoding process that is described below, this decoding processing can be dealt with the ground floor information of transmission/reception and wrong situation appears at least one side in the second layer information.

Figure 29 illustrates the figure that the input bit of

demodulation multiplexer

1313a and 1313b is carried out multiplexing notion.

Bit interleaver

1312a and 1312b are to input bit X ₀, X ₁And X _N-1Interweave, and the bit of output after interweaving.Deinterleaving method is introduced in the above.

Demodulation multiplexer

1313a and 1313b carry out demultiplexing to the bit stream after interweaving.The method of demultiplexing can change according to the code check of error correction/encoding method and the symbol mapped method of symbol mapper.If the code element method of symbol mapper is QPSK, then input bit for example is woven into two son streams, and symbol mapper is mapped to code element with the real axis and the imaginary axis corresponding to constellation with these two sub-streams.For example, the first bit y0 of the first son stream of demultiplexing is corresponding to real axis, and the first bit y1 of the second son stream of demultiplexing is corresponding to the imaginary axis.

If the code element method of symbol mapper is 16QAM, then input bit for example is demultiplexed back into 4 son streams.Symbol mapper is selected the bit that comprises in 4 son streams, and selected bit is mapped to code element with the real axis and the imaginary axis corresponding to constellation.

For example, the bit y0 of the first and the 3rd son stream of demultiplexing and y2 are corresponding to real axis, and the bit y1 of the second and the 4th son stream of demultiplexing and y3 are corresponding to the imaginary axis.

Similarly, if the code element method of symbol mapper is 64QAM, then input bit is demultiplexed back into 6 son streams.Symbol mapper is mapped to code element with the real axis and the imaginary axis corresponding to constellation with these 6 sub-streams.For example, bit y0, the y2 of the first, the 3rd and the 5th son stream of demultiplexing and y4 are corresponding to real axis, and bit y1, the y3 of the second, the 4th and the 6th son stream of demultiplexing and y6 are corresponding to the imaginary axis.

Similarly, if the code element method of symbol mapper is 256QAM, then input bit is demultiplexed back into 8 son streams.Symbol mapper is mapped to code element with the real axis and the imaginary axis corresponding to constellation with these 8 sub-streams.For example, at first, bit y0, y2, y4 and the y6 of the first, the 3rd, the 5th and the 7th son stream of demultiplexing are corresponding to real axis, and bit y1, y3, y6 and the y7 of the second, the 4th, the 6th and the 8th son stream of demultiplexing are corresponding to the imaginary axis.

If symbol mapper mapping code element then is mapped to the real axis of constellation and the bit stream of the imaginary axis by the sub-stream behind the demodulation multiplexer demultiplexing.

Above-mentioned Bit Interleave method, Deplexing method and symbol mapped method are exemplary, the method for the whole bag of tricks as the bit in the chooser stream can be made by real axis and the imaginary axis of the stream of the son behind the demodulation multiplexer demultiplexing corresponding to constellation.

Be mapped to code element the unit word can any changes in the method for interweaving method, demultiplexing and the symbol mapped method according to coming according to code check to carry out to the bit stream error correction, to bit stream.Aspect the reliability of error correction decoding, the MSB of unit word is higher than the LSB of unit word.Though the reliability of the bit of the ad-hoc location of error correction coding block is lower,, if the bit of unit word is arranged on MSB or near MSB, then can handles the reliability that improves bit by symbol de-maps.

Therefore, though the reliability of the bit of encoding according to the characteristic of the H matrix of the error correction/encoding method that is used for irregular LDPC changes, but, can conciliate mapping by symbol mapped and handle robust ground transmission/reception bit, and the Adjustment System performance.

Figure 30 illustrates an execution mode that inlet flow is carried out demultiplexing by demodulation multiplexer.

If the symbol mapped method is QPSK, then two bits are mapped to a code element, and two bits of a symbol unit according to the order (

index

0 and 1 of b) of bit index by demultiplexing.

If the symbol mapped method is 16QAM, then 4 bits are mapped to a code element, and 4 bits of a symbol unit according to the result of calculation (

index

0,1,2 and 3 of b) of the mould 4 of bit index by demultiplexing.

If the symbol mapped method is 64QAM, then 6 bits are mapped to a code element, and 6 bits of a symbol unit according to the result of calculation (

index

0,1,2,3,4 and 5 of b) of the mould 6 of bit index by demultiplexing.

If the symbol mapped method is 256QAM, then 8 bits are mapped to a code element, and 8 bits of a symbol unit according to the result of calculation (

index

0,1,2,3,4,5,6 and 7 of b) of the mould 8 of bit index by demultiplexing.

The order of the demultiplexing of son stream is exemplary, and can revise.

Figure 31 is the example that illustrates according to the demultiplexing type of symbol mapped method.The symbol mapped method comprises QPSK, 16QAM, 64QAM and 256QAM, and the type of demultiplexing comprises the first kind to the six types.

The first kind be input bit sequentially corresponding to the even number index (0,2,4,8 ...) (the perhaps real axis of constellation) and sequentially corresponding to the odd number index (1,3,5,7 ...) example of (the perhaps imaginary part of constellation).Below, the bit demultiplexing of the first kind can use demultiplexing identifier 10 (position of

binary number

1010,1 is the position of the MSB corresponding with the real axis of constellation and the imaginary axis) to represent.

Second type is to carry out the example of demultiplexing according to the backward of the first kind, that is to say that the LSB of input bit is sequentially corresponding to even number index (6,4,2,0) (the perhaps real axis of constellation) and in the odd number index (1,3,5,7 ...) (the perhaps imaginary part of constellation).Below, the bit demultiplexing of second type can be represented (binary number 0101) with demultiplexing identifier 5.

The 3rd type is that input bit is arranged so that the bit at code word two ends is the example of MSB.Input bit reset with the two ends from code word begin to fill code word.Below, can represent the bit demultiplexing of the 3rd type with demultiplexing identifier 9 (binary one 001).

The 4th type is that input bit is arranged so that the intermediate bit of code word becomes the example of MSB.At first, a bit of input bit is filled into the centre position of code word, then,, the two ends of remaining bits towards code word is rearranged according to the order of input bit.Below, can represent the bit demultiplexing of the 4th type with demultiplexing identifier 6 (Binary Zero 110).

The 5th type is that the bit deinterleaving is made that last bit of code word is MSB, and first bit of code word is the example of LSB.And the 6th type is that bit rearrangement is made that first bit of code word is MSB, and the example that its last bit is LSB.Below, represent the bit deinterleaving of the 5th type with demultiplexing identifier 3 (Binary Zero 011), and represent the bit deinterleaving of the 6th type with demultiplexing identifier 12 (binary one 100).

As mentioned above, the type of demultiplexing can change according to the code check of symbol mapped method or error correction/encoding method.That is to say,, then can use different multiplexing types if symbol mapped method or code check change.

Figure 32 illustrates the figure that incoming bit stream is carried out an execution mode of demultiplexing according to the demultiplexing type.This execution mode can comprise bit interleaver 1312a and 1312b,

demodulation multiplexer

1313b and 1313b and

mapper

1315a and 1315b.

Bit interleaver 1312a and the 1312b PLP Business Stream after to error correction coding interweaves.For example, bit interleaver 1312a and 1312b can carry out Bit Interleave according to error correction coding unit according to the pattern of error correction coding.The method of Bit Interleave is introduced in the above.

Demultiplexing

1313a and 1313b can comprise first kind demodulation multiplexer 1313a1 and 1313b1, n type demodulation multiplexer 1313a2 and 1313b2.Here, n is an integer.Method by n kind demodulation multiplexer demultiplexing bit is followed type shown in Figure 17.For example, first kind demodulation multiplexer can be corresponding to first kind bit demultiplexing (1100), and the second class demodulation multiplexer (not shown) can be corresponding to the second analogy particular solution multiplexing (0011).N class demultiplexing 1313b comes incoming bit stream is carried out demultiplexing according to n class bit multiplexing (for example, demultiplexing identifier 1100), and the bit stream behind the output demultiplexing.Selector 1313a3 and 1313b3 receive the demodulation multiplexer of the demultiplexing type that is suitable for input bit and select signal, and select bit stream after signal is exported demultiplexing according to any one and demodulation multiplexer in the first kind to the n type.Demodulation multiplexer selects signal to change according to the code check of error correction coding and the symbol mapped method of constellation.Correspondingly, can determine the demultiplexing type according to the code check of error correction/encoding method and/or the symbol mapped method of constellation.To introduce according to the code element that is mapped to constellation after a while and/or select the concrete example of code check of the error correction coding of signal according to demodulation multiplexer.

Sub-stream after mapper 1315a and 1315b can select signal with demultiplexing according to demultiplexing is mapped to code element, and exports the code element of being shone upon.

Figure 33 is the figure that the demultiplexing type of determining according to the code check and the symbol mapped method of error correction coding is shown.

In 4QAM symbol mapped method, even the code check cr of LDPC error correction/encoding method is in 1/4,1/3,2/5,1/2,3/5,2/3,3/4,4/5,5/6,8/9 and 9/10 any, also can come bit stream is carried out demultiplexing (representing with " all ") according to whole demultiplexing types.

In 16QAM symbol mapped method,, then code element can be shone upon and need not to carry out Bit Interleave and bit demultiplexing (representing) by " not interweaving " and " not demultiplexing " if the code check of LDPC error correction/encoding method is 1/4,1/3,2/5 and 1/2.If the code check of error correction coding is 3/5, then can come bit is carried out demultiplexing according in

demultiplexing identifier

9,10 and 12 any.If the code check of error correction/encoding method is 2/3,3/4,4/5,5/6,8/9 and 9/10, then can come incoming bit stream is carried out demultiplexing according to demultiplexing identifier 6.

In 64QAM symbol mapped method,, then code element can be shone upon and need not to carry out Bit Interleave and bit demultiplexing if the code check of LDPC error correction/encoding method is 1/4,1/3,2/5 and 1/2.If code check is 3/5, then can come bit is carried out demultiplexing according in

demultiplexing identifier

9 and 10 any.If code check is 2/3,3/4,4/5,5/6,8/9 and 9/10, then can come bit is carried out demultiplexing according to demultiplexing identifier 6.

In 256QAM symbol mapped method,, then code element can be shone upon and need not to carry out Bit Interleave and bit deinterleaving if the code check of LDPC error correction/encoding method is 1/4,1/3,2/5 and 1/2.If code check is 3/5, then can come bit is carried out demultiplexing according to demultiplexing identifier 9.If code check is 2/3,3/4,4/5,5/6,8/9 and 9/10, then can come input bit is carried out demultiplexing according to demultiplexing identifier 6.

As mentioned above, bit demultiplexing type can change according to code check that is used for error correction coding and symbol mapped method.Therefore, can be positioned at the error correcting capability of bit of the ad-hoc location of error correction coding block by the sub-stream behind the demultiplexing being mapped to code element adjustment.Correspondingly, can make the robustness optimization according to bit-level.

Figure 34 illustrates the figure that represents the example of Deplexing method with equation.For example, if the symbol mapped method is QPSK, input bit then

Corresponding to bit y0 and the y1 behind the demultiplexing.If the symbol mapped method is 16QAM, then input bit

Corresponding to bit y0, y1, y2 and the y3 behind the demultiplexing.

If the symbol mapped method is 64QAM, then input bit Corresponding to bit y0, y1, y2, y3, y4 and the y5 behind the demultiplexing.If the symbol mapped method is 256QAM, then input bit Corresponding to bit y0, y1, y2, y3, y4, y5, y6 and the y7 behind the demultiplexing.

Here, N represents at the input of bit interleaver and is mapped to the amount of bits of code element.

Figure 35 is the figure that illustrates by the example of symbol mapper mapping code element.For example, in QPSK symbol mapped method, the value of the value of the bit y0 of first after of the code element on constellation stream and the bit y1 of the second son stream behind the demultiplexing corresponding to demultiplexing.

In 16QAM, the bit of the bit of the real axis of the code element on the constellation the first and the 3rd after stream (be separated by 0 and 2 bit of the position of MSB), its imaginary axis the second and the 4th son stream after corresponding to demultiplexing (be separated by 1 and 3 bit of the position of MSB) corresponding to demultiplexing.

In 64QAM, the bit of the bit of the real axis of the code element on the constellation the first, the 3rd and the 5th after stream (be separated by 0,2 and 4 bit of the position of MSB), the imaginary axis of the code element on the constellation the second, the 4th and the 6th son stream after corresponding to demultiplexing (be separated by 1,3 and 5 bit of the position of MSB) corresponding to demultiplexing.

Therefore, the bit that can will constitute code element according to the order of demultiplexing is mapped to the unit word.If the bit that constitutes the unit word is by demultiplexing, then the MSB of unit word and LSB are changed, though and the reliability of LDPC error correction coding bit change according to the position, can adjust the robustness of bit.

Figure 36 is an illustration according to the block diagram of the MIMO/MISO encoder of embodiment of the present invention.The MIMO/MISO encoder utilizes the MIMO/MISO encoding scheme that the input data are encoded, and the data after will encoding output to a plurality of paths.If signal receiving end receives the signal that will send to a plurality of paths from one or more path, then it can obtain gain (being also referred to as diversity gain, payload gain or spatial multiplexing gain).

140 pairs of business datums from each path that frame constructor 130 generates of MIMO/MISO encoder are encoded, and the corresponding A of an antenna amount path is exported to and exported to the data after will encoding.

Figure 37 is an illustration according to the block diagram of the modulator of embodiment of the present invention.Modulator comprises first power controller (PAPR reduces by 1) 151, spatial transform unit (IFFT) 153, second power controller (PAPR reduces by 2) 157 and protection inserter 159 at interval.

First power controller 151 is reduced in PAPR (the Peak-to-Average Power Ratio: peak-to-average power ratio) of the data that send to R signal path in the frequency domain.

Spatial transform (IFFT) unit 153 converts the frequency-region signal that receives to time-domain signal.For example, can convert frequency-region signal to time-domain signal according to the IFFT algorithm.Therefore, can modulate frequency domain data according to the OFDM scheme.

Second power controller (PAPR reduces by 2) 157 has reduced the PAPR (peak-to-average power ratio) of the channel data that sends to R signal path in time domain.In this case, can use carrier wave to reserve (tone reservation) scheme and dynamic constellation extension (the ACE:active constellation extension) scheme that is used to expand symbol constellations.

Protection inserter 159 at interval will be protected the OFDM code element that is inserted into output at interval, and the result after the output insertion.As mentioned above, can in each signal in R path, carry out above-mentioned execution mode.

Figure 38 is an illustration according to the block diagram of the analog processor 160 of embodiment of the present invention.Analog processor 160 comprises digital to analog converter (DAC) 161, up-conversion unit 163 and analog filter 165.

DAC 161 will import data transaction and become analog signal, and export this analog signal.Up-conversion unit 163 is transformed into the RF zone with the frequency domain of analog signal.165 pairs of RF band signals of analog filter carry out filtering, and export filtered RF signal.

Figure 39 is an illustration according to the block diagram of the device that is used for received signal of embodiment of the present invention.Signal receiving device comprises the first signal receiver 210a, n signal receiver 210n, the first demodulator 220a, n demodulator 220n, MIMO/MISO decoder 230, frame parser 240 and decoding demodulator 250 and output processor 260.

Under situation, a plurality of service integrations in R channel, then, are carried out time shift, thus the result after the transmitting time displacement according to the received signal of TFS signal frame structure.

This receiver can comprise that at least one is used to be received in the signal receiver of the business that sends at least one RF channel.Can send to mulitpath via the TFS signal frame that A antenna will send to the individual RF channel of R (wherein, R is a natural number).This A antenna is used for R RF channel, so the antenna sum is R * A.

The business datum that the first signal receiver 210a can receive in the middle of the whole service data that send via a plurality of RF channels, send via at least one path.For example, the first signal receiver 210a can receive the transmission signal that utilizes the MIMO/MISO scheme to handle by a plurality of paths.

The first signal receiver 210a and n signal receiver 210 can receive a plurality of Service Data Units that n RF channel in the middle of a plurality of RF channels send as single PLP.That is, this execution mode illustrates the signal receiving device that can receive the data of R RF channel simultaneously.Therefore, if this execution mode receives single RF channel, then only need the first receiver 210a.

The first demodulator 220a and n demodulator 220n carry out demodulation according to the OFDM scheme to the signal that receives among the first signal receiver 210a and the n signal receiver 210n, and the signal after the output demodulation.

MIMO/MISO decoder 230 is decoded to the business datum that receives by a plurality of transmit paths according to the MIMO/MISO decoding scheme, and decoded business datum is outputed on the single transmit path.If receive on a plurality of transmit paths, send R professional, then MIMO/MISO decoder 230 can export with the corresponding R of the quantity of a R channel business in each business in the single PLP business datum that comprises.If by R RF channel sent P professional, and received the signal of each RF channel by A antenna, then (R * A) individual reception antenna is decoded to this P business altogether in the receiver utilization.

240 pairs of frame parsers comprise that the TFS signal frame of a plurality of business resolves, and the business datum of output after resolving.

The business datum that comprises in the frame after 250 pairs of parsings of decoding demodulator is carried out error correction decoding, decoded symbol data is separated be mapped to Bit data, and the result after mapping is handled is separated in output.

260 pairs of output processors comprise that the stream of separating the Bit data after the mapping decodes, and the stream behind the output decoder.

In the above description, each in frame parser 240, decoding demodulator 250 and the output processor 260 all receives a plurality of Service Data Units the same with the quantity of PLP, and received business datum is carried out signal processing.

Figure 40 is an illustration according to the block diagram of the signal receiver of embodiment of the present invention.Signal receiver can comprise tuner (tuner) 211, low-converter 213 and analog to digital converter (ADC) 215.

When comprising PLP in a plurality of RF channels, some the RF channels that can send user-selected business in 211 pairs of whole RF channels of tuner are carried out frequency hopping, and output frequency hopping result.Tuner 211 is carried out the frequency hopping of the RF channel that comprises in the TFS signal frame according to the RF centre frequency of input, and simultaneously the corresponding frequencies signal is carried out tuning, the signal after making this tuner output tuning.If signal is sent to A bar multipath, then tuner 211 is carried out the tuning of corresponding RF channels, and receives received signal by this A antenna.

213 pairs of low-converters are carried out down-conversion by the RF frequency of the tuning signal of tuner 211, and the result of output down-conversion.ADC 215 becomes digital signal with analog signal conversion.

Figure 41 is an illustration according to the block diagram of the demodulator of embodiment of the present invention.Demodulator comprises frame detector 221, frame synchronization unit 222, protection interval removal 223, frequency-domain transform unit (FFT) 224, channel estimator 225, channel equalizer 226 and signaling information extractor 227.

If demodulator obtains to send to the business datum of single PLP stream, then will carry out signal demodulation subsequently.Below its detailed description will be described.

The transfer system of frame detector 221 identification received signals.For example, frame detector 221 judges whether received signal is the DVB-TS signal.And frame detector 221 can also judge whether received signal is the TFS signal frame.It is synchronous that frame synchronization unit 222 obtains the time domain and the frequency domain of TFS signal frame.

Protection interval controller 223 from time domain remove between the OFDM code element protection at interval.Frequency domain transform device (FFT) 224 utilizes fft algorithm to convert received signal to frequency-region signal, thereby can obtain the frequency domain symbols data.

Channel estimator 225 utilizes the pilot frequency code element that comprises in the symbol data of frequency domain that receive channel is carried out channel estimating.Channel equalizer 226 utilizes by channel estimator 225 estimated channel information butt joint and receives data execution channel equalization.

Signaling information extractor 227 can be extracted in signaling information that set up, physical layer in first pilot signal and second pilot signal, and described first pilot signal and second pilot signal are included in the reception data after the channel equalization.

Figure 42 is an illustration according to the block diagram of the MIMO/MISO decoder of embodiment of the present invention.Signal receiver and demodulator are designed to handle the signal that receives in single path.If signal receiver and demodulator receive via a plurality of paths of a plurality of antennas the PLP of single business are provided business datum, and this PLP business datum of demodulation, then MIMO/MISO decoder 230 signal that will receive in mulitpath is output as the business datum that sends to single PLP.Therefore, obtain diversity gain and spatial multiplexing gain in the business datum that MIMO/MISO decoder 230 can receive from corresponding PLP.

MIMO/MISO decoder 230 receives multipaths from a plurality of antennas and sends signals, and can utilize and can decode to signal with the MIMO scheme that the form of individual signals is recovered each received signal.In addition, MIMO/MISO decoder 230 can utilize from the MIMO scheme that individual antenna receives that multipath sends signal and the multipath that recovers to be received sends signal and come restoring signal.

Therefore, if send signal by the individual RF channel of R (R is a natural number), then MIMO/MISO decoder 230 signal that can receive A antenna by each RF channel is decoded.If the value of A equals " 1 ", then can decode to signal by the MISO scheme.If the value of A greater than " 1 ", then can be decoded to signal by the MIMO scheme.

Figure 43 is an illustration according to the block diagram of the frame parser of embodiment of the present invention.Frame parser comprises first frequency deinterleaver 241a, r frequency deinterleaver 241r, frame parser 243, very first time deinterleaver 245a, p time de-interweaving device 245p, the first symbol de-maps device 247a and p symbol de-maps device.The value of " r " can be decided by the quantity of RF channel, and the value of p can decide by the quantity of transmission by the stream of the PLP business datum of frame parser 243 generations.

Therefore, if send p business to p PLP stream on R RF channel, then frame parser comprises r frequency deinterleaver, a p time de-interweaving device and p symbol de-maps device.

Be associated with a RF channel, first frequency deinterleaver 241a carries out deinterleaving to frequency domain input data, and output deinterleaving result.

Frame parser 243 utilizes the schedule information of TFS signal frame that the TFS signal frame that sends to a plurality of RF channels is resolved, and the PLP business datum that comprises in the time slot that comprises the specific RF channel that expectation is professional is resolved.Frame parser 243 is resolved the TFS signal frame according to the TFS signal frame structure, is distributed to particular traffic data on a plurality of RF channels with reception, and exports the first path PLP business datum.

Very first time deinterleaver 245a carries out deinterleaving to the first path PLP business datum after resolving in time domain.The business datum that the first symbol de-maps device 247a determines to be mapped to code element is a Bit data, makes it can export the PLP stream that is associated with the first path PLP business datum.

Suppose that symbol data is converted into Bit data, and each symbol data comprises based on the code element of mixing the code element mapping scheme, and p symbol de-maps device (wherein each all comprises the first symbol de-maps device) can utilize different symbol de-maps schemes at interval symbol data to be defined as Bit data according to each of input symbols data.

Figure 44 is the figure that the execution mode of each

symbol de-maps device

247a and 247p is shown.The symbol de-maps device is from receiving the stream corresponding with PLP respectively with symbol de-maps device time corresponding interleaver 245a and the 245p.

Each

symbol de-maps device

247a and 247p can comprise error correction block splitter 2471, code element splitter 2473, first order de-mapping device 2475a, second level de-mapping device 2475b and bit stream combiner 2478.

Error correction block splitter 2471 can split the PLP stream that receives among from time-interleaved

device

245a and 245p corresponding one by error correction block unit.Error correction block splitter 2471 can split Business Stream by general mode LDPC block unit.In this case, can will be used as according to the state of the error correction block of a piece of general mode (block length is 64800 bits) fractionation Business Stream down according to 4 pieces of short pattern (block length is 16200 bits).

Code element splitter 2473 can split the code element stream that splits in the error correction block according to the symbol mapped method of code element stream.

For example, first order de-mapping device 2475a can become bit with the symbol mapped according to high-order symbol mapped method.Second level de-mapping device 2475b can become bit with the symbol mapped according to low order symbol mapped method.

Bit stream combiner 2478 can receive the bit after the conversion and export a bit stream.

Figure 45 is the figure that another execution mode of each

symbol de-maps device

247a and 247p is shown.Except also comprising first order calibration of power unit 2474a and calibration of power unit, second level 2474b, the execution mode of this figure is similar to the execution mode of Figure 44.

First order calibration of power unit 2474a receives the code element that is split out by code element splitter 2473, the power of the code element that calibration is received according to the symbol mapped scheme, and the code element after the output calibration.The power of institute's receiving symbol can have the power of calibrating according to constellation size based on the symbol mapped method.First order calibration of power unit 2474a changes the power of calibration according to the raw symbol power of constellation.First order de-mapping device 2475a can with by the first order calibration of power sing1e unit calibration symbol de-maps of power be bit.

Similarly, calibration of power unit, second level 2474b receives the code element that is split out by code element splitter 2473, according to the size of constellation the calibration power of the code element that receives is revised as original power, and the code element behind the output modifications.

Figure 46 is the figure that another execution mode of each

symbol de-maps device

247a and 247p is shown.Each

symbol de-maps device

247a and 247p can comprise code element splitter 2473, first order de-mapping device 2474a, second level de-mapping device 2474b, first order multiplexer 2475a, second level multiplexer 2475b, first order bit deinterleaver 2476a, second level bit deinterleaver 2476b and bit stream combiner 2478.By this execution mode, the decoding of Figure 36 and the execution mode of demodulating unit comprise first decoder 253, first deinterleaver 255 and second decoder 257.

Code element splitter 2473 can split the code element stream of PLP according to the method corresponding with the symbol mapped method.

Code element stream after first order de-mapping device 2474a and second level de-mapping device 2474b will split converts bit to.For example, first order de-mapping device 2474a carries out the symbol de-maps of high-order QAM, and second level de-mapping device 2474b carries out the symbol de-maps of low order QAM.For example, first order de-mapping device 2474a can carry out the symbol de-maps of 256QAM, and second level de-mapping device 2474b can carry out the symbol de-maps of 64QAM.

First order multiplexer 2475a and second level multiplexer 2475b carry out multiplexing to the bit through symbol mapped.The method of the demultiplexing that multiplexing method can be introduced corresponding to reference Figure 15 to Figure 18.Therefore, can change the son circulation of demultiplexing into a bit stream.

First order bit deinterleaver 2476a is to carrying out deinterleaving by the multiplexing bit stream of first order multiplexer 2475a.Second level bit deinterleaver 2476b is to carrying out deinterleaving by the multiplexing bit stream of first order multiplexer 2475a.The method of deinterleaving is corresponding to the Bit Interleave method.Bit Interleave method shown in Figure 12.

Bit stream combiner 2478 can will be merged into a bit stream by the bit stream after bit interleaver 2476a and the 2476b deinterleaving.

The decoding and first decoder 253 of demodulating unit can come the bit stream of exporting is carried out error correction decoding according to general mode or short pattern and according to the code check of these patterns.

Figure 47 is the figure that another execution mode of each

symbol de-maps device

247a and 247p is shown.Except also comprising first order calibration of power unit 2474a and calibration of power unit, second level 2474b, the execution mode of this figure is similar to the execution mode of Figure 46.First order calibration of power unit 2474a and calibration of power unit, second level 2474b are according to the calibration power of symbol mapped method modification code element, and the code element behind

symbol de-maps device

2475a and 2475b output modifications.

Figure 48 illustrates the figure that the sub-stream behind the demultiplexing is carried out a multiplexing execution mode.In this execution mode,

de-mapping device

2474a and 2474b determine to comprise the unit word of

bit.Multiplexer

2475a and 2475b select signal to carry out the unit word of determining multiplexing according to multiplexer.Unit word behind the demultiplexing is transfused to any one among the first multiplexer 2475a2 and 2475b2 to the n multiplexer 2475a3 to 2475b3.

The first multiplexer 2475a2 and 2475b2 to the n multiplexer 2475a3 to 2475b3 select signal to change the order of the bit in the unit word according to multiplexer.Multiplexer selects signal to change according to the code check or the symbol mapped method of error correction coding.In order to generate send multiplexer to one stream and bit stream, the order of the son stream of selection can select signal to change according to multiplexer.

Bit stream after the first demodulation multiplexer 2475a1 and 2475b1 select signal with symbol de-maps according to multiplexer is exported to any one among the first multiplexer 2475a2 and 2475b2 to the n multiplexer 2475a3 to 2475b3.The first demodulation multiplexer 2475a1 and 2475b1 can receive by the first multiplexer 2475a2 and the multiplexing son stream of 2475b2 to the n multiplexer 2475a3 to 2475b3, and select signal to export a stream according to multiplexer.

To comprise the unit word input bit interleaver 2476a and the 2476b of the bit after the change, bit deinterleaver 2476a and 2476b carry out deinterleaving to input bit, and the bit after the output deinterleaving.

Figure 49 is an illustration according to the block diagram of the decoding demodulator of embodiment of the present invention.The decoding demodulator can comprise and coding and the corresponding a plurality of functional blocks of modulating unit.In the present embodiment, the decoding demodulator of Figure 16 can comprise first deinterleaver 251, first decoder 253, second deinterleaver 255 and second decoder 257.Second deinterleaver 255 can optionally be included in the decoding demodulator.

First deinterleaver 251 is used as inner deinterleaver, and can carry out deinterleaving to p the PLP stream that frame parser generates.

First decoder 253 can be carried out error correction to the data after the deinterleaving as inner decoder, and can use the error correction decoding algorithm based on the LDPC scheme.

Second deinterleaver 255 is used as outer deinterleaver, and can carry out deinterleaving to the data behind the error correction decoding.

Second decoder 257 is as outer decoder.To through 255 deinterleavings of second deinterleaver or carry out error correction once more through the data of first decoder, 253 error correction, make second decoder 257 export the data after the error correction once more.Second decoder 257 utilizes the error correction decoding algorithm that data are decoded based on the BCH scheme, makes data behind this second decoder output decoder.

First deinterleaver 251 and second deinterleaver 255 can convert the burst error that produces in the data that comprise in the PLP stream to random error.First decoder 253 and second decoder 257 can be corrected the mistake that comprises in the data.

The decoding demodulator illustrates and the relevant operational processes of single PLP stream.If there is p stream, then need p decoding demodulator, the demodulator of perhaps decoding can be repeatedly to input data decode p time.

Figure 50 is an illustration according to the block diagram of the output processor of embodiment of the present invention.Output processor can comprise p base band (BB) frame parser (251a ..., 261p), the first service combining device 263a, the second service combining device 263b, the first demodulation multiplexer 265a and the second demodulation multiplexer 265b.

The BB frame parser (261a ..., 261p) from first to p PLP stream, remove BB frame header according to received PLP path, and the result after the output removal.This execution mode illustrates business datum is sent at least two streams.First-class is MPEG-2 TS stream, and second stream is GS stream.

The first service combining device 263a calculates the summation of the business datum that comprises in the payload of at least one BB frame, thereby the summation of this business datum is exported as single Business Stream.The first demodulation multiplexer 255a can carry out demultiplexing to this Business Stream, and the result behind the output demultiplexing.

Like this, the second service combining device 263b calculates the summation of the business datum that comprises in the payload of at least one BB frame, thereby this second service combining device can be exported another Business Stream.The second demodulation multiplexer 255b can carry out demultiplexing to GS form Business Stream, and the Business Stream behind the output demultiplexing.

Figure 51 is an illustration according to another implementation of the invention the block diagram of device that is used to send signal.Sender unit comprises professional synthesizer 310, frequency divider 320 and transmitter 400.400 pairs in transmitter comprises that the signal of the Business Stream that will send to each RF frequency band encodes or modulate.

Professional synthesizer 310 receives a plurality of Business Streams, a plurality of Business Streams that send to each RF channel is carried out multiplexing, and exports Business Stream after multiplexing.When transmitter 400 sent PLP via a plurality of RF channels, professional synthesizer 310 output scheduling information made it possible to utilize this schedule information to control transmitter 400.By this schedule information, 310 pairs of professional synthesizers will be modulated by a plurality of traffic frames that transmitter 400 sends to a plurality of RF channels, and send the traffic frame after the modulation.

Frequency divider 320 receives the Business Stream that will send to each RF frequency band, and each Business Stream is split into a plurality of son streams, and making can be to the independent RF frequency band of this a little flow distribution.

400 pairs of Business Streams that will send to each frequency band of transmitter are handled, and the stream that obtains after the output processing.For example, with the given traffic streams that will send to a RF channel explicitly, first mapper 410 with the input Business Stream be mapped to code element.420 pairs of code elements of being shone upon of first interleaver interweave, to prevent burst error.

The signal frame that first symbol inserter 430 will have a pilot signal (for example discrete guide-frequency signal or continuous pilot signal) inserts in the signal after the modulation.

First modulator 440 is modulated the data after interweaving according to signal modulation scheme.For example, first modulator 440 can utilize the OFDM scheme that signal is modulated.

The first pilot frequency code element inserter 450 is inserted in first pilot signal and second pilot signal in the signal frame, and can send the TFS signal frame.

Send to the TFS signal frame via a plurality of 415,425,435 of the different paths shown in the transmitter of Figure 18,445 and 455 traffic data that will send to the 2nd RF channel.

The quantity of the signal processing path that sends from transmitter 400 can equal the quantity of the RF channel that comprises the TFS signal frame.

First mapper 410 and second mapper can comprise demodulation multiplexer 1313a and 1313b respectively, and allow to change in symbol mapped unit word the position of MSB and LSB.

Figure 52 has been the illustration block diagram of the device that is used for received signal according to another implementation of the invention.Signal receiving device can comprise receiving element 510, lock unit 520, mode detector 530, equalizer 540, parametric detector 550, deinterleaver 560, de-mapping device 570 and professional decoder 580.

The signal of a RF channel of selecting by the user in the middle of the receiving element 500 energy received signal frames.If signal frame comprises a plurality of RF channels, then 500 pairs of a plurality of RF channels of receiving element are carried out frequency hopping, and can receive the signal that comprises selected traffic frame simultaneously.

Lock unit 510 obtains the synchronous of received signal, and the received signal after the output synchronously.Demodulator 520 can carry out demodulation to the signal after obtaining synchronously.Mode detector 530 can utilize first pilot signal of signal frame to obtain the FFT pattern of second pilot signal (for example, 2k, 4k, 8k FFT computing length).

Demodulator 520 carries out demodulation to received signal under the FFT of second pilot signal pattern.Equalizer 540 is carried out channel estimating to received signal, and delivery channel is estimated the signal obtain.Received signal after 560 pairs of channel equalizations of deinterleaver is carried out deinterleaving.(for example, QAM) Dui Ying symbol de-maps scheme is separated mapping to the code element after interweaving to symbol mapped scheme when de-mapping device 570 utilizes with the transmission signal.

Parametric detector 550 obtains the physical parameter information (for example, ground floor (L1) information) that comprises in second pilot signal from the output signal of equalizer 540, and the physical parameter information of being obtained is sent to receiving element 500 and lock unit 510.It is another channel with the RF channel-changing that receiving element 500 can utilize by the parametric detector 550 detected network informations.

Parametric detector 550 output and the professional information that is associated, professional decoder 580 is decoded according to the business datum from the information butt joint that is associated with the business collection of letters of parametric detector No. 550, and the business datum behind the output decoder.

De-mapping device 570 can comprise multiplexer 2475a and 2475b, and exports the bit stream that obtains by the order of recovering following bit, and MSB in the order of described bit and the position of LSB change according to the code check and the symbol mapped method of error correction coding.

The method and apparatus of first pilot signal after below using description to the method that first pilot signal of signal frame with at least one RF frequency band is modulated and being used to receive modulation.

Via the PLP code element after the zone of division comes transmitting time to interweave in time in signal frame.If there are a plurality of RF frequency bands, the PLP code element after then can coming transmitting time to interweave via the zone of in frequency domain, dividing.Therefore, if send or reception PLP, then can obtain diversity gain.Error correction mode and symbol mapped method can change according to the business corresponding to transport stream, perhaps can change in business.

First pilot signal and second pilot signal are arranged on the initial position that has such as the signal frame of the characteristic of preamble signal.

As mentioned above, first pilot signal that comprises in signal frame can comprise following identifier: this identifier is used to discern the signal frame with said structure.First pilot signal can comprise: the information of the transmission structure that whether sends via multipath about the expression signal frame and about the information of the FFT pattern of the signal after first pilot signal.Receiver can be from first pilot signal detection signal frame, and obtain the information estimated about whole carrier frequency shift and about the information of the FFT pattern of data symbols.

Figure 53 is the figure of execution mode that the structure of first pilot signal is shown.The part of being represented by A is the live part of first pilot signal.B is illustrated in Cyclic Prefix identical with the first of part A in the time domain, and C is illustrated in cyclic suffix identical with the second portion of part A in the time domain.First can be that the latter half from part A duplicates, and second portion can duplicate from the first half of part A.

By duplicating first and second portion and the part of duplicating being carried out frequency displacement, can obtain B and C respectively.Relation between B or C and the A is as follows:

[equation 1]

In above-mentioned equation, SH represents the skew unit of frequency displacement.Therefore, the frequency shift value of part B and C can be inversely proportional to the length of part B and C.

If constitute first pilot signal by Cyclic Prefix (B) and cyclic suffix (C) are carried out frequency displacement, so, although constituting the data symbols of PLP modulates according to identical FFT pattern with the code element that constitutes lead code, with the data symbols error detection is that the probability of lead code is very low, and has reduced the probability of error detection lead code.

If comprise continuous wave (CW) interference as analog tv signal, then the probability of error detection lead code reduces owing to the noise DC component that produces in association process.In addition, if the size of FFT that puts on the data symbols that constitutes PLP is greater than the size of the FFT that puts on lead code, so, even be equal to or greater than in the delay spreading channel of length of effective code element part A of lead code, also can improve the preamble detection performance in length.Owing in lead code, use Cyclic Prefix (B) and cyclic suffix (C), so can estimate the decimal carrier frequency shift by association process.

Figure 54 illustrates the figure that detects the preamble signal shown in Figure 53 and estimate the execution mode of timing slip and frequency shift (FS).This execution mode can be included in frame detector 221 or the frame synchronization unit 222.

This execution mode can comprise first delay cell 601, complex conjugate computing unit 603, first multiplier 605, second multiplier 607, first filter 611, second delay cell 615, the 3rd multiplier 609, second filter 613, the 4th multiplier 617, peak search unit 619 and phase measurement unit 621.

First delay cell 601 can postpone the signal that received.For example, first delay cell 601 can be with the length of the effective code element part (A) of signal delay first pilot signal that received.

The complex conjugate of first pilot signal of complex conjugate computing unit 603 after can computing relay, and the signal that calculated of output.

First multiplier 605 can be with the signal and the signal multiplication that is received from complex conjugate computing unit 603 output, and the signal that obtains of output multiplication.

Because first pilot signal comprises by live part A being carried out part B and the C that frequency displacement obtains, so by the corresponding frequency shift amount of the signal bias that is received being obtained relating value separately.In first pilot signal, part B be from part A to upshift or to the part of downshift, and C is to upshift or to the part of downshift from part A.

For example, if use the output of complex conjugate computing unit 603, then the output of first multiplier 605 can comprise the association results of B (or complex conjugate of B) and A (or complex conjugate of A).

Second multiplier 607 can with from the signal times of first multiplier 605 output with the frequency shift amount that puts on part B (with ej ^FSHT represents), and the signal that obtains of output multiplication.

611 pairs of signals from 607 outputs of second multiplier of first filter are carried out rolling average in predetermined periods.The rolling average part can be the length of Cyclic Prefix (B) or the length of cyclic suffix (C).In this embodiment, first filter 611 can calculate the mean value of the signal that comprises in the length of part B.Then, from the result of first filter, 611 outputs, part A that comprises in the part of having calculated mean value and the relating value of C roughly become 0, and the association results of part B and A keeps.Since second multiplier 607 with the signal times of part B with frequency offseting value, so it equals the signal that obtains by the latter half that duplicates part A.

The 3rd multiplier 609 can with from the signal times of first multiplier 605 output with the frequency shift amount that puts on portion C (representing) with-ejfSHt, and the signal that obtains of output multiplication.

613 pairs of signals from 609 outputs of the 3rd multiplier of second filter are carried out rolling average in predetermined periods.The rolling average part can be the length of Cyclic Prefix (B) or the length of cyclic suffix (C).In this embodiment, second filter 613 can calculate the mean value of the signal in the length that is included in portion C.Then, from the result of second filter, 613 outputs, part A that comprises in the part of having calculated mean value and the relating value of B roughly become 0, and the association results of portion C and A keeps.Since the 3rd multiplier 609 with the signal times of portion C with frequency offseting value, so it equals the signal that obtains by the first half that duplicates part A.

The length T B that carries out the part of rolling average by first filter 611 and second filter 613 is expressed as follows.

[equation 2]

T _B＝k/f _SH

Wherein k represents integer.In other words, the f of unit of the frequency displacement of in part B and C, using _SHCan determine by k/TB.

Second delay cell 615 can postpone from the signal of first filter, 611 outputs.For example, second delay cell 615 will be by the length of the signal delay part B of first filter, 611 filtering, and the signal of output delay.

Signal times after the 4th multiplier 617 will be postponed by second delay cell 615 is with by second filter, 613 filtered signals, and the signal that obtains of output multiplication.

Peak search unit 619 is being searched for the position that produces peak value from the multiplying signal of the 4th filter 617 outputs, and exports the position that searches to phase measurement unit 621.Peak value and position can be used for timing slip and estimate.

Phase measurement unit 621 can use the phase place of measuring change from the peak value of peak search unit 619 output and position, and the phase place that measures of output.Phase value can be used for the decimal carrier frequency shift and estimate.

Simultaneously, generate the oscillator that is used for carrying out the frequency of frequency displacement by second multiplier 607 and the 3rd multiplier 609 and may produce any phase error.

Even the phase error that the 4th multiplier 617 also can the oscillation-damped device in this case.Can represent by equation from the result of

first filter

611 and 613 outputs of second filter and the result who exports from the 4th multiplier 617.

[equation 3]

y _MAF1＝‖a ₁(n)‖ ²·e ^j2πΔf+θ

y _MAF2＝‖a ₂(n)‖ ²·e ^j2πΔf-θ

y _prod＝‖a ₁(n)‖ ²·‖a ₂(n)‖ ²·e ^j2π·2Δf

Wherein, y _MAF1And y _MAF2Represent the output of first filter 611 and second filter 613 respectively, and y _ProdRepresent the output of the 4th multiplier 617.In addition, a1 and a2 represent the level of association results respectively, and f and θ represent the frequency displacement and the phase error of oscillator respectively.

Therefore, y _MAF1And y _MAF2The phase error that can comprise oscillator with distinct symbols, but in the result of the 4th multiplier 617, eliminated the phase error of oscillator.Therefore, can irrespectively estimate frequency displacement f with the phase error of the oscillator of signal receiving device.

The frequency displacement of estimating can be represented by following equation.

[equation 4]

f _B＝∠y _prod/4π

Wherein, the frequency displacement f of estimation is 0＜=f＜0.5.

Figure 55 is the figure of another execution mode that the structure of first pilot signal is shown.In first pilot signal, the frequency displacement of the first half of live part A is Cyclic Prefix (B), and the frequency displacement of the latter half of live part A is cyclic suffix (C).For example, the length that is used for the live part A of generating portion B and C can be part A length 1/2, and the length of B and C can be different.

Figure 56 illustrates to detect first pilot signal shown in Figure 55 and use testing result to measure the figure of the execution mode of timing slip and frequency shift (FS).In this embodiment, for convenience of description, B and C represent respectively by 1/2 of the length of part A is carried out Cyclic Prefix and the cyclic suffix that frequency shift (FS) obtains.

This execution mode comprises first delay cell 601, complex conjugate computing unit 603, first multiplier 605, second multiplier 607, first filter 611, second delay cell 615, the 3rd multiplier 609, second filter 613, the 4th multiplier 617, peak search unit 619 and phase measurement unit 621.That is, this execution mode is equal to the execution mode of Figure 54, but the characteristic of parts can change according to the length of the part A that is used for generating portion B and C.B represents from the part of part A to downshift, and C represents from the part of part A to upshift.

First delay cell 601 can postpone the signal that received.For example, first delay cell 601 can be with 1/2 of the length of the effective code element part (A) of signal delay first pilot signal that received.

Second multiplier 607 can multiply each other with the frequency shift amount (representing with ejfSHt) that puts on part B from the signal of first multiplier 605 output, and the signal that obtains of output multiplication.

611 pairs of signals from 607 outputs of second multiplier of first filter are carried out rolling average in predetermined periods.The rolling average part can be the length of Cyclic Prefix (B).In this embodiment, first filter 611 can calculate the mean value of the signal that comprises in the length of part B.So from the result of first filter, 611 outputs, part A that comprises in the part of having calculated mean value and the relating value of C roughly become 0, the association results of part B and A keeps.Since second multiplier 607 with the signal times of part B with frequency offseting value, so it equals the signal that obtains by the latter half that duplicates part A.

613 pairs of signals from 609 outputs of the 3rd multiplier of second filter are carried out rolling average in predetermined periods.The rolling average part can be the length of cyclic suffix (C).In this embodiment, second filter 613 can calculate the mean value of the signal in the length that is included in portion C.So from the result of second filter, 613 outputs, part A that comprises in the part of having calculated mean value and the relating value of B roughly become 0, the association results of portion C and A keeps.Since the 3rd multiplier 609 with the signal times of portion C with frequency offseting value, so it equals the signal that obtains by the first half that duplicates part A.

Second delay cell 615 can postpone from the signal of first filter, 611 outputs.For example, second delay cell 615 will be by the length of first filter, 611 filtered signal delay part B+1/2A, and the signal after the output delay.

Signal after the 4th multiplier 617 will be postponed by second delay cell 615 with by second filter, 613 filtered signal multiplications, and the signal that obtains of output multiplication.

As mentioned above, generate the oscillator that is used for carrying out the frequency of frequency displacement by second multiplier 607 and the 3rd multiplier 609 and may produce any phase error.But, even in this embodiment, the phase error that the 4th multiplier 617 also can the oscillation-damped device.

Can represent by following equation from the result of

first filter

[equation 5]

y _MAF1＝||a ₁(n)|| ²·e ^j2πΔf+θ

y _MAF2＝||a ₂(n)|| ²·e ^j2πΔf-θ

y _prod＝||a ₁(n)|| ²·||a ₂(n)|| ²·e ^j2π·2Δf

Wherein, y _MAF1And y _MAF2Represent the output of first filter 611 and the 3rd filter 613 respectively, and y _ProdRepresent the output of the 4th multiplier 617.In addition, a1 and a2 represent the level of association results respectively, and f and θ represent the frequency displacement and the phase error of oscillator respectively.

[equation 6]

f _B＝∠y _prod/2π

Wherein, the frequency displacement f of estimation is 0＜=f＜1.

That is, in the frequency displacement of in [equation 4], estimating, can in the scope of 0.5＜=f＜1, produce phase distortion (phase aliasing), but not produce phase distortion in the frequency displacement of in [equation 6], estimating.Therefore, can measure frequency displacement more accurately.Can in data symbols and second frequency signal, use the structure of first pilot signal.If use such structure, then can improve the skew estimated performance of interfering, and can improve the receptivity of receiver such as CW.

Figure 57 illustrates to detect first pilot signal and use testing result to measure the figure of the execution mode of timing slip and frequency shift (FS).

This execution mode comprises first delay cell 601, the 3rd delay cell 602, the first complex conjugate computing unit 603, the second complex conjugate computing unit 604, first multiplier 605, the 5th multiplier 606, second multiplier 607, first filter 611, second delay cell 615, the 3rd multiplier 609, second filter 613, the 4th multiplier 617, peak search unit 619 and phase measurement unit 621.

In this embodiment, first delay cell 601 can postpone the signal that received.For example, first delay cell 601 can be with the length of the signal delay cyclic suffix that received.

The 3rd delay cell 602 can postpone by the signal after 601 delays of first delay cell.For example, the 3rd delay cell 602 further postpones described signal poor between the length of the length of Cyclic Prefix and cyclic suffix.

The first complex conjugate computing unit 603 can calculate the complex conjugate by the signal after 602 delays of the 3rd delay cell, and exports the signal that is calculated.The second complex conjugate computing unit 604 can calculate the complex conjugate by the signal after 601 delays of first delay cell, and exports the signal that is calculated.

First multiplier 605 can be with the signal and the signal multiplication that is received from the output of the first complex conjugate computing unit 603, and the signal that obtains of output multiplication.The 5th multiplier 606 can be with the complex conjugate that calculated by the second complex conjugate computing unit 604 and the signal multiplication that is received, and the signal that obtains of output multiplication.

Second multiplier 607 can with from the signal of first multiplier 605 output with put on the frequency shift amount of part B (with e ^JfSHtExpression) multiply each other, and the signal that obtains of output multiplication.

611 pairs of signals from 607 outputs of second multiplier of first filter are carried out rolling average in predetermined periods.The rolling average part can be the length of the live part (A) of first pilot signal.

The 3rd multiplier 609 can with from the signal of second multiplier 604 output and the frequency shift amount that puts on portion C (with-e ^JfSHtExpression) multiply each other, and the signal that obtains of output multiplication.

613 pairs of signals from 609 outputs of the 3rd multiplier of second filter are carried out rolling average in predetermined periods.The rolling average part can be the length of the live part A of first pilot signal.

Second delay cell 615 can postpone from the signal of first filter, 611 outputs.For example, second delay cell 615 will be by the length of the live part (A) of signal delay first pilot signal of first filter, 611 filtering, and the signal after the output delay.

Signal after the 4th multiplier 617 will be postponed by second delay cell 615 with by second filter, 613 filtered signal multiplications, and the signal that obtains of output multiplication.The 4th multiplier 617 can the oscillation-damped device phase error.

The operation of peak search unit 619 and phase measurement unit 621 is equal to the operation of the peak search unit 619 and the phase measurement unit 621 of above-mentioned execution mode.Peak search unit 619 is being searched for the position that produces peak value from the multiplying signal of the 4th filter 617 outputs, and exports the position that searches to phase measurement unit 621.Peak value and position can be used for timing slip and estimate.

Figure 58 is the figure that the execution mode of the method that sends signal is shown.

The transport stream of transport service is carried out error correction coding (S110).Can change the error correction coding scheme according to transport stream.

Can use LDPC error correction coding scheme as the error correction coding scheme, and can carry out error correction coding according to various code checks.The bit that has carried out error correction coding according to specific error correction code rate can be included in the error correction coding block according to the error correction coding pattern.If the error correction coding scheme is LDPC, then can use general mode (64800 bit) and short pattern (16200 bit).

To the transport stream after the error correction coding interweave (S120).Can in memory, write the bit that comprises in the error correction coding block and the direction that from memory, reads in the bit that comprises in the error correction coding block and carry out and interweave by distinguishing.The quantity of the row of memory and the quantity of row can change according to the error correction coding pattern.Can be that the unit execution interweaves according to error correction coding block.

The bit that will interweave is mapped to code element (S130).The symbol mapped method can change according to transport stream, perhaps changes in transport stream.For example, as the symbol mapped method, can use more senior symbol mapped method and more rudimentary symbol mapped method.When mapping during code element, can carry out demultiplexing to the bit stream that interweaves according to the code check of symbol mapped method or error correction coding, and can use the bit that comprises in the son stream behind demultiplexing to shine upon code element.Then, can change the order of the bit in the unit word that is mapped to code element.

To the code element interweave (S140) after the mapping.Can be that unit comes the code element after the mapping is interweaved according to error correction coding block.Time-interleaved

device

132a and 132b can be that unit comes code element is interweaved according to error correction coding block.That is, once more transport stream is interweaved in symbol level.

Split the code element that interweaves of transport stream, give the signal frame that has at least one frequency band and in described frequency band, comprise a plurality of time slots that the time is cut apart with the symbol allocation of separating, and in the initial part of signal frame, the lead code that comprises first pilot signal and second pilot signal is set.The code element that interweaves of transport stream can constitute PLP at the transport stream that is used to provide professional.The stream that constitutes PLP can be split and distribute to signal frame.PLP can be assigned to signal frame with at least one frequency band.If be provided with a plurality of frequency bands, then the code element that constitutes PLP can be arranged in the time slot that is offset between frequency band.Can be that unit is arranged on the bit that comprises in the transport stream in the signal frame according to the error correction coding block that interweaves.

According to the OFDM scheme signal frame is transformed to time domain (S160).

In time domain, will carry out Cyclic Prefix that frequency displacement obtains by first and carry out the cyclic suffix that frequency displacement obtains by second portion and insert in the OFDM code element that comprises in first pilot signal (S170) live part to the live part of first pilot signal.If in frequency domain, do not insert lead code, then the lead code that comprises first pilot signal and second pilot signal can be inserted in the time domain.First pilot signal of time domain can comprise the cyclic suffix of the second portion of the Cyclic Prefix of first of live part, live part and live part.First can be the backmost part or the foremost part of live part.Second portion can be the foremost part of live part or part backmost.

Send the signal frame (S180) that comprises first frame signal by the RF signal.

Because the live part of first pilot signal comprises Cyclic Prefix and cyclic suffix after the frequency displacement, so signal frame clearly can be identified as the structure of first pilot signal.Can estimate and compensate timing slip or frequency shift (FS), to use the structure of first pilot signal.

Figure 59 is the figure of execution mode that the method for received signal is shown.

The special frequency band received signal (S210) that from signal frame, comprises.Signal frame can have at least one frequency band and sends.Can be from the special frequency band received signal.

From the signal that receives, discern first pilot signal, this first pilot signal comprises by the first to live part carries out Cyclic Prefix that frequency displacement obtains and carries out the cyclic suffix that frequency displacement obtains by the second portion to live part, and uses first pilot signal to come demodulation wherein to comprise the signal frame (S220) of piece of the code element of transport stream to a plurality of time domain time slot allocation by the OFDM scheme.The back will describe the demodulation process of using first pilot signal in detail.

Resolve the signal frame of being discerned (S230).This signal frame can comprise at least one frequency band.In signal frame, the error correction coding block that comprises the code element that transport stream is mapped to can be distributed to the OFDM code element with the error correction coding block of another transport stream.。If signal frame comprises a plurality of frequency bands, then error correction coding block can be assigned to the OFDM code element of time migration in a plurality of frequency bands.

The code element that the signal frame after resolving transport stream is mapped to is carried out deinterleaving (S240).Can carry out deinterleaving in the symbol level that transport stream is mapped to.For example, time de-interweaving device 245a and 245b can carry out deinterleaving to the error correction coding block that comprises the code element that transport stream is mapped to.

Then, the code element after the deinterleaving is separated mapping, to obtain transport stream (S250).When code element being separated when mapping, can export by code element being separated a plurality of son streams that mapping obtains, can carry out multiplexingly to a plurality of sub-stream of exporting, and can export transport stream after the error correction coding.Can change multiplexing scheme according to symbol mapped method and error correction code rate.The symbol de-maps method can change in a transport stream or change according to a plurality of transport stream.

Transport stream is carried out deinterleaving and the transport stream after the deinterleaving is carried out error correction coding (S260).

According to transmission and the device of received signal and the method for transmission and received signal of embodiment of the present invention, the signal that can easily detect and recover to send.In addition, can improve the signal transmission/receptivity of transmission/receiving system.

Figure 60 is illustrated in the flow chart of discerning first pilot signal in the demodulation process and estimating the execution mode of skew.

First pilot signal comprises by the first to the live part of first pilot signal carries out Cyclic Prefix that frequency displacement obtains and carries out the cyclic suffix that frequency displacement obtains by the second portion to its live part.Can use first pilot signal to calculate timing slip and frequency shift (FS) as follows.

The signal (S311) that postpones reception.For example, decay part can be 1/2 of the live part of first pilot signal or a live part.Alternatively, decay part can be the length of Cyclic Prefix or the length of cyclic suffix.

The complex conjugate of the signal behind the computing relay (S313).

With the complex conjugate of the signal that receives with postpone after signal multiplication (S315).Multiply by complex conjugate delay back signal can be the signal with above-mentioned length.If postponing the back signal is the length of Cyclic Prefix or cyclic suffix, then can computing relay after the complex conjugate of signal.

Frequency displacement according to Cyclic Prefix carries out reversed migration (S317) to multiply by complex conjugate signal.That is, the reversed migration amount of the frequency shift amount of complex conjugate signal bias Cyclic Prefix signal will be multiply by.That is, the subtend upshift signal carry out to downshift (perhaps the subtend downshift signal carry out to upshift).

Then, calculate the mean value (S319) that has carried out the signal of reversed migration according to the frequency shift amount of Cyclic Prefix.The part of calculating mean value can be according to the length of the Cyclic Prefix of first pilot signal of execution mode or the length of live part A.Owing to come calculating mean value at signal, can export moving average with the signal that receives with equal length with the signal that receives.

The signal that has calculated mean value is postponed (S321).According to present embodiment, decay part can be the length of the live part A of the length of 1/2 length sum, Cyclic Prefix of the length of Cyclic Prefix and effectual time or first pilot signal.

According to the frequency displacement of cyclic suffix, multiplied signals in step S315 is carried out reversed migration (S323).The reversed migration amount of the frequency shift amount of complex conjugate signal bias cyclic suffix signal will be multiply by.That is, the subtend upshift signal carry out to downshift (perhaps the subtend downshift signal carry out to upshift).

Come calculating mean value (S325) at the signal that has carried out reversed migration according to the frequency displacement of cyclic suffix.According to execution mode, come moving average calculation at the signal corresponding with the length of the live part of the length of the cyclic suffix that calculates or first pilot signal.

Signal after will in step S321, postponing and the signal multiplication (S327) of falling into a trap and having calculated mean value at step S325.

The peak position (S329) of search multiplied result, and use this peak to come the phase place (S331) of measuring-signal.The peak that searches can be used to estimate timing slip, and the phase place that measures can be used for the estimated frequency skew.

In this flow chart, the length of cyclic suffix, the length of Cyclic Prefix and frequency reversed migration amount can change.

According to the device of transmission of the present invention and received signal and the method for transmission and received signal, if constituting the data symbols of PLP modulates according to identical FFT pattern with the code element that constitutes lead code, then lower to the probability of data symbols by preamble detection, and reduced the probability of error detection lead code.If comprise continuous wave (CW) interference as analog tv signal, then reduced the probability that detects lead code owing to the noise DC component that when association, produces mistakenly.

According to the device of transmission of the present invention and received signal and the method for transmission and received signal, if the size of FFT that puts on the data symbols that constitutes PLP is greater than the size of the FFT that puts on lead code, so, even be equal to or greater than in the delay spreading channel of length of effective code element part A of lead code in length, also can improve the preamble detection performance.Since in lead code, use Cyclic Prefix (B) and cyclic suffix (C) the two, so can estimate the decimal carrier frequency shift.

With describe according to above-mentioned Bit Interleave method send example with the method for received signal thereafter.

Figure 61 illustrates another example according to the method for transmission of the present invention and received signal.

Carry out error correction coding (S411) to comprising professional transport stream.

Method by changing stored bits in memory according to the symbol mapped method and read the method for bit from memory is to the bit of the transport stream after the error correction coding interweave (S413).In this case, carry out Bit Interleave by this way: with the unit of classifying as with bit storage in memory, wherein memory has a plurality of row and a plurality of row according to the symbol mapped method, according to the symbol mapped method, produce skew between the position of first bit of in each row, being stored, and, in each row, according to cyclic addressing, from the position of storing first bit to the location storage bit of stored bits.

If read the bit of storage, then read according to the symbol mapped method and be stored in bit in the memory with behavior unit.In this case,, should produce skew in the position of reading first bit from each row according to the symbol mapped method, and, in each row, read bit from the position of reading first bit according to cyclic addressing.

According to above-mentioned symbol mapped method the bit after interweaving is carried out symbol mapped (S415).

Symbol allocation after the mapping is sent to the signal frame of at least one RF channel, and will be comprised that the lead code of first pilot signal that signal frame can be identified each other is arranged on (S417) in the signal frame.

Modulated signal frames sends (S419) then.

The method that receives and handle above-mentioned signal will be described below.

Receive the received signal comprise the signal frame that sends at least one RF channel from a RF channel, and come identification signal frame (S421) according to first pilot signal of the lead code of signal frame.

Restituted signal frame, and the signal frame after the parsing demodulation, thereby the code element (S423) of first transport stream of output in a plurality of time slots.

According to the symbol mapped method code element is separated mapping with output bit flow (S425).

By method that changes stored bits in memory and the method that reads bit from memory the bit stream of exporting is carried out deinterleaving (S427).Use is corresponding to the Bit Interleave of step S413.With the unit's of classifying as stored bits in memory, wherein memory has a plurality of row and a plurality of row according to the symbol mapped method.In this case, stored bits in memory as follows: according to the symbol mapped method, in each row, produce skew between the position of first bit of storage, and in each row, according to cyclic addressing, from the position of storing first bit to the location storage bit of stored bits.

If read the bit of storage, then read according to the symbol mapped method and be stored in bit in the memory with behavior unit.In this case, according to the symbol mapped method, should produce skew from the position of each first bit of reading of row, and in each row, read bit from the position of reading first bit according to cyclic addressing.

Bit after the deinterleaving is carried out error correction decoding (S429).

Figure 62 is the figure that another execution mode of the device that is used to send signal is shown.Sender unit shown in Figure 62 comprises input processor 110, coding and modulating unit 120, frame constructor 130, MIMO/MISO encoder 140, corresponding to the modulator 150a in a plurality of paths of MIMO/MISO encoder 140, ..., 150r and a plurality of analog processor 160a, ..., 160r.Execution mode shown in this execution mode and Fig. 4 is similar, and difference is also to comprise information (L1/L2) maker 1301 and is used for information (L1/L2) encoder 1303 that ground floor information and second layer information are encoded and interweaved.To describe the example of information maker 1301 and information encoder 1303 now in detail.

As mentioned above, ground floor information can comprise the information about the PLP structure of signal frame, and can be included in second pilot signal.Second layer information can be described the business that is sent by PLP included in signal frame, and can send to second pilot signal or public PLP.For example, although send included second pilot signal and public PLP in the signal frame, send identical value to a plurality of RF channels to a plurality of RF channels of signal frame.Therefore, owing to can't obtain frequency diversity gain, therefore processing signals as follows: make according to error correction coding or interweave and improve the information recovery capability.

If frame constructor 130 has constituted signal frame, then information maker 1301 can generate ground floor information and the second layer information that is included in the signal frame.Information maker 1301 can generate and be used to send professional transport stream with the position of the signal frame that sends to and the modulation and the coded message of transport stream.

Information encoder 1303 can be encoded to the ground floor information and the second layer information that are generated by information maker 1301 according to modulation and coded message.Frame constructor 130 will be inserted in second pilot signal by the ground floor information of information encoder 1303 codings, and second layer information is inserted among second pilot signal or the public PLP.Therefore, by information encoder 1303, can protect ground floor information and the second layer information mistake of transmitting channel not occur.

Figure 63 is the figure that the execution mode of information encoder 1303 is shown.The information encoder can comprise first encoder 1311, first interleaver 1313, second encoder 1315 and second interleaver 1317.

First encoder 1311 is external encoders, and it carries out first error correction coding to input data (ground floor information and second layer information).For example, the input data can be carried out error correction coding by BCH error correction coding scheme.Carry out the error correction coding of first encoder 1311 according to the error correction coding scheme of second encoder, to reduce wrong substrate (floor).

First interleaver 1313 is outer interleaver, and it can interweave to the data from 1311 outputs of first encoder.First interleaver 1313 can reduce burst error.

Second encoder 1315 is internal encoders, and it is to carrying out second error correction coding from the data of first interleaver, 1313 outputs.For example, the data after second encoder 1315 can interweave to first interleaver 1313 by LDPC error correction coding scheme are encoded.

When the input data were encoded, second encoder 1315 can be carried out shortening and delete surplus the data that will carry out error correction coding.For example, because the amount of ground floor information and second layer information less than the amount that is used to send professional transport stream, therefore can be used the code with short length.Therefore, second encoder 1315 can be carried out from the female sign indicating number with low encoding rate and shorten and delete surplusly, and output has the error correcting code of short length.As female sign indicating number, can use LDPC or convolution code.

Second encoder 1315 is filled into undersized information bit (zero padding) with zero (0), so second encoder 1315 meets the input bit number of LDPC coding (shortening).After LDPC coding, second encoder 1315 remove fill zero, and to the part of the parity check of the coded data that generates carry out delete surplus, to meet its encoding rate.

Second interleaver 1317 is inner interleaver, and it carries out Bit Interleave to carried out coded data by second encoder 1315.Can carry out Bit Interleave by one of scheme shown in Figure 20 to Figure 28.

Figure 64 is the figure that another execution mode of the device that is used for received signal is shown.Signal receiving device shown in this execution mode and Figure 39 is similar.Therefore, the execution mode of this signal receiving device comprises the first signal receiver 210a, n signal receiver 210n, the first demodulator 220a, n demodulator 220n, MIMO/MISO decoder 230, frame parser 240, decoding demodulator 250 and output processor 260.The execution mode of this figure also comprises information (L1/L2) decoder 2401 and information (L1/L2) extractor 2403.

Frame parser 240 can the analytic signal frame.Frame parser 240 can be resolved the lead code of the signal frame that comprises first pilot signal and second pilot signal.Frame parser 240 can be resolved the public solution parser.

Frame parser 240 is exported ground floor information and second layer information included in second pilot signal and public PLP to information decoding device 2401.2401 pairs of ground floor information of information decoding device and second layer information are decoded.The back will be described the example of information decoding device 2401 in detail.Information extractor 2403 is extracted decoded ground floor information and second layer information, and to frame parser 240 and system controller (not shown) output ground floor information.Frame parser 240 can use the structure of the ground floor information check included PLP in signal frame that extracts, and output is by the PLP of user according to the ground floor Information Selection.

Figure 65 is the figure that the detailed execution mode that ground floor information and second layer information are decoded is shown.This execution mode can comprise first deinterleaver 2411, first decoder 2413, second deinterleaver 2415 and second decoder 2417.

2411 pairs of first deinterleavers comprise that the input data execution inside of ground floor information and second layer information interweaves.Can carry out the deinterleaving scheme of first deinterleaver 2411 by one of described Bit Interleave scheme of Figure 20 to Figure 28.

First decoder 2413 is carried out error correction decoding according to the data of the first error correction coding scheme after to deinterleaving.In this case, can shorten and delete ground floor information after surplus and the data of second layer information are decoded comprising.

For example, 2413 pairs of Parity Check Bits from the data of first deinterleaver, 2411 outputs of first decoder are carried out complementary (depuncture).In addition, first decoder 2413 adds the data behind the complementary to and carries out error correction decoding 0.First decoder 2413 is removed the data after 0 and the output added are shortened.

2415 pairs of second deinterleavers are carried out deinterleaving by the data that first decoder 2413 has carried out error correction decoding, and second decoder 2417 according to the second error correction coding scheme to carrying out error correction decoding from the data of second deinterleaver, 2415 outputs.Second decoder 2417 can be exported the initial data of ground floor information and second layer information.

Although use the shortening scheme in the above-described embodiment and delete surplus scheme ground floor information and second layer information are carried out correction coding/decoding, can carry out correction coding/decoding at least one side of ground floor information and second layer information.For example, can only use the shortening scheme and delete surplus scheme ground floor information.In this case, can be only to the execution mode among ground floor information employing Figure 63 and Figure 65.Can only adopt the execution mode of Fig. 6 and Figure 49 to ground floor information, vice versa.

Figure 66 illustrates the flow chart that is used to send with the method for received signal.To the execution mode of handling ground floor information be described thereafter.But, similar with this execution mode, can under with the state of second layer information setting in public PLP, send second layer information.To describe execution mode that ground floor information decoded and encode thereafter.

Generation will be inserted into the ground floor information (S501) of signal frame.Ground floor information can comprise the information and the information that is used for the id signal frame about the PLP structure of signal frame.Can comprise about the information of the PLP that comprises in the superframe included in a plurality of signal frames with about the information of the signal frame of superframe about the information of PLP structure.PLP wherein encodes separately to transport stream and modulates to send the unit of transport stream.PLP can be distributed at least one RF channel of signal frame or a plurality of signal frames.

The error correction coding scheme that use comprises the shortening scheme and deletes surplus scheme is to ground floor information encode (S503).Owing to will be inserted into ground floor information big or small less of signal frame, therefore can be according to short pattern such as the error correction coding scheme of LDPC encoding scheme, use error correction coding scheme comes ground floor information is encoded.

To the bit of the ground floor information after the error correction coding interweave (S505).

As error correction coding, can carry out the processing of first error correction coding or second error correction coding and handle.Then, after first error correction coding, carry out first and interweave, and after second error correction coding, carry out second and interweave.As second error correction coding, can use LDPC error correction coding scheme.

For example, carry out the second error correction coding step by adding the input data to, to check the number (shortening) of input data with 0.After second error correction coding, the part of the Parity Check Bits that generates is deleted surplus, and adjust the encoding rate (deleting surplus) of the second error correction coding scheme.

The bit of the ground floor information after interweaving is set in the lead code of signal frame, and PLP (S507) is set in signal frame.Signal frame can comprise will be by the PLP of at least one RF channel transmission.

Modulated signal frames and send signal frame (S509) by at least one RF channel.

If receive signal, then be received in the signal frame (S511) that sends the RF frequency band that comprises at least one RF channel from a RF channel.

Signal frame to the received signal carries out demodulation (S513).

Lead code to the signal frame that comprises ground floor information is resolved, and output ground floor information (S515).

Bit to ground floor information carries out deinterleaving (S517).

The bit of the error correction decoding scheme that use comprises the shortening scheme and deletes surplus scheme after decode (S519) to deinterleaving.In this step, for example, carry out complementary and add 0 according to the bit of error correction coding scheme after to deinterleaving.Carry out error correction decoding to having added 0 data, and remove add 0.

Ground floor information behind the use error correction decoding is come the analytic signal frame, and obtains PLP (S521) from signal frame.

Handle by this,, therefore can proofread and correct the mistake of information included in lead code because the lead code of the signal frame that can't obtain diversity gain is carried out error correction coding.Therefore, may improve the receptivity of information included in the accurate lead code.

To those skilled in the art, apparent, can make various modifications and modification to the present invention, and not depart from scope of the present invention.Therefore, the present invention is intended to cover modification of the present invention and modification, as long as these modifications and modification fall within the scope of appended claims and equivalent thereof.

Pattern of the present invention

With optimal mode of the present invention embodiments of the present invention have been described.

Industrial applicability

The device of the method for sending/receiving signal of the present invention and sending/receiving signal can be used for broadcasting and the communications field.

Claims

1. method that sends signal, this method may further comprise the steps:

Generation (S501) will be inserted into the ground floor information in the signal frame;

By the error correction coding scheme described ground floor information is encoded (S503), described error correction coding scheme comprises the shortening scheme and deletes surplus scheme;

To the bit of the ground floor information after the error correction coding interweave (S505);

The bit setting (S507) of the ground floor information after will interweaving and is arranged on physical layer pipe (PLP) in the described signal frame in the lead code of described signal frame; And

Modulation (S509) described signal frame, and send signal frame after the modulation by at least one radio frequency (RF) channel.

2. method according to claim 1, wherein, described error correction coding scheme comprises low-density checksum (LDPC) error correction coding scheme.

3. method according to claim 2 wherein, is carried out error correction coding according to the short pattern of described LDPC to described ground floor information.

4. method according to claim 1, wherein, described ground floor information comprises at least a in quantity, professional modulation intelligence and the cell identifier of the error correction coding block in protection gap length, each signal frame.

5. the method for a received signal, this method may further comprise the steps:

Receive the signal that (S511) sends in the RF frequency band that comprises at least one radio frequency (RF) channel;

Carry out demodulation (S513) to the received signal;

Resolve the lead code that (S515) comprises the signal frame of ground floor information the signal after demodulation;

Bit to described ground floor information carries out deinterleaving (S517);

The bit of the error correction decoding scheme that use comprises the shortening scheme and deletes surplus scheme after decode (S519) to deinterleaving; And

Ground floor information behind the use error correction decoding obtains (S521) physical layer pipe (PLP) from described signal frame.

6. method according to claim 5 wherein, is carried out error correction decoding by low-density checksum (LDPC) error correction coding scheme.

7. method according to claim 6 wherein, is carried out error correction coding according to the short pattern of described LDPC to described ground floor information.

8. method according to claim 5, wherein, described ground floor information comprises at least a in quantity, professional modulation intelligence and the cell identifier of the error correction coding block in protection gap length, each signal frame.

9. device that sends signal, this device comprises:

Information maker (1301), it is constituted as generation will be inserted into ground floor information in the signal frame;

Information encoder (1303), it is constituted as

Use comprises the shortening scheme and deletes the error correction coding scheme of surplus scheme to described ground floor information and executing error correction coding; And

Bit to the ground floor information after the error correction coding interweaves;

Frame constructor (130), its bit that is constituted as the ground floor information after interweaving is arranged in the lead code of described signal frame, and physical layer pipe (PLP) is distributed in the described signal frame;

Modulator (150a, 150r), it is constituted as the described signal frame of modulation; And

Transmitting element (160a, 160r), it is constituted as by the signal frame after at least one radio frequency (RF) channel transmission modulation.

10. method according to claim 9, wherein, described information encoder (1303) comprising:

First encoder (1311), it is constituted as carries out first error correction coding to the bit of described ground floor information;

First interleaver (1313), it is constituted as the bit after first error correction coding is interweaved;

Second encoder (1315), it is constituted as according to described shortening scheme and describedly deletes surplus scheme the bit after interweaving is carried out second error correction coding; And

Second interleaver (1317), it is constituted as the bit after second error correction coding is interweaved.

11. according to Claim 8 with 9 in any described device, wherein, described error correction coding scheme comprises low-density checksum (LDPC) error correction coding scheme.

12. device according to claim 10 wherein, carries out error correction coding according to the short pattern of described LDPC error correction coding scheme to described ground floor information.

13. the device of a received signal, this method comprises:

Receiver (210a, 210n), it is constituted as and is received in the signal that sends in the RF frequency band that comprises at least one radio frequency (RF) channel;

Demodulator (220a, 220n), it is constituted as and carries out demodulation to the received signal;

Information decoding device (2401), it is constituted as

Bit to the ground floor information that parses from the signal frame of received signal carries out deinterleaving, and

Carry out error correction decoding according to the bit of the error correction decoding scheme that comprises the shortening scheme and delete surplus scheme after to deinterleaving;

Information extractor (2403), it is constituted as the ground floor information after the extraction error correction coding; And

Frame parser (240), it is constituted as the ground floor information that use extracts and resolves described signal frame, and obtains physical layer pipe (PLP) from described signal frame.

14. device according to claim 13, wherein, described information decoding device (2401) comprising:

First deinterleaver (2411), it is constituted as carries out deinterleaving to the bit of described ground floor information;

First decoder (2413), it is constituted as basis and described shortening scheme and described scheme of deleting surplus scheme contrary, and the bit after the deinterleaving is carried out error correction decoding;

Second deinterleaver (2415), it is constituted as the bit behind the error correction decoding is carried out deinterleaving; And

Second decoder (2417), it is constituted as carries out error correction decoding to the bit after the deinterleaving.