CN101924132A - Semiconductor device for power - Google Patents
Semiconductor device for power Download PDFInfo
- Publication number
- CN101924132A CN101924132A CN 201010144886 CN201010144886A CN101924132A CN 101924132 A CN101924132 A CN 101924132A CN 201010144886 CN201010144886 CN 201010144886 CN 201010144886 A CN201010144886 A CN 201010144886A CN 101924132 A CN101924132 A CN 101924132A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- semiconductor layer
- layer
- post layer
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a semiconductor device for power, which comprises a n column layer and a p column layer which are laterally and alternately disposed above a n+ leaking layer, a p substrate disposed at the surface of the p column layer, a n source layer formed on the surface of the p substrate, a surface p column layer and a surface n column layer which are laterally and alternately disposed, a leakage electrode electrically connected to the n+ leaking layer, a grid electrode which is formed by disposing insulated film between two of the p substrate, surface p column layer and the surface n column layer, and a source electrode which is connected to the surface of the p column layer and the n source layer. The surface p column layer is disposed above at least one p column layer which is arranged between two p substrates. The impurity concentration of the p column layer disposed below the surface p column layer is higher the impurity concentration of the p column layer disposed below the p substrate.
Description
The cross reference of related application
The application is based on the Japanese patent application NO.2009-138270 formerly that submitted on June 9th, 2009 and require its priority, is incorporated herein its full content as a reference.
Technical field
The present invention relates to power semiconductor device, particularly possess the power semiconductor device of super-junction structure.
Background technology
In power semiconductor device, expect low-power consumption in order to reduce energy loss.For example, depend on the resistance of conducting shell (drift layer) part of decision conducting resistance significantly as the power consumption of the vertical structure power MOSFET of one of power semiconductor device.And, determine the withstand voltage of pn knot that the doping impurity amount of the resistance of this drift layer forms according to basic unit and drift layer and can not rise to more than the boundary.Therefore, in device withstand voltage and conducting resistance, exist and trade off, under this trade-off relation, carry out the optimal design of device.On the other hand, in this trade-off relation, the intrinsic boundary that depends on device material and structure is arranged, the technology of developing above this boundary is the method that realizes above the low energy-consumption electronic device of existing power semiconductor device.
For example, as significantly having improved above-mentioned compromise power semiconductor device, known have have super-junction structure (the SJ structure: MOSFET SuperJunction structure) of in drift layer, having imbedded p post layer and n post layer periodically.The SJ structure is a same amount by making the quantity of electric charge (impurity level) that is included in p post layer and the n post layer, thereby produce the non-impurity-doped layer virtually and keep high withstand voltage, and then electric current is flow through by the n post layer after highly doped, thereby realize low on-resistance near the material boundary.
By such use SJ structure, can realize surpassing in the past conducting resistance and the device of withstand voltage trade-off relation.But in order to reduce conducting resistance, needing increases the impurity level that mixes in n post layer in the SJ structure, but needs simultaneously to increase the impurity of p post layer and reduce horizontal periodic width.Increase the impurity level of p post layer and n post layer if do not reduce horizontal periodic width, the horizontal electric field that the SJ structure is exhausted fully will be higher than the electric field longitudinally that avalanche breakdown produces in drift layer.Therefore, before the SJ structure was exhausted fully, the hole current that is produced by the avalanche breakdown in the drift layer was injected into the basic unit of MOSFET, makes the parasitic transistor conducting, and the withstand voltage reduction that the pn that basic unit and drift layer are formed ties.That is, in order to keep the high withstand voltage state decline low on-resistance of SJ structure in maintenance, reducing horizontal periodic width is integral (for example, patent documentation 1).But, if reduce horizontal periodic width, the manufacturing process that then has the SJ structure and the form device thereon complicated such problem that becomes.
In patent documentation 2, put down in writing by combination super-junction structure and TERRACE GATE (terraced steps grid) structure, and part ground improves the structure of post concentration.Thus, can the limit keep high withstand voltagely, the limit reduces conducting resistance.But, in this structure, owing to added TERRACE GATE (terraced steps grid) spreading resistance under just, so in the reduction of conducting resistance, have boundary.
Patent documentation 1: Japanese kokai publication hei 11-233759 communique
Patent documentation 2: TOHKEMY 2008-258327 communique
Summary of the invention
According to a mode of the present invention, a kind of power semiconductor device is provided, it is characterized in that possessing: the 1st semiconductor layer of the 1st conductivity type; The 2nd semiconductor layer of the 1st conductivity type that on above-mentioned the 1st semiconductor layer, laterally is arranged alternately and the 3rd semiconductor layer of the 2nd conductivity type; Be arranged on the 4th semiconductor layer of the 2nd conductivity type on the surface of above-mentioned the 3rd semiconductor layer; Optionally be arranged on the 5th semiconductor layer of the 1st conductivity type on the surface of above-mentioned the 4th semiconductor layer; The 6th semiconductor layer of the 2nd conductivity type that on above-mentioned the 2nd semiconductor layer and the 3rd semiconductor layer, laterally is arranged alternately and the 7th semiconductor layer of the 1st conductivity type; The 1st main electrode that is electrically connected with above-mentioned the 1st semiconductor layer; Be arranged on the dielectric film on above-mentioned the 4th semiconductor layer, above-mentioned the 6th semiconductor layer and above-mentioned the 7th semiconductor layer; Across above-mentioned dielectric film, be arranged on the control electrode on above-mentioned the 4th semiconductor layer, above-mentioned the 6th semiconductor layer and above-mentioned the 7th semiconductor layer; And with the 2nd main electrode of the surface engagement of above-mentioned the 4th semiconductor layer and above-mentioned the 5th semiconductor layer, above-mentioned the 6th semiconductor layer is connected with above-mentioned the 4th semiconductor layer, and then be connected with at least one above-mentioned the 3rd semiconductor layer that between two above-mentioned the 4th semiconductor layers, is provided with, the impurity concentration that is arranged on above-mentioned the 3rd semiconductor layer under above-mentioned the 6th semiconductor layer is higher than the impurity concentration that is arranged on above-mentioned the 3rd semiconductor layer under above-mentioned the 4th semiconductor layer.
Description of drawings
Fig. 1 is the schematic diagram of the profile of unit (unitcell) that the power semiconductor device of the 1st execution mode of the present invention is shown.
Fig. 2 is the schematic diagram of planar configuration that the semiconductor layer of the power semiconductor device that constitutes the 1st execution mode of the present invention is shown.
Fig. 3 illustrates the planar configuration of semiconductor layer of the power semiconductor device that constitutes the 1st execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Fig. 4 is the schematic diagram of planar configuration that the semiconductor layer of the power semiconductor device that constitutes the 1st execution mode of the present invention is shown.
Fig. 5 is the schematic diagram of planar configuration of semiconductor layer that the power semiconductor device of the variation that constitutes the 1st execution mode of the present invention is shown.
Fig. 6 is the schematic diagram of planar configuration of semiconductor layer that the power semiconductor device of the variation that constitutes the 1st execution mode of the present invention is shown.
Fig. 7 is the stereogram of unit of power semiconductor device that the variation of the 1st execution mode of the present invention schematically is shown.
Fig. 8 is the schematic diagram of section of unit of power semiconductor device that the variation of the 1st execution mode of the present invention is shown.
Fig. 9 illustrates the section of unit of power semiconductor device of the 2nd execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Figure 10 illustrates the section of unit of power semiconductor device of the 2nd execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Figure 11 is the schematic diagram of section of unit that the power semiconductor device of the 3rd execution mode of the present invention is shown.
Figure 12 illustrates the section of unit of power semiconductor device of variation of the 3rd execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Figure 13 illustrates the section of unit of power semiconductor device of variation of the 3rd execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Figure 14 illustrates the section of power semiconductor device of the 4th execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Figure 15 illustrates the section of power semiconductor device of variation of the 4th execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Figure 16 illustrates the section of power semiconductor device of variation of the 5th execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Figure 17 illustrates the section of power semiconductor device of variation of the 5th execution mode of the present invention and the schematic diagram of impurities concentration distribution.
Figure 18 is the profile of structure that the power semiconductor device of the 6th execution mode of the present invention schematically is shown.
Figure 19 is the profile of structure of power semiconductor device that the variation of the 6th execution mode of the present invention schematically is shown.
Figure 20 is the schematic diagram of planar configuration that the semiconductor layer of the power semiconductor device that constitutes the 7th execution mode of the present invention is shown.
Figure 21 is the schematic diagram of planar configuration of semiconductor layer that the power semiconductor device of the variation that constitutes the 7th execution mode of the present invention is shown.
Figure 22 is the schematic diagram of planar configuration of semiconductor layer that the power semiconductor device of the variation that constitutes the 7th execution mode of the present invention is shown.
Figure 23 is the schematic diagram of planar configuration of semiconductor layer that the power semiconductor device of the variation that constitutes the 7th execution mode of the present invention is shown.
Figure 24 is the vertical view that the relation of the gate electrode of power semiconductor device of the 8th execution mode of the present invention and semiconductor layer schematically is shown.
Figure 25 is the vertical view that the relation of the gate electrode of power semiconductor device of variation of the 8th execution mode of the present invention and semiconductor layer schematically is shown.
Figure 26 is the profile of structure that the power semiconductor device of the 9th execution mode of the present invention schematically is shown.
Figure 27 is the profile of structure of power semiconductor device that the variation of the 9th execution mode of the present invention schematically is shown.
Embodiment
Below, with reference to accompanying drawing embodiments of the present invention are described.In addition, in the following description, be example with power MOSFET as one of power semiconductor device.In each figure, same key element is added same label, and the 1st conductivity type is made as the n type, the 2nd conductivity type is made as the p type.
(the 1st execution mode)
Fig. 1 is the profile of unit that the power MOSFET of the 1st execution mode of the present invention schematically is shown.
The MOSFET of present embodiment is to use semiconductor substrate 21 to be made.This has the n of semiconductor substrate 21 as the 1st semiconductor layer
+Drop ply 2 and be formed on n
+The n post layer 3 of conduct the 2nd semiconductor layer on the drop ply 2, and n post layer 3 between laterally p post layer 4a, the 4b of conduct the 3rd semiconductor layer of alternate configurations.
On the surface of semiconductor substrate 21, be formed with the p basic unit 5 of conduct the 4th semiconductor layer that is connected with p post layer 4a.Surface in p basic unit 5 is formed with the n source layer 6 as the 5th semiconductor layer.And then, on the surface of semiconductor substrate 21, be formed with a plurality of conduct the 6th semiconductor layers that are connected with p basic unit 5 surface p post layer 10 and with the surface n post layer 11 of conduct the 7th semiconductor layer of surface p post layer 10 alternate configurations.
And then, on semiconductor substrate 21, be formed with dielectric film, as to control electrode being the gate insulating film 8 that insulate between gate electrode 9 and p basic unit 5 and surface p post layer 10, the surface n post layer 11 and performance function.
On the other hand, at the back side of semiconductor substrate 21, be formed with and n
+The drain electrode 1 of conduct the 1st main electrode that drop ply 2 is electrically connected.In addition, on the surface of semiconductor substrate 21, be formed with source electrode 7 with conduct the 2nd main electrode of the surface engagement of p basic unit 5 and n source layer 6.
P post layer 4b is connected with p basic unit 5 across surface p post layer 10.In addition, the impurity concentration of the p post layer 4b that is connected with surface p post layer 10 is higher than the impurity concentration of the p post layer 4a that is connected with p basic unit 5.And then gate insulating film 8 is thicker relatively on the p post layer 4a that is arranged under the surface p post layer 10, and the part of joining with p basic unit 5 is relative thinner.
At the semiconductor substrate 21 that is used for making power MOSFET shown in Figure 1, for example, can use n
+Be made as n on the type silicon substrate
+Drop ply 2 has formed the super epitaxial substrate of tying layer 22 thereon.Super knot layer 22 for example is repeated multiple times epitaxial growth and the multilayer grown layer that forms, and at each grown layer each, correspondence becomes the zone of n post layer 3 and p post layer 4a, 4b, and ion injects n type impurity and p type impurity.At this moment, as mentioned above, the dosage when adjusting the ion injection is so that the p type impurity level of the n type impurity level of n post layer 3 and p post layer 4a, 4b becomes roughly with amount.As shown in the figure, be formed at n
+In the super knot layer 22 on the drop ply 2, have regulation periodically alternate configurations n post layer 3 and p post layer 4a, 4b, and constituted the SJ structure.
In addition, be formed on p basic unit 5 on the semiconductor substrate 21 and clip gate electrode 9 and periodically dispose, the section of one-period is represented in the unit shown in the figure.In addition, in the power MOSFET of present embodiment, each layer of n post layer 3 and p post layer 4a, 4b, p basic unit 5, n source layer 6 forms striated (with reference to Fig. 2) along the depth direction of figure.
From a p basic unit 5 across a plurality of n post layers 3 and p post layer 4b on the zone of another relative p basic unit 5, be formed with gate electrode 9 across gate insulating film 8.In gate insulating film 8, for example use the Si oxide-film.In addition, between two relative p basic units 5, be formed with the surface p post layer 10 that is connected with each p basic unit 5, as shown in the figure, two p post layer 4b that are not connected with p basic unit 5 are connected with surface p post layer 10.
The thickness of the gate insulating film 8 of present embodiment is thicker at the central portion of gate electrode 9, and is thinner on the p of end basic unit 5.That is, the gate insulation thickness on the p basic unit 5 is set thinlyyer, so that gate threshold voltage becomes the value of the scope of regulation.For example, for gate threshold voltage is made as about 4V, form the thickness about 0.1 μ m.On the other hand, the central part of gate electrode is not in order to impact gate threshold voltage, and for example can be made as thick in 1～1.5 μ m.
If drain electrode 1 is applied high voltage, then to applying high voltage between source electrode 7 and the drain electrode 1 and between gate electrode 9 and the drain electrode 1.At gate electrode 9 central portions, by gate insulating film 8 and this two sides sustaining voltage of SJ structure.Therefore,, can improve the withstand voltage of gate insulating film 8, reduce the sustaining voltage of SJ structure by thickening gate insulating film 8.That is, can improve the impurity concentration of each the post layer that constitutes the SJ structure, and reduce conducting resistance.
On the other hand, by be formed on p basic unit 5 just under the voltage that keeps of the n post layer 3 of SJ structure, the p post layer 4a that promptly is connected and adjacency with p basic unit 5 can not be subjected to about the thickness institute of gate insulating film 8.That is, can not improve the impurity concentration of the post layer 4a under the p basic unit 5 in order to keep device withstand voltage.Therefore, shown in the Impurity Distribution among the figure, the impurity concentration of each post layer is configured at the central portion of gate electrode 9 higher, and is lower in p basic unit 5 times.Like this, even can't improve whole post concentration without exception, the impurity concentration of the post layer by improving gate electrode 9 central parts, and improve the impurity concentration of the n post layer 3 of adjacency, can reduce the conducting resistance of device integral body.
For example, have in design under the situation of the withstand voltage device of 600V, the thick part of gate insulating film 8 can be made as 1.5 μ m, the sustaining voltage of dielectric film is made as 300V, the sustaining voltage of the SJ structure under it is made as 300V.Thus, compare, be the sustaining voltage of half, so the impurity concentration of each post layer 4b can be increased to about 2 times of post layer 4a structure under the p basic unit 5 with the SJ structure under the p basic unit 5.Its result if also improve impurity concentration with the n post layer 3 of each post layer 4b adjacency, and makes the high post layer of impurity concentration occupy whole half, then conducting resistance can be reduced about 25%.
In order to obtain above-mentioned effect, it is easy forming gate insulating film 8 thicker.And, inject at ion repeatedly under the situation of the technology that forms the SJ structure with imbedding growth, the amount of the impurity that is mixed can be changed by the mask width that partly changes the ion injection, the impurities concentration distribution of each post layer as shown in Figure 1 can be realized.That is, the mask pattern that can only inject by the change ion is easily made the power MOSFET of present embodiment, can significantly reduce conducting resistance.
Fig. 2 is the schematic diagram of planar configuration of each semiconductor layer that the power MOSFET of above-mentioned the 1st execution mode is shown.Fig. 2 (a) is the schematic diagram that the configuration of surface p post layer 10 and surface n post layer 11, p basic unit 5, n source layer 6 is shown.In addition, Fig. 2 (b) illustrates the configuration of p post layer 4a, 4b and n post layer 3.As mentioned above, p post layer 4a, 4b, n post layer 3 form striated.In addition, be connected with p post layer 4a and the p basic unit 5 that forms also forms along the striated of p post layer 4a.
And, under the gate electrode 9 (not shown) that is disposed between the p basic unit 5 that periodically forms, be formed with surface p post layer 10 and surface n post layer 11 across gate insulating film 8.Shown in Fig. 2 (a), surface p post layer 10 and surface n post layer 11 edge are formed with the direction of p basic unit 5 quadratures, and have periodically alternate configurations.In addition, be configured to simultaneously and p post layer 4a, 4b and n post layer 3 also quadrature.
If gate electrode 9 is applied voltage, then form mos gate raceway groove (with reference to Fig. 1) at the both ends of p basic unit 5, across mos gate raceway groove, surface n post layer 11,, thereby in the n of SJ structure post layer 3 integral body, flow through electric current from n source layer 6 to n post layer 3 extend current.That is, in order to reduce conducting resistance, the surface n post layer 11 that becomes current path also must be a low resistance.The impurity concentration of the surface n post layer 11 that therefore, preferably forms on the surface of semiconductor substrate 21 is higher than the impurity concentration of n post layer 3 more shallowly.
In addition, if to applying high voltage to a certain degree between drain electrode 1 and the source electrode 7, then the SJ structure exhausts fully.At this moment, between source electrode 7 and p post layer 4a, 4b, cause discharging and recharging of hole.Discharge and recharge in order to carry out this apace, p post layer 4a, 4b must be connected with some p basic unit 5.In the structure shown in the present embodiment, there be not direct-connected p post layer 4b to be connected with p basic unit 5 with p basic unit 5 via surface p post layer 10, can when switch, carry out discharging and recharging of hole.
On the other hand, if connect p basic unit 5 and each p post layer 4a, 4b, then the electric capacity of the knot of the pn between all p post layer 4a, 4b and the n post layer 3 becomes capacitor C ds between leakage, source.Follow the increase that is applied to the voltage Vds between drain electrode 1 and the source electrode 7, capacitor C ds reduces between leakage, source.At this moment, big if the rate of change of Cds-Vds characteristic becomes, then the rate of change of drain voltage (Δ Vds/ Δ t) becomes big, and it is big that switching noise becomes.
For example, do not having under the situation that direct-connected p post layer 4b and the p basic unit 5 surface p post layer 10 by high concentration is connected with p basic unit 5, surface p post layer 10 is difficult to exhaust, the voltage that adds according to seal, exhausting simultaneously of all p post layer 4a, 4b and n post layer 3 advances, and Cds sharply reduces.Thus, exist the rate of change of Cds-Vds characteristic to become big, be easy to produce the such problem of switching noise.
With respect to this, before the SJ structure of drift layer exhausted fully owing to be applied to voltage Vds between drain electrode 1 and the source electrode 7, surface p post layer 10 exhausted, and p post layer 4b becomes and be difficult to exhaust, thereby can reduce switching noise.That is, if since surface p post layer 10 exhaust, thereby p basic unit 5 was cut off with being connected of p post layer 4, then p post layer 4b exhaust termination, only in the direct p post layer 4a that is connected with p basic unit 5, exhaust.Afterwards, if further improve Vds, then from it carries out the exhausting of n post layer 3 of p post layer 4b and adjacency in order near a side of p basic unit 5.By such action, the rate of change of Cds-Vds characteristic diminishes, and the rate of change of drain voltage (Δ Vds/ Δ t) diminishes, and can reduce switching noise.
In order to obtain the reduction effect of above-mentioned switching noise, surface p post layer 10 is exhausted.Therefore, preferably compare,, set the impurity concentration of surface p post layer 10 lower in the part that is connected with p post layer 4b with the part that is connected with p basic unit 5.For example, shown in Fig. 3 (a), form that to become the impurity concentration that makes surface p post layer 10 be effective towards the such distribution of the area decreases corresponding with the central portion of gate electrode 9.According to such CONCENTRATION DISTRIBUTION, follow the increase that is applied to the voltage Vds between drain electrode 1 and the source electrode 7, surface p post layer 10 exhausts gradually from the part of low concentration, with the disappearance that is connected of p basic unit 5.Thus, can reduce the variation of Cds-Vds characteristic, so can further reduce switching noise.
At this moment, can for example be made as the impurity concentration of surface n post layer 11 constant between the p basic unit 5 as Fig. 3 (b) adjacency that is shown in.In this case, can be made as the part that is connected with p basic unit 5, the impurity concentration of surface p post layer 10 is higher than the impurity concentration of surface n post layer 11.On the other hand, can the central part of the gate electrode between p basic unit 59 just down, be the central portion of Fig. 3 (a), make the impurity concentration of surface n post layer 11 be higher than the impurity concentration of surface p post layer 10.Thus, can expand depleted region gradually to the direction of p basic unit 5 from the low part of the concentration of the surface p post layer 10 of the central authorities of Fig. 3 (a).
In addition, though shown in Fig. 3 (b) impurity concentration of surface n post layer 11 and non-constant, as long as the central part of gate electrode 9 just down, make the impurity concentration of surface n post layer 11 be higher than the impurity concentration of surface p post layer 10, then also can obtain same effect.That is, the impurity concentration of surface n post layer 11 is changed between p basic unit 5.For example, can also be made as with a side and compare near p basic unit 5, the central part of gate electrode 9 just down, make the higher distribution of impurity concentration of surface n post layer 11.
And then preferably after the impurities concentration distribution that has formed surface p post layer 10 shown in Fig. 3 (a), the periodic width b of alternate configurations surface p post layer 10 and surface n post layer 11 is less than the periodic width a of n post layer 3 with p post layer 4a, 4b as shown in Figure 4.As shown in the figure, by reducing the width of surface p post layer 10, can exhausting according to the surface p post layer 10 in the lower voltage propelling central portion.Thus, owing to can further reduce the rate of change of Cds-Vds characteristic, so can reduce switching noise reliably.
In addition, in above-mentioned present embodiment, also have, can realize the such advantage of high current density action by increasing maximum leakage current.That is, under conducting state also with cut-off state similarly because surface p post layer 10 exhausts, thereby the hole disappears to the path that p basic unit 5 moves from p post layer 4b.Thus, be suppressed to the stretching, extension of the depletion layer of n post layer 3 from p post layer 4b, the current channel in the n post layer 3 is kept, and leakage current is difficult to saturated.Thus, big even maximum leakage current becomes, also can carry out the high current density action.
Fig. 5 to Fig. 7 is the schematic diagram of power MOSFET that the variation of the 1st execution mode is shown.In the above-described embodiment, illustrated to have the n post layer 3 that forms striated and the power MOSFET of p post layer 4a, 4b, but be not limited to the post layer of striated, and also can be to being configured to Fig. 5 and mesh-shape, the cancellous p post layer of skew shown in Figure 6 implemented.
For example, Fig. 5 illustrates and is configured to cancellous n post layer 3 and p post layer 4b relatively, striated ground alternate configurations the state of surface p post layer 10 and surface n post layer 11.Surface p post layer 10 is connected with p post layer 4b and forms, and is connected (with reference to Fig. 7) with not shown p basic unit 5.
In addition, even as shown in Figure 6, be configured to be offset cancellous n post layer 3 and p post layer 4b also can implement.As shown in Figure 6, striated ground alternate configurations surface p post layer 10 and surface n post layer 11, surface p post layer 10 is connected with p post layer 4b and forms.In addition, surface p post layer 10 is connected with the p basic unit 5 that is arranged to striated.P basic unit 5 be along with the direction setting of surface p post layer 10 and surface n post layer 11 quadrature, and be connected with a plurality of p post layer 4a.Not shown gate electrode is provided with across dielectric film between each p basic unit 5.
Fig. 7 is the stereogram of unit of power MOSFET that the variation of the 1st execution mode schematically is shown.As shown in Figure 5, be configured on cancellous n post layer 3 and p post layer 4a, the 4b, alternate configurations surface p post layer 10 and surface n post layer 11.Surface p post layer 10 forms and is electrically connected the p basic unit 5 and p post layer 4b that striated ground forms.And then, the end of p basic unit 5, with surface p post layer 10 and surface n post layer 11 on, formed gate electrode 9 across dielectric film.In addition, even under the situation of the n post layer 3 of skew mesh-shape ground shown in Figure 6 configuration and p post layer 4b, also be that the mode with the similar shown in Fig. 7 is clear and definite.
In above-mentioned variation, surface p post layer 10 is shown and surface n post layer 11 is the periodic structure of striated, thereby but because as long as p post layer 4 is connected and applies voltage with p basic unit 5 via surface p post layer 10 and exhausts, then also can access same effect, so the plane pattern of surface p post layer 10 is not limited to striated, can also be made as other plane patterns such as clathrate.Accompany with it, the plane pattern of gate electrode can also be made as other patterns such as mesh-shape, skew mesh-shape.
In addition, if than higher concentration the surface n post layer 11 of the impurity that mixed be formed up to the position darker than p basic unit 5, then the bend of p basic unit 5 ends and surface n post layer 11 join, and produce electric field in p basic unit 5 ends and concentrate, and have the problem of withstand voltage reduction.Therefore, surface n post layer 11 preferably is formed up to the position more shallow than p basic unit 5 from the surfaces of semiconductor substrate 21.Thus, can prevent withstand voltage reduction, also further diminish, so increase that can the suppressor electric leakage, the change of gate threshold voltage etc. and obtain high reliability with electric field in the interface of gate insulating film.
Fig. 8 is the schematic diagram that the impurity concentration of the section of unit of power MOSFET of variation of the 1st execution mode and each post layer is shown.As shown in the figure, under a fairly large number of situation of the p of the central portion that is disposed at gate electrode 9 post layer 4b, change continuously, can suppress to produce the charge unbalance of SJ structure, obtain stable high withstand voltage by the impurity concentration that makes each post layer.As mentioned above, in the SJ structure, balance when the charge depletion of adjacent post layer need become high resistance in fact.That is, p post layer is equated with the impurity concentration of n post layer, if this balance is destroyed, then withstand voltage reduction.Therefore, as shown in the figure, set the concentration that the impurity concentration that makes each post layer becomes the centre of mutually adjacent post layer for, gate electrode 9 times, so that the impurity concentration continually varying mode of each post interlayer forms the SJ structure.Thus, on one side can keep charge balance with adjacent post layer,, reduce conducting resistance Yi Bian improve the concentration of the post layer of central portion.On the other hand, the sustaining voltage of gate insulating film 8 is owing to proportional with thickness, so the change in concentration of preferred and post layer makes the thickness of gate insulating film 8 also be varied at the central portion of gate electrode 9 thick accordingly.
(the 2nd execution mode)
Fig. 9 is the schematic diagram that the impurity concentration of the section of unit of power MOSFET of the 2nd execution mode of the present invention and p post layer is shown.
In the structure of present embodiment, the impurity concentration of p post layer 4a, 4b changes at depth direction.As shown in the figure, the impurity concentration of p post layer 4a, 4b is higher in source electrode 7 sides (face side of semiconductor substrate 21), and is lower in drain electrode 1 side (rear side of semiconductor substrate 21).In addition, in source electrode 7 sides, near the impurity concentration height of the n post layer 3 that connects, in drain electrode 1 side, near the impurity concentration of the n post layer 3 that connects low.And then, make at concentration difference Δ N2, Δ N4 between the n post layer 3 of the p of the central portion under the gate electrode 9 post layer 4b and adjacency less than concentration difference Δ N1, Δ N3 between the n post layer 3 of p post layer 4a that is connected to p basic unit 5 and adjacency.
In being connected to the p post layer 4a of p basic unit 5, by increasing Δ N1, Δ N3, the electric field of the upper and lower side of SJ structure diminishes.Thus, even when avalanche breakdown, produced a large amount of charge carriers, also be difficult to produce negative resistance, and can realize the avalanche capability higher than the central portion under the gate electrode 9.
On the other hand, discharge to source electrode 7 via p basic unit 5 in the hole of the generation of the central portion under gate electrode 9.Therefore, the discharge path in hole is longer, and discharge resistance is higher.Therefore, if because avalanche breakdown and central portion under gate electrode 9 has produced a large amount of charge carriers, then the hole is difficult for being discharged from, and becomes the state that avalanche capability is easy to reduce.
Therefore, in the present embodiment, Δ N2, the Δ N4 by making p post layer 4b is less than Δ N1, the Δ N3 of p post layer 4a, and the central portion under gate electrode 9 is difficult for causing avalanche breakdown.That is, be made as just down, cause avalanche breakdown energetically, can be used as the whole high avalanche capability that realizes in the p basic unit 5 of having improved avalanche capability.
In addition, for impurity concentration Nn1, the Nn2 of n post layer 3, make the concentration Nn2 of the central portion under the gate electrode 9 be higher than concentration Nn1 with the n post layer 3 of the p post layer 4a adjacency of p basic unit 5 under just.It is that its purpose is to reduce conducting resistance according to the structure of above-mentioned the 1st execution mode (with reference to Fig. 1) structure.
Figure 10 illustrates the section of unit of power MOSFET of variation of above-mentioned the 2nd execution mode and the schematic diagram of impurities concentration distribution.In execution mode shown in Figure 9, show the example that the impurity concentration of p post layer 4a, 4b changes, even but p post layer 4a, 4b and n post layer 3 this two side's impurity concentration is changed, also obtain same effect.
In the present embodiment, the impurity concentration of p post layer 4a, 4b is higher in source electrode 7 sides, and is lower in drain electrode 1 side.On the other hand, the impurity concentration of n post layer 3 is lower in source electrode 7 sides, and is higher in drain electrode 1 side.Thus, the electric field of upper and lower side that can make the SJ structure is less than execution mode shown in Figure 9, and improves avalanche capability.In addition, in the present embodiment, also make at concentration difference Δ N2, Δ N4 between the n post layer 3 of the p of the central portion under the gate electrode 9 post layer 4b and adjacency less than concentration difference Δ N1, Δ N3 between the n post layer 3 of p post layer 4a and adjacency.Thus, can be made as in p basic unit 5 and just down avalanche current is flow through energetically, and realize high avalanche capability.
(the 3rd execution mode)
Figure 11 is the schematic diagram of section of unit that the power MOSFET of the 3rd execution mode of the present invention is shown.Cross-section structure shown in the figure illustrates the SJ structure applications of the p post layer that for example will have mesh-shape ground shown in Figure 5 configuration and n post layer in the section of the device of MOSFET shown in Figure 1.In addition, the profile shown in the figure illustrates the A-A section (with reference to Fig. 5) with section quadrature shown in Figure 1.
In the present embodiment, form groove 25, imbed with gate insulating film 8 and gate electrode 9 in the groove 25 in the both sides of p post layer 4.If gate electrode 9 is applied voltage, then accumulate raceway groove in the gate insulating film 8 and the interface formation of n post layer 3.Thus, can reduce, can reduce conducting resistance at spreading resistance from the electronics of n source layer 6.
In addition, as the distinctive effect of slot grid structure, the electrode sectional area becomes the part size that is embedded to groove 25 greatly, so the built-in gate resistance of gate electrode 9 is lowered.Thus, the uniformity of the gate voltage in the chip improves, and can realize the high speed of switching speed.
And then, in the part 25a that is clamped by groove 25 and p post layer 4 shown in Figure 12, except the depletion layer that extends from p post layer 4, also extend depletion layer from gate insulating film 8.Therefore, this part 25a integral body is easy to exhaust and the electric field reduction, so compare with the situation that does not form groove 25, obtains high withstand voltage.Therefore, as shown in the figure, the impurity concentration of n post layer 3 of the part 25a that has formed groove and the impurity concentration of p post layer 4 can be improved, lower conducting resistance can be realized.
In addition, can also the p post layer 4 and the impurity concentration of the depth direction of n post layer 3 be changed, and obtain high avalanche capability as shown in figure 13.Promptly, with the situation of above-mentioned execution mode 2 in the same manner, make the concentration of p post layer 4 be higher than the concentration of n post layer 3 in source electrode 7 sides, make the concentration of n post layer 3 be higher than the concentration of p post layer 4 in drain electrode 1 side, thereby can reduce the electric field of the upper and lower side of super-junction structure, and realize high avalanche capability.
(the 4th execution mode)
Figure 14 is the schematic diagram that the Impurity Distribution of the section of power MOSFET of the 4th execution mode of the present invention and SJ structure is shown.The structure of the part that is formed with p basic unit 5 shown in the figure is identical with the structure shown in above-mentioned the 1st execution mode and the 2nd execution mode.In the present embodiment, the guard ring shown in the central authorities of figure 12 is formed on grid pad 13 (grid extraction electrode) periphery.Protect circular layer 12 deeper to form by making than p basic unit 5, thus the hole that produces in the n post layer 3 of discharging apace in adjacency, the avalanche capability of the periphery of raising grid pad 13.
On the other hand, in the structure shown in the figure, if cause avalanche breakdown in the SJ structure under grid pad 13, then the discharge path in hole is longer, so avalanche capability reduces easily.Therefore, be made as protection circular layer 12 is also extended to zone under the grid pad 13, carry out the discharge in hole smoothly, thereby can also improve the avalanche capability under the grid pad 13.In addition, in order to increase withstand voltage under the grid pad 13, preferably shown in the Impurity Distribution among the figure, make the impurity concentration of the post layer under the grid pad 13 lower than other regional post layers.
In addition,, make the impurity concentration of protecting the p post layer 4c under the circular layer 12, avalanche breakdown can obtain high avalanche capability thereby discharge causing energetically just down of the little protection circular layer 12 of resistance in the hole than the p post layer 4a height under the p basic unit 5 by as shown in figure 15.
(the 5th execution mode)
Figure 16 is the schematic diagram of section that the power MOSFET of the 5th execution mode of the present invention is shown.Present embodiment relates to the device architecture that comprises the device terminal part.
In device architecture as shown in the figure, the structure of device area that is formed with p basic unit 5 and gate electrode 9 is identical with above-mentioned the 1st execution mode and the 2nd execution mode.On the other hand, in the terminal area of device, have the withstand voltage structure higher than the device area of device central authorities in order to obtain the high device of reliability, need to be made as.Therefore, as shown in the figure, in the terminal area under field insulating membrane 15, do not form the SJ structure, and form high resistance n as the 9th semiconductor layer
-Layer 16.Thus, the withstand voltage unbalanced influence that can not be subjected to the impurity concentration of SJ structure of terminal area forms to by high resistance n
-It is withstand voltage that the avalanche capability of layer 16 determines.And then, in the periphery of device area,, and be formed with protection circular layer 12 than dark conduct the 8th semiconductor layer of p basic unit 5 for the electric field of the end that suppresses p basic unit 5 is concentrated.Thus, the hole that produces in the terminal area is discharged energetically via protection circular layer 12, so can obtain high avalanche capability, answer tolerance.In addition, for the electric field of end of field insulating membrane 15 sides that relax protection circular layer 12, and at high resistance n
-Layer 16 surface have formed a plurality of the 2nd protection circular layers 14 as the 10th semiconductor layer.
And then, preferably make the p post layer 4c of the outermost p post layer 4d relative inner of SJ structure become the thin layer impurity concentration of half.Wherein, owing to be formed with high resistance n in the outside of SJ structure
-Layer 16 is easy to extend to high resistance n-layer 16 so become depletion layer, and is difficult to the structure to the extension of SJ structure side.Be doped to high resistance n
-Impurity in the layer 16 is compared seldom with n post layer 3.Therefore, the outermost p post of SJ structure layer 4d will and the n post layer 3 of the adjacency of SJ structure side between obtain charge balance.Therefore, if the thin layer concentration of outermost p post layer 4d does not form half of p post layer 4c of adjacency, the destroyed and withstand voltage reduction of the charge balance when then exhausting.
In addition, preferably in outermost border, form a termination n layer 17, do not reach line of cut so that extend to the depletion layer of terminal area.The field stops n layer 17 and can inject by carrying out ion simultaneously with n post layer 3, and easily forms.And then, as shown in figure 17, can also be made as the impurity concentration that makes the outermost p post layer 4d under the protection circular layer 12 and be higher than the p post layer 4a under the p basic unit 5 and cause avalanche breakdown for 12 times energetically, and obtain high avalanche capability at the hole little protection circular layer of discharge resistance.
Except above-mentioned execution mode; as long as use terminal structures such as RESURF (REduced SURfaceField: reduce surface field) structure, an effect electroplax structure; and form dark protection circular layer 12 in the device area periphery, then can realize high withstand voltageization of terminal part.
(the 6th execution mode)
Figure 18 is the profile of structure that the power MOSFET of the 6th execution mode schematically is shown.The thickness that power MOSFET shown in Figure 180 has gate insulating film 8 is made as constant planar gate structure.In above-mentioned power MOSFET shown in Figure 1, use the central portion of the gate electrode 9 between p basic unit 5, thicker TERRACE GATE (terraced steps grid) structure that is provided with gate insulating film 8.The power MOSFET of present embodiment is on this aspect of planar gate structure in the structure of gate electrode, and different with power MOSFET shown in Figure 1, other structures are identical.
In the power MOSFET of present embodiment, also with power MOSFET shown in Figure 1 in the same manner, can reduce switching noise, and then, can reduce conducting resistance and realize the densification of leakage current.
For example, if to applying high voltage between drain electrode 1 and the source electrode 7, and surface p post layer 10 exhausts, then the p basic unit 5 and the disappearance that is electrically connected between the p post layer 4b under the gate electrode 9.Thus, as mentioned above, exhaust successively to p post layer 4b from the p post layer 4a that is positioned under the p basic unit 5, so the inclination of Cds-Vds characteristic slows down.Thus, the dVds/dt during switch diminishes, and can reduce switching noise.
In addition, similarly, surface p post layer 10 exhausts under conducting state.Therefore, depletion layer is difficult to extend towards the n of adjacency post layer 3b from the p post layer 4b that is positioned under the gate electrode 9.Thus, can not narrow down as the width of the n post layer 3b of current channel, the saturation current density of leakage current becomes big and can realize the high current density action.
And then, it is not the TERRACE GATE shown in Fig. 1 (terraced steps grid) structure, but, accumulate raceway groove thereby between surface n post layer 11 and gate insulating film 8, form by being made as planar gate structure, can realize the conducting resistance lower than power MOSFET shown in Figure 1.
In order to be easy to obtain above-mentioned effect, as shown in Figure 3, can make the impurity concentration of surface p post layer 10, become lower with comparing under the central part of gate electrode 9 near the part of p basic unit 5.In addition, as long as under the central part of gate electrode 9, the impurity concentration of surface n post layer 11 is higher than surface p post layer 10, then can access same effect.For example, between p basic unit 5, change, can under the central part of gate electrode 9, make the impurity concentration of surface n post layer 11 be higher than surface p post layer 10 by the impurity concentration that makes surface n post layer 11.That is, can be made as under the central part of gate electrode 9, have the impurity concentration that makes surface n post layer 11 and be higher than CONCENTRATION DISTRIBUTION near the impurity concentration of the part of p basic unit 5.
And, by shown in Fig. 9 and 10, make p post layer 4b under the gate electrode 9 and the concentration difference between the n post layer 3b less than the concentration difference between p post layer 4a under the p basic unit 5 and the n post layer 3a, can realize withstand voltage high withstand voltageization of cut-off state.Thus, as shown in figure 18, can the concentration of n post layer 3b and p post layer 4b be improved, can reduce conducting resistance at gate electrode.In Fig. 9 and 10, show the distribution that between n post layer 3 and p post layer 4, has concentration difference, but for example, can also be gate electrode 9 times, be made as identical with the impurity concentration of n post layer 3b the impurity concentration of p post layer 4b.
Figure 19 is the profile of structure of power MOSFET that the variation of the 6th execution mode schematically is shown.As shown in the drawing, become TERRACEGATE (terraced steps grid) structure of a part of having thickeied gate insulating film 8.
In the power MOSFET of this variation, be the structure of the impurity concentration that improved the n post layer 3b under the thicker gate insulating film 8b that must be provided with.Thus, can be made as the conducting resistance lower than power MOSFET shown in Figure 180.Shown in this variation, the ground thickening of gate insulating film 8 parts is being kept under the withstand voltage situation, can make the concentration of the n post layer 3 corresponding be higher than the concentration of the n post layer 3b under the central authorities of gate electrode 9 of power MOSFET shown in Figure 180 with the thick part of gate insulating film 8.And then, in order to obtain charge balance, also improve the concentration of the p post layer 4b of adjacency.
(the 7th execution mode)
Figure 20 is the schematic diagram of planar configuration that the semiconductor layer of the power semiconductor device that constitutes the 7th execution mode is shown, and the configuration of p post layer 4 and p basic unit 5 is shown.In the present embodiment, as shown in the drawing, the p post layer 4 of point-like is configured to clathrate with the cycle of regulation respectively with p basic unit 5.In addition, the section of representing with B-B in the figure for example can be made as cross-section structure shown in Figure 180.Surface in p basic unit 5 is provided with n source layer 6, and then, under p basic unit, dispose p post layer 4a.
About in Figure 20 and in the horizontal periodic width, it is wideer than the periodic width that disposes p post layer 4 to dispose the periodic width of p basic unit 5.And not shown gate electrode 9 is arranged to clathrate in the mode that covers between the p basic unit 5.In addition, be connected with each p basic unit 5 via surface p post layer 10 with the not direct-connected p post layer 4b of p basic unit 5.On the other hand, in by surface p post layer 10 area surrounded,, be provided with not shown surface n post layer 11 with n post layer 3 and p post layer 4b ground connection mutually.Thus, surface p post layer 10 becomes the structure that laterally is being arranged alternately with surface n post layer.
In planar configuration as shown in Figure 20, surface p post layer 10 also exhausts, and blocking being electrically connected between the p post layer 4b under the gate electrode 9 and p basic unit 5.Thus, similarly reduce switching noise with above-mentioned execution mode.In addition, with p basic unit 5 between be electrically connected among the p post layer 4b that is interdicted, the expansion of depletion layer is suppressed, so the current channel in the n post layer 3 can not narrow down, and can realize the reduction of conducting resistance.
And then, in the central area (under the central part of gate electrode 9) that is surrounded by four p basic units 5 shown in Figure 20, can establish the impurity concentration of n post layer 3 higher, so can reduce conducting resistance.Therefore, can increase maximum leakage current, and realize the high current density action.
In addition, for example, compare striated, can relatively increase the area of not shown gate electrode 9 with the structure that p basic unit 5, gate electrode 9 are set as the 1st execution mode of Fig. 2～shown in Figure 4.Thus, can increase the n post layer 3 of the high concentrationization that is configured under the gate electrode 9, thus with striated p basic unit 5, gate electrode 9 be set structure compare, can reduce conducting resistance.
And then if be made as the configuration of surface p post layer 10 as shown in Figure 20, then more near p basic unit 5, the interval of adjacent surface p post layer 10 is narrow more.Thus, can near the zone of p basic unit 5, relatively improve the concentration of surface n post layer 11 and surface p post layer 10.More near p basic unit 5, current density is high more under conducting state.Therefore, if near the zone of p basic unit 5, improve surface n post layer 11 concentration, then can further reduce conducting resistance.
Possess that applied grid structure is not limited to specific mos gate structure in the power MOSFET of configuration of p post layer 4 shown in Figure 20 and p basic unit 5, and can also application drawing 1 and TERRACE GATE as shown in Figure 19 (terraced steps grid) structure.In addition, also can be planar gate structure shown in Figure 180.
Figure 21～Figure 23 is the vertical view that the configuration of the p post layer 4 of variation of the 7th execution mode and p basic unit 5 schematically is shown.Can also be made as the dot pattern of horizontal direction skew in the figure with the configuration of p post layer 4 and p basic unit 5 as shown in figure 21.
In p post layer 4 and p basic unit 5 shown in Figure 21, the p post layer 4 of point-like and the arrangement of p basic unit 5 are provided with at each change phase place of each arrangement.In the example in the figure, become for a change the staggered configuration of the phase place of horizontal direction.In addition, the p post layer 4 that is configured between the adjacent p basic unit 5 is electrically connected with a plurality of p basic unit 4 via surperficial post layer 11.
In addition, p post layer 4 is connected with some p basic unit 5 across surface p post layer 10 and gets final product.Therefore, as Figure 22 and shown in Figure 23, can be configured to surface p post layer 10 and connect each p post layer 4 and the p basic unit 5 approaching with each p post layer 4.
In the configuration of p post layer 4 shown in Figure 22 and p basic unit 5, the p post layer 4 that is configured between the adjacent p basic unit 5 only is connected with the p basic unit 5 of vicinity via surface p post layer 10.Therefore, under the central part that is arranged at the not shown gate electrode between the adjacent p basic unit 5, be formed with the zone that surface p post layer 10 is not set.On the other hand, in the zone that surface p post layer 10 is not set, surface n post layer 11 can be set.Therefore, the area of surface n post layer 11 is increased relatively, can further reduce conducting resistance.Become around p basic unit 5, laterally alternate configurations the surface p post layer 10 that is connected with p basic unit 5 and the structure that is arranged at the surface n post layer 11 between the surface p post layer 10.
In variation shown in Figure 23, p post layer 4 and p basic unit 5 be arranged as with Figure 21 similarly, changed the staggered configuration of the phase place of horizontal direction.Be connected by surface p post layer 10 between the p post layer 4b that closely disposes with each p basic unit 5 and each p basic unit 5.In addition, between each p basic unit 5 than p post layer 4b further from the position p post layer 4c respectively and contiguous a plurality of p basic unit 5 between, connect by surface p post layer 10.In such structure, also by with surface p post layer 10 area surrounded that p post layer 4c is connected with p basic unit 5 in be provided with surface n post layer 11.Therefore, and surface p post layer 10 between laterally alternately disposed surface n post layer 11.
Even as shown in Figure 23 p post layer 4 and p basic unit 5 also can form the zone that surface p post layer 10 is not set at the central part that is arranged at the gate electrode between the adjacent p basic unit 5.Therefore, the area of not shown surface n post layer 11 is increased relatively, can reduce conducting resistance.
And then Figure 22 and structure shown in Figure 23 can also be applied to Fig. 1 and the p post layer 4 with striated as shown in Figure 18 and the structure of n post layer 3.For example, in Figure 18, can constitute by the part that the part of the surface p post layer 10 that will join with the surface of n post layer 3b is replaced by surface n post layer 11.
(the 8th execution mode)
Figure 24 is the vertical view of gate electrode 9 and the relation of surface n post layer 11 and surface p post layer 10 that the power MOSFET of the 8th execution mode schematically is shown.
As shown in figure 24, gate electrode 9 presents the flat shape of the ladder shape with peristome 27.In addition, when being provided with gate electrode 9 between adjacent p basic unit 5, the peristome 27 that becomes gate electrode 9 is positioned on the surface p post layer 10, and gate electrode 9 is arranged on the structure on the surface n post layer 11.
For example, in Fig. 1～4 and execution mode shown in Figure 180, the effect of the conducting resistance that is reduced.But, and if the area of gate electrode 9 increase capacitor C gd between grid leak accordingly, then switching loss increases.Therefore,, the peristome 11 of gate electrode 9 is set on surface p post layer 10, can reduces Cgd by as shown in figure 24.
On the other hand, owing on surface n post layer 11, be provided with gate electrode 9, accumulate raceway groove so between gate insulating film 8 and surface n post layer 11, form as mentioned above.Therefore, can keep the effect that reduces conducting resistance, and reduce Cgd.
Figure 25 be gate electrode 9 that the power MOSFET of modified embodiment of the present embodiment schematically is shown, with the vertical view of the relation of surface n post layer 11 and surface p post layer 10.In variation shown in Figure 25, peristome 27 is arranged on the surface p post layer 10 of a part.In execution mode shown in Figure 24, on all surface p post layer 10, be provided with the peristome 27 of gate electrode 9.With respect to this, by as shown in figure 25, change the quantity that is arranged on the peristome 27 on the surface p post layer 10, can adjust the value of Cgd.
(the 9th execution mode)
Figure 26 is the profile of structure that the power MOSFET of the 9th execution mode schematically is shown.The power MOSFET of present embodiment has TERRACE GATE (terraced steps grid) structure identical with power MOSFET shown in Figure 8, possesses a plurality of p post layers 4 and n post layer 3 between two p basic units 5.On the other hand, in the power MOSFET of present embodiment, at the central portion that is arranged at two gate electrodes 9 between the p basic unit 5, the end of drop ply 2 sides of the p post layer 4 that is connected with surface p post layer 10 and the interval between the drop ply 2 are greater than the end of drop ply 2 sides of the p post layer 4 that is provided with p basic unit 5 on the surface and the interval between the drop ply 2.That is, shoal from the degree of depth of surface p post layer 10 towards the p of the direction of drop ply 2 post layer 4.
By using TERRACE GATE (terraced steps grid) structure shown in Figure 26, as mentioned above, at the central portion of the thick gate electrode 9 of gate insulating film 8, the voltage that gate insulating film 8 keeps uprises.Its result can reduce the voltage that the SJ structure should keep relatively, can reduce the SJ thickness of structure.That is, can also be as shown in figure 26, be provided with the degree of depth of p post layer 4 more shallow.Thus, obtain with at the central portion of gate electrode 9, reduced the identical effect of situation of the thickness of drift layer, can reduce conducting resistance.In addition, as shown in figure 26,, can further reduce conducting resistance by making up with the impurity concentration of p post layer 4 and n post layer 3 and from the change in concentration of p basic unit 5 sides towards the direction increase of the central portion of gate electrode 9.
Figure 27 is the profile of structure that the power MOSFET of modified embodiment of the present embodiment schematically is shown.In this variation, under the central portion that is arranged at two gate electrodes 9 between the p basic unit 5, have super knot layer 22 structure that is dug into from the surface.That is, become the thickness that makes from the interface of surface p post layer 10 and gate insulating film 8 drop ply 2 less than from the surface of the p basic unit 5 that is connected with source electrode 7 to the thickness of 2 of drop plies, reduce the structure of conducting resistance.
On the other hand, compare with a side of p basic unit 5, the central portion of gate electrode 9 more heavy back gate insulating film 8 is set, the voltage that gate insulating film 8 can keep uprises relatively at the central portion of gate electrode 9.Therefore, can compensate the SJ structure thin and the amount of withstand voltage reduction, reduce conducting resistance so can not reduce withstand voltage.
More than, the 1st to the 5th execution mode of the present invention has been described, but has the invention is not restricted to above-mentioned execution mode.For example, though the 1st conductivity type is made as the n type, the 2nd conductivity type is made as the p type and is illustrated, also the 1st conductivity type can be made as the p type, the 2nd conductivity type is made as the n type implements.
For example, the formation method of super-junction structure is not limited to said method, except the repeated multiple times ion inject with epitaxially grown, method that can also be by imbedding growth having formed groove after, the whole bag of tricks such as method that oppose side wall carries out the ion injection after having formed groove are implemented.
In addition, for p post layer 4, show not and n
+The structure that drop ply 2 joins is even but join and also can implement.And then in addition, even at p post layer 4 and n
+Formed the low n of concentration ratio n post layer 3 between the drop ply 2
-Layer also can be implemented.
In addition, the MOSFET that has used silicon (Si) as semi-conducting material has been described, but can also have used for example wide bandgap semiconductors such as carborundum (SiC), CaCl2 compound semiconductors such as (GaN), diamond.And then, except MOSFET, can also use loading in mixture in the devices such as device, IGBT of MOSFET and SBD with super-junction structure.
Claims (20)
1. power semiconductor device is characterized in that possessing:
The 1st semiconductor layer of the 1st conductivity type;
The 2nd semiconductor layer of the 1st conductivity type that on above-mentioned the 1st semiconductor layer, laterally is arranged alternately and the 3rd semiconductor layer of the 2nd conductivity type;
Be arranged on the 4th semiconductor layer of the 2nd conductivity type on the surface of above-mentioned the 3rd semiconductor layer;
Optionally be arranged on the 5th semiconductor layer of the 1st conductivity type on the surface of above-mentioned the 4th semiconductor layer;
The 6th semiconductor layer of the 2nd conductivity type that on above-mentioned the 2nd semiconductor layer and the 3rd semiconductor layer, laterally is arranged alternately and the 7th semiconductor layer of the 1st conductivity type;
The 1st main electrode that is electrically connected with above-mentioned the 1st semiconductor layer;
Be arranged on the dielectric film on above-mentioned the 4th semiconductor layer, above-mentioned the 6th semiconductor layer and above-mentioned the 7th semiconductor layer;
Across above-mentioned dielectric film, be arranged on the control electrode on above-mentioned the 4th semiconductor layer, above-mentioned the 6th semiconductor layer and above-mentioned the 7th semiconductor layer; And
With the 2nd main electrode of the surface engagement of above-mentioned the 4th semiconductor layer and above-mentioned the 5th semiconductor layer,
Above-mentioned the 6th semiconductor layer is connected with above-mentioned the 4th semiconductor layer, and then is connected with at least one above-mentioned the 3rd semiconductor layer that is provided with between two above-mentioned the 4th semiconductor layers,
The impurity concentration that is arranged on above-mentioned the 3rd semiconductor layer under above-mentioned the 6th semiconductor layer is higher than the impurity concentration that is arranged on above-mentioned the 3rd semiconductor layer under above-mentioned the 4th semiconductor layer.
2. power semiconductor device according to claim 1 is characterized in that:
Above-mentioned dielectric film is thicker relatively on the 3rd semiconductor layer that is arranged under above-mentioned the 6th semiconductor layer, and is thinner relatively on above-mentioned the 4th semiconductor layer.
3. power semiconductor device according to claim 1 is characterized in that:
Under the central part of the above-mentioned control electrode between two above-mentioned the 4th semiconductor layers, the impurity concentration of above-mentioned the 7th semiconductor layer is higher than the impurity concentration of above-mentioned the 6th semiconductor layer.
4. power semiconductor device according to claim 1 is characterized in that:
The periodic width of the configuration of above-mentioned above-mentioned the 6th semiconductor layer that is arranged alternately and above-mentioned the 7th semiconductor layer is narrower than the periodic width of the configuration of above-mentioned above-mentioned the 2nd semiconductor layer that is arranged alternately and above-mentioned the 3rd semiconductor layer.
5. power semiconductor device according to claim 1 is characterized in that:
The impurity concentration of above-mentioned the 3rd semiconductor layer is higher than the impurity concentration of above-mentioned the 2nd semiconductor layer of adjacency in above-mentioned the 2nd main electrode one side, in above-mentioned the 1st main electrode one side, is lower than the impurity concentration of above-mentioned the 2nd semiconductor layer of adjacency.
6. power semiconductor device according to claim 5 is characterized in that:
The difference of the impurity concentration of above-mentioned the 2nd semiconductor layer of the impurity concentration of above-mentioned the 3rd semiconductor layer and adjacency is bigger under above-mentioned the 4th semiconductor layer, and is less under above-mentioned the 6th semiconductor layer.
7. power semiconductor device according to claim 1 is characterized in that:
Have the surface that optionally is arranged on above-mentioned the 3rd semiconductor layer, and the 8th semiconductor layer of the 2nd conductivity type that is electrically connected with above-mentioned the 2nd main electrode,
Dark from the surface that joins with above-mentioned the 2nd main electrode of above-mentioned the 4th semiconductor layer from the surface that joins with above-mentioned the 2nd main electrode of above-mentioned the 8th semiconductor layer towards the degree of depth of the direction of above-mentioned the 1st semiconductor layer towards the depth ratio of the direction of above-mentioned the 1st semiconductor layer.
8. power semiconductor device according to claim 7 is characterized in that also possessing:
Dispose the device area of above-mentioned the 4th semiconductor layer; And the terminal area that is arranged on the end of above-mentioned device area,
Above-mentioned the 8th semiconductor layer is arranged on the periphery of above-mentioned device area.
9. power semiconductor device according to claim 7 is characterized in that:
The impurity concentration that is provided with above-mentioned the 3rd semiconductor layer of above-mentioned the 8th semiconductor layer on the surface is higher than the impurity concentration that is provided with above-mentioned the 3rd semiconductor layer of above-mentioned the 4th semiconductor layer on the surface.
10. power semiconductor device according to claim 1 is characterized in that:
Be configured in the 2nd the highest semiconductor layer of impurity concentration in a plurality of above-mentioned the 2nd semiconductor layer between two above-mentioned the 4th semiconductor layers and above-mentioned the 3rd semiconductor layer or the 3rd semiconductor layer and be arranged at central authorities between above-mentioned two the 4th semiconductor layers,
Have above-mentioned the 2nd semiconductor layer of the highest impurity concentration or the 3rd semiconductor layer, and the impurity concentration that is provided with above-mentioned the 2nd semiconductor layer that is provided with between above-mentioned the 3rd semiconductor layer of above-mentioned the 4th semiconductor layer and above-mentioned the 3rd semiconductor layer on the surface be median in the impurity concentration of the 2nd semiconductor layer of separately both sides adjacency or the 3rd semiconductor layer.
11. power semiconductor device according to claim 1 is characterized in that, also possesses:
Dispose the device area of above-mentioned the 4th semiconductor layer; And the terminal area that is arranged on the end of above-mentioned device area,
Above-mentioned the 2nd semiconductor layer and above-mentioned the 3rd semiconductor layer are arranged on above-mentioned device area,
The 9th semiconductor layer of the 1st conductivity type that impurity concentration is lower than above-mentioned the 2nd semiconductor layer is communicated to above-mentioned the 1st semiconductor layer from the surface of above-mentioned terminal area and is formed on the border of above-mentioned device area and above-mentioned terminal area.
12. power semiconductor device according to claim 11 is characterized in that:
On the surface of above-mentioned the 9th semiconductor layer, be provided with the 10th semiconductor layer of the 2nd conductivity type more than at least 1.
13. power semiconductor device according to claim 1 is characterized in that:
Above-mentioned the 4th semiconductor layer, above-mentioned the 6th semiconductor layer, above-mentioned the 7th semiconductor layer and above-mentioned control electrode are formed by striated ground,
Above-mentioned the 4th semiconductor layer and above-mentioned the 7th semiconductor layer quadrature.
14. power semiconductor device according to claim 13 is characterized in that:
Above-mentioned the 3rd semiconductor layer is arranged to and the parallel striated of above-mentioned the 4th semiconductor layer.
15. power semiconductor device according to claim 13 is characterized in that:
Above-mentioned the 2nd semiconductor layer is arranged to mesh-shape or skew mesh-shape.
16. power semiconductor device according to claim 1 is characterized in that:
Above-mentioned the 3rd semiconductor layer and above-mentioned the 4th semiconductor layer are arranged to the some shape of clathrate ground configuration or have been changed the some shape that disposes of phase place at each arrangement staggeredly.
17. power semiconductor device according to claim 1 is characterized in that:
Above-mentioned the 6th semiconductor layer be arranged to be spaced from each other above-mentioned the 3rd semiconductor layer that disposes between a plurality of above-mentioned the 4th semiconductor layer that the compartment of terrain is provided with, with one that is configured in a plurality of above-mentioned the 4th semiconductor layer of the nearest position of above-mentioned the 3rd semiconductor layer between be connected.
18. power semiconductor device according to claim 1 is characterized in that:
Above-mentioned control electrode has opening on above-mentioned the 6th semiconductor layer.
19. power semiconductor device according to claim 1 is characterized in that:
Under the central portion that is arranged at two above-mentioned control electrodes between above-mentioned the 4th semiconductor layer, the end of above-mentioned the 1st semiconductor layer side of above-mentioned the 3rd semiconductor layer that above-mentioned the 6th semiconductor layer connects and the interval between above-mentioned the 1st semiconductor layer are greater than the end of above-mentioned the 1st semiconductor layer side of above-mentioned the 3rd semiconductor layer that is provided with above-mentioned the 4th semiconductor layer on the surface and the interval between above-mentioned the 1st semiconductor layer.
20. power semiconductor device according to claim 1 is characterized in that:
Under the central portion that is arranged at two above-mentioned control electrodes between above-mentioned the 4th semiconductor layer, from the interface of above-mentioned the 6th semiconductor layer and above-mentioned dielectric film to the thickness of above-mentioned the 1st semiconductor layer less than from the surface of above-mentioned the 4th semiconductor layer that is connected with above-mentioned the 2nd main electrode to the thickness of above-mentioned the 1st semiconductor layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009-138270 | 2009-06-09 | ||
| JP2009138270 | 2009-06-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101924132A true CN101924132A (en) | 2010-12-22 |
| CN101924132B CN101924132B (en) | 2013-05-01 |
Family
ID=43338913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010144886 Expired - Fee Related CN101924132B (en) | 2009-06-09 | 2010-03-18 | Semiconductor device for power |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101924132B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102694027A (en) * | 2012-01-13 | 2012-09-26 | 西安龙腾新能源科技发展有限公司 | Non-equilibrium junction terminal structure for super-junction device |
| CN103493207A (en) * | 2011-07-14 | 2014-01-01 | 富士电机株式会社 | High-voltage semiconductor device |
| CN103996705A (en) * | 2013-02-18 | 2014-08-20 | 英飞凌科技奥地利有限公司 | Semiconductor device with a super junction structure having a vertical impurity distribution |
| CN104009084A (en) * | 2013-02-21 | 2014-08-27 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device with a nominal breakdown voltage in a cell area |
| CN104347699A (en) * | 2013-08-05 | 2015-02-11 | 首尔半导体株式会社 | Nitride-based field-effect transistor and method of fabricating the same |
| CN107819025A (en) * | 2016-09-14 | 2018-03-20 | 富士电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN108376713A (en) * | 2018-02-13 | 2018-08-07 | 王振海 | A kind of semiconductor devices and preparation method thereof with super-junction structure |
| CN111969040A (en) * | 2020-08-26 | 2020-11-20 | 电子科技大学 | Super junction MOSFET |
| CN112786706A (en) * | 2016-08-25 | 2021-05-11 | 英飞凌科技奥地利有限公司 | Transistor device with high avalanche robustness |
| CN113646895A (en) * | 2019-04-11 | 2021-11-12 | 三菱电机株式会社 | Semiconductor device and power conversion device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030008483A1 (en) * | 1999-10-21 | 2003-01-09 | Fuji Electric, Co., Ltd. | Super-junction semiconductor device and the method of manufacturing the same |
| US20030148559A1 (en) * | 1999-10-20 | 2003-08-07 | Fuji Electric, Co., Ltd. | Semiconductor device and the method of manufacturing the same |
| US20080246085A1 (en) * | 2007-04-03 | 2008-10-09 | Kabushiki Kaisha Toshiba | Power semiconductor device |
-
2010
- 2010-03-18 CN CN 201010144886 patent/CN101924132B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030148559A1 (en) * | 1999-10-20 | 2003-08-07 | Fuji Electric, Co., Ltd. | Semiconductor device and the method of manufacturing the same |
| US20030008483A1 (en) * | 1999-10-21 | 2003-01-09 | Fuji Electric, Co., Ltd. | Super-junction semiconductor device and the method of manufacturing the same |
| US20080246085A1 (en) * | 2007-04-03 | 2008-10-09 | Kabushiki Kaisha Toshiba | Power semiconductor device |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103493207A (en) * | 2011-07-14 | 2014-01-01 | 富士电机株式会社 | High-voltage semiconductor device |
| CN103493207B (en) * | 2011-07-14 | 2016-03-09 | 富士电机株式会社 | High-voltage semiconductor device |
| CN102694027A (en) * | 2012-01-13 | 2012-09-26 | 西安龙腾新能源科技发展有限公司 | Non-equilibrium junction terminal structure for super-junction device |
| CN102694027B (en) * | 2012-01-13 | 2015-08-19 | 西安龙腾新能源科技发展有限公司 | The non-equilibrium junction termination structures of superjunction devices |
| US9825127B2 (en) | 2013-02-18 | 2017-11-21 | Infineon Technologies Austria Ag | Super junction semiconductor device with field extension zones |
| CN103996705A (en) * | 2013-02-18 | 2014-08-20 | 英飞凌科技奥地利有限公司 | Semiconductor device with a super junction structure having a vertical impurity distribution |
| CN103996705B (en) * | 2013-02-18 | 2017-09-01 | 英飞凌科技奥地利有限公司 | Semiconductor devices with the super-junction structures with vertical Impurity Distribution |
| CN104009084A (en) * | 2013-02-21 | 2014-08-27 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device with a nominal breakdown voltage in a cell area |
| US9515137B2 (en) | 2013-02-21 | 2016-12-06 | Infineon Technologies Austria Ag | Super junction semiconductor device with a nominal breakdown voltage in a cell area |
| CN104009084B (en) * | 2013-02-21 | 2017-04-12 | 英飞凌科技奥地利有限公司 | Super junction semiconductor device with a nominal breakdown voltage in a cell area |
| CN104347699A (en) * | 2013-08-05 | 2015-02-11 | 首尔半导体株式会社 | Nitride-based field-effect transistor and method of fabricating the same |
| CN112786706A (en) * | 2016-08-25 | 2021-05-11 | 英飞凌科技奥地利有限公司 | Transistor device with high avalanche robustness |
| CN107819025A (en) * | 2016-09-14 | 2018-03-20 | 富士电机株式会社 | The manufacture method of semiconductor device and semiconductor device |
| CN108376713A (en) * | 2018-02-13 | 2018-08-07 | 王振海 | A kind of semiconductor devices and preparation method thereof with super-junction structure |
| CN108376713B (en) * | 2018-02-13 | 2021-01-15 | 汇佳网（天津）科技有限公司 | Semiconductor device with super junction structure and manufacturing method thereof |
| CN113646895A (en) * | 2019-04-11 | 2021-11-12 | 三菱电机株式会社 | Semiconductor device and power conversion device |
| CN111969040A (en) * | 2020-08-26 | 2020-11-20 | 电子科技大学 | Super junction MOSFET |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101924132B (en) | 2013-05-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101924132B (en) | Semiconductor device for power | |
| US10157983B2 (en) | Vertical power MOS-gated device with high dopant concentration N-well below P-well and with floating P-islands | |
| US7723783B2 (en) | Semiconductor device | |
| US7642597B2 (en) | Power semiconductor device | |
| JP5612256B2 (en) | Semiconductor device | |
| US9093522B1 (en) | Vertical power MOSFET with planar channel and vertical field plate | |
| US9461127B2 (en) | Vertical power MOSFET having planar channel and its method of fabrication | |
| CN101479851B (en) | Lateral trench gate FET with direct source-drain current path | |
| US8610210B2 (en) | Power semiconductor device and method for manufacturing same | |
| US20170330962A1 (en) | Power mosfet having planar channel, vertical current path, and top drain electrode | |
| EP2937907B1 (en) | Vertical semiconductor device, and method of manufacturing the vertical semiconductor device | |
| US9087893B2 (en) | Superjunction semiconductor device with reduced switching loss | |
| JP3799888B2 (en) | Superjunction semiconductor device and method for manufacturing the same | |
| US20100308399A1 (en) | Power semiconductor device | |
| CN101794816B (en) | Semiconductor device | |
| JP2008117826A (en) | Power semiconductor element | |
| US20080308839A1 (en) | Insulated gate bipolar transistor | |
| CN107275383B (en) | Super junction IGBT containing heterojunction | |
| WO2003044864A1 (en) | Semiconductor Devices | |
| JP2005011846A (en) | Semiconductor device | |
| JP4119148B2 (en) | diode | |
| JP2007311822A (en) | Schottky barrier diode | |
| CN110212018A (en) | Super-junction structure and superjunction devices | |
| WO2018034818A1 (en) | Power mosfet having planar channel, vertical current path, and top drain electrode | |
| CN104576730B (en) | Super-junction device and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130501 Termination date: 20170318 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |