CN101916090A - Unmanned aerial vehicle onboard three-redundancy electrical load management center - Google Patents
Unmanned aerial vehicle onboard three-redundancy electrical load management center Download PDFInfo
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Abstract
The invention relates to an unmanned aerial vehicle onboard three-redundancy electrical load management center which comprises a CPU (Central Processing Unit) module, a state quantity monitoring control module, a synchronizing module, a CCDL (Cross Channel Data Link) module, an analogue quantity collecting and conditioning module, a drive control module, a communication module and a power supply module. The three-redundancy electrical load management center receives a control command of a supervisory computer by the communication module; the synchronizing module is used for finishing synchronization among programs; a load equation is solved according to the control command of the supervisory computer, a voltage-current state of a system power bus bar returned by the analogue quantity collecting and conditioning module and a load state of an SSPC (Solid-State Power Controller) returned by the state quantity monitoring control module so as to form load power distributing commands of an unmanned aerial vehicle in different flight states; the switching among the management centers is finished by the data exchange and the monitoring decision of the CCDL module, and the main-working-redundancy electrical load management center is used for finishing power distribution on a load; and the invention has practical value and wide application prospect in the technical fields of aviation electrical systems and unmanned aerial vehicles.
Description
(1) technical field
The present invention relates to a kind of unmanned aerial vehicle onboard three-redundancy electrical load administrative center, particularly relate to a kind of unmanned aerial vehicle onboard three-redundancy electrical load administrative center based on " DSP+FPGA " structure, it is used for large-scale unmanned aerial vehicle onboard distribution system, its technical characterstic shows as multidisciplinary fusion, relates to aspects such as computer technology, aviation electrical technology, Power Electronic Technique.Belong to aircraft electrical system technology and UAS technical field.
(2) background technology
Since the eighties in 20th century, along with the development of computer technology, mechanics of communication, control technology, large power semiconductor device, the how electric aircraft technology of digitizing, intellectuality, high reliability becomes one of technological trend.Large-scale unmanned plane belongs to typical, special how electric aircraft, it is characterized in that extensively adopting electrical actuation technology, power consumption big, intelligent high, needs high-power, high-performance and highly reliable electric system.Its distribution system is by electric power system processor (Power System Processor, PSP), electrical load administrative center (ELMC), power-supply controller of electric (Power Control Unit, PCU), generator control unit (Generator Control Unit, GCU), (Remote Terminal RT) forms remote terminal.And electrical load administrative center is as the important component part of distribution system, and its reliability is seriously restricting the reliability of whole large-scale unmanned aerial vehicle onboard electrical system, and redundance design, intelligent management etc. can effectively improve system and equipment dependability.
(3) summary of the invention
1, purpose: the purpose of this invention is to provide a kind of unmanned aerial vehicle onboard three-redundancy electrical load administrative center, it is by to the electrical load administrative center hardware configuration that is applicable to the unmanned plane electrical system and the design innovation of software algorithm, make designed three-redundancy electrical load administrative center finish robotization distribution control and intelligent management function, have advantages such as reliability height, fast, the intelligent degree height of response speed, volume are little, light weight.
2, technical scheme: a kind of unmanned aerial vehicle onboard three-redundancy electrical load of the present invention administrative center, it is a core with DSP TMS320F2812 and FPGA EP2C35F484, realizes the control of robotization distribution and the intelligent management function of large-scale unmanned plane.It comprises CPU central processing module, quantity of state Monitoring and Controlling module, synchronization module, cross aisle data chainning (being CCDL) module, analog acquisition conditioning module, drive control module, communication module and eight parts of power module.Position annexation between them is: this three-redundancy electrical load administrative center receives the steering order of master system in real time by communication module; Finish between this three-redundancy electrical load administrative center program synchronous through synchronization module; Voltage, current status according to the steering order of host computer, systematic electricity bus-bar that the analog acquisition conditioning module is returned, and the load condition of the solid-state power controller (being SSPC) that returns of quantity of state Monitoring and Controlling module, find the solution the load equation, thereby form the load distribution instruction under the unmanned plane different flight state; Finish switching between this three-redundancy electrical load administrative center through the exchanges data of CCDL module and monitoring voting, finish distribution load by the electrical load administrative center of main work remaining; Voltage, current information with the load state information that collects and electric power bus-bar is uploaded to unmanned aerial vehicle onboard power supply processor (PSP) by communication module simultaneously.
Described power module is finished the electric energy of whole electrical load administrative center is supplied with.Its major function is to be converted into the stabilized power source that satisfies each module needs of electrical load administrative center by multiple DC/DC modular converter.Power module mainly is made up of XZR05S/24S05, TPS70445, TPS75733, TPS76801 chip, and it converts airborne 28V direct supply to+5V ,+direct supply of 3.3V and+different power supply systems such as 1.2V.
Power module converts airborne+28V direct current Bus Voltage to+direct supply of 5V by the XZR05S/24S05 chip, then the direct supply by TPS70445 chip general+5V convert that FPGA needs to+3.3V and+direct supply of 1.2V, direct supply by TPS75733 chip general+5V converts that DSP needs to+direct supply of 3.3V, the direct supply by TPS76801 chip general+5V convert to the DSP needs+direct supply of 1.2V.
Described CPU central processing module is the core of unmanned plane electrical load administrative center, functions such as the control of the co-ordination of responsible redundance CPU, the collection of status information, system directive and execution.Its structure realizes by building digital signal processor (DSP) system and software programming; It is in real time by the steering order of communication module reception from host computer, receive load state information simultaneously from quantity of state Monitoring and Controlling module feedback, control analog acquisition conditioning module is gathered voltage, the current signal of electric power bus-bar, comprehensively find the solution the load equation, form the distribution instruction of respective load.
The CPU central processing module is by the real-time reception PC control instruction of interrupt service subroutine, in interrupt service subroutine, by check bit one eight of the back of the packet that receives increases, judge whether the packet that receives is effective steering order, if packet is effective steering order, then deposit control corresponding register among the DSP in, otherwise give up; Finish the synchronous of three remaining CPU through synchronization module, obtain the load state information that quantity of state Monitoring and Controlling module is fed back by corresponding registers among the inquiry DSP, the break-make that obtains load according to the load equation solution is instructed, and deposits it in distribution order register.
Described quantity of state Monitoring and Controlling module is the software module that unmanned plane electrical system platform monitoring is provided for the CPU central processing module.Its structure is programmed by dsp software and is realized, DSP finishes to the collection of load signal and uploading of load state information SSPC according to the communications protocol of SSPC to SSPC sending controling instruction packet; This module is finished the collection to all load state information of solid-state power controller SSPC on the one hand, according to the corresponding SSPC action of the distribution instruction control of CPU central processing module, and the feedback of status of detection SSPC, thereby realize the distributing function of electrical load administrative center.On the other hand, the various load state information that obtain are fed back to CPU central processing module and host computer, utilize these status informations to carry out built-in test (being BIT) and fault diagnosis.
Quantity of state Monitoring and Controlling module is obtained steering order from the control register of DSP, send the steering order packet that meets communications protocol to SSPC, make SSPC finish collection to load information, SSPC is uploaded to quantity of state Monitoring and Controlling module with the load state information of gathering, and deposits among the DSP in the corresponding status register; Obtain the distribution instruction that the CPU central processing module calculates in the distribution order register of quantity of state Monitoring and Controlling module from DSP, send the break-make instruction to SSPC, finish distribution control to respective load, by carrying out BIT and fault diagnosis according to the load information in the status register among the DSP, break down if finish the SSPC of distribution, then switch to backup SSPC and finish distribution.
Described synchronization module is this distinctive module of three-redundancy electrical load administrative center.Its structure is by writing synchronized algorithm and realize through digital I/O mouth and the FPGA device of DSP in DSP, each remaining DSP sends a high level signal at the digital I/O mouth that begins by DSP of each duty cycle to FPGA, (time of waiting for when the first time is synchronous is 0.5s to FPGA in official hour, the synchronous stand-by period afterwards is 100us) detect the high level signal that three remaining DSP send, then FPGA replys a high level signal to synchronous successful remaining DSP when receiving the high level signal of two or three remaining DSP, finish and shake hands for the first time, same mode is finished second handshake, thereby finishes the synchronous of three-redundancy electrical load administrative center; It is by the mode of " two shaking hands ", promptly this three-redundancy electrical load administrative center carries out the synchronizing signal transmission mutually by the CCDL module, sends synchronous clock request and syn ack signal, the executive software synchronized algorithm, and allow limited time deviation, so that output signal is synchronous.When main electrical load administrative center does not respond the synchronization request of Hot Spare remaining in setting-up time, the high remaining of backup electrical load administrative center's priority will be finished switching controls by FPGA.The innovation part of this module is to improve greatly by the response speed of the traditional bus load mode of the digital I/O mouth transfer ratio of DSP.
Synchronization module is to be made of synchronized algorithm among the DSP and the synchronized algorithm among the FPGA.In DSP, synchronized algorithm judge this subsynchronous whether be that first time of three remaining DSP is synchronous, if be that it is 0.5s that synchronization module is provided with the synchronous stand-by period, is 100us otherwise the synchronous stand-by period is set synchronously for the first time; Forbid interrupt service subroutines all among the DSP; DSP sends the high level synchronizing signal by digital I/O mouth DO to FPGA, enter the synchronous circulation program, detect simultaneously and wait for synchronously whether number of times surpasses limit value, if synchronization times surpasses limit value then jumps out synchronous circulation, the step-out number of times adds one, restart synchronously, otherwise wait for that synchronously number of times adds one; Synchronization module detects whether FPGA sends feedback signal from high level to the I/O of DSP mouth DI, if DSP receives the high level signal that FPGA sends, then expression is shaken hands successfully for the first time, otherwise represents this synchronization failure, restarts synchronously; DSP sends the synchronizing signal of high level once more to FPGA after the success of shaking hands for the first time, detect the high level signal of FPGA feedback simultaneously, if the second handshake success, then synchronous circulation is withdrawed from position, synchronous mark position, otherwise represent this synchronization failure, restart synchronously; After jumping out synchronous circulation, enable interrupt service subroutine; Detect the synchronous mark position, if three remaining DSP success is synchronously represented in set, the step-out counter O reset, synchronization program finishes, otherwise judges the step-out number of times, if the step-out number of times, is represented this remaining DSP fault greater than 5 times, restarts this remaining DSP.
In FPGA, synchronized algorithm is waited for the synchronous high level signal that three remaining DSP send in real time, if receive the synchronous high level signal of three remaining DSP, then FPGA is to three remaining DSP synchronized transmission feedback high level signals, and expression is success synchronously; If receive the synchronous high level signal of two remaining DSP, then FPGA sends the feedback high level signal to these two remaining DSP, represents the success synchronously of these two remainings; If only receive the synchronous high level signal of a remaining DSP, then represent three remaining DSP synchronization failures, FPGA is not to any remaining DSP feedback signal.
Described CCDL module is this distinctive module of three-redundancy electrical load administrative center, comprises remaining data monitoring, remaining data voting and three parts of remaining switching.The structure of CCDL module is by write the remaining data monitoring in FPGA, remaining data voting and remaining handoff algorithms are realized, three remaining DSP instruct PC control, the load state information of gathering and send to FPGA according to the distribution instruction that the load equation solution obtains, FPGA deposits these data respectively among the FPGA in the corresponding storage unit, then these data are compared, when the data of two or more remaining DSP are identical, then FPGA sends enable signal according to the priority (configuring in advance) of three redundancy electrical load administrative centers to the high remaining DSP of priority, switches thereby finish remaining.The remaining DSP of fault is restarted automatically in the remaining data voting, enters the remaining data voting of next round, if still fault then this remaining DSP are thoroughly isolated, if recover normally then this remaining DSP priority is fallen one-level and become the work of backup remaining; Three-redundancy electrical load administrative center at first exchanges main remaining and two data that back up between the remaining by remaining data monitoring program, switches through the remaining of remaining data voting algorithm decision three-redundancy electrical load administrative center then.The remaining data monitoring mainly is the intersection transmission of finishing data between the three-redundancy electrical load administrative center, to realize sharing of data between three remainings; The remaining data voting is calculated strategy according to the data of sharing between the three-redundancy electrical load administrative center through corresponding voting, judges whether three-redundancy electrical load administrative center duty is normal; The result that remaining is switched according to the remaining data voting switches to the distribution that the normal remaining of duty is finished load, restarts or shield the remaining of fault simultaneously according to the remaining processing policy.The innovation part of this module be the CCDL module at the scene in the programmable gate array (being FPGA) utilize VHDL language to write the voting algorithm of realizing based on hardware logic electric circuit to realize that this remaining monitoring voting formula of realizing based on hardware logic electric circuit has higher reliability, quicker response than traditional monitoring voting formula of realizing based on software algorithm.
Remaining data monitoring algorithm utilizes data bus and the address bus between DSP and the FPGA, and load state information and distribution instruction that three remaining DSP are sent deposit in the relevant register successively, to realize sharing of three remaining DSP data; Remaining data voting algorithm obtains the data that three remaining DSP share by the inquiry corresponding registers, and relatively whether identical (suppose that three remaining DSP passages are respectively A, B, C, priority is followed successively by A＞B＞C) to the data of three remaining DSP from high to low.If the data of three remaining DSP are identical, the remaining handoff algorithms is changed to A channel according to the priority slicing of three remaining DSP, is finally finished the load distribution by the DSP of A channel; If there are the data of two remaining DSP identical, if the DSP data that are A channel and B passage are identical, then the remaining handoff algorithms is changed to A channel according to the priority slicing of two remaining DSP, finally finish the load distribution by A channel DSP, the remaining handoff algorithms makes fault remaining C-channel DSP restart simultaneously, enter the remaining data voting of next round, if the remaining data voting C-channel DSP of next round fault then thoroughly shield subchannel still, he otherwise would recover normal; If three remaining DSP data are all inequality, the remaining handoff algorithms selects the A channel of high priority to finish distribution to load according to the priority of three remaining DSP.After a thorough shielding of remaining quilt is arranged in three remainings, the work of remaining handoff algorithms degradation, promptly when two remaining DSP data are identical, the passage of selection high priority is finished the distribution to load, when two remaining DSP data are inequality, still select the passage of high priority to finish distribution to load.
Described analog acquisition and conditioning module, it mainly is made up of typical amplifier voltage collection circuit, Hall current mutual inductor HX10-P, modulus conversion chip AD7865, sends the DSP device by the semaphore of gathering and nursing one's health to by the IO data line and handles; Position annexation therebetween is: the amplifier voltage collection circuit is gathered the voltage signal of electric power bus-bar, and the Hall current mutual inductor is gathered the current signal of electric power bus-bar, delivers to modulus conversion chip through modulate circuit and carries out analog to digital conversion.It gathers voltage, the current signal of corresponding electric power bus-bar according to the steering order of CPU central processing module, and, system-level and status information equipment are sent to the CPU central processing module carry out fault diagnosis and processing through modulate circuit and analog to digital conversion circuit.
Described drive control module, it is to be made of ULN2003 power drive chip; Position annexation therebetween is: the CPU central processing module is to the ULN2003 sending controling instruction, and power chip ULN2003 carries out power amplification with steering order, drives high-power contactor and finishes distribution.It is according to the steering order of CPU central processing module, and the corresponding high-power contactor of drive controlling is finished high-power distribution controls with electric loading such as bus-bars.
Described communication module, it is that RS-422 serial bus communication chip MAXIM3160 by MAXIM company finishes.This three-redundancy electrical load administrative center finishes tripartite surface function by this module: 1. and upper machine communication, receive the steering order that host computer sends, send the various status informations of electric power bus-bar and load simultaneously to host computer; 2. finish the communication with solid-state power controller (SSPC), receive the various load state information that SSPC sends, send the distribution instruction to SSPC; 3. the exchanges data of finishing between the three-redundancy electrical load administrative center is shared.
Wherein, the processor of described CPU central processing module is the dominant frequency digital signal processor of 150M Hz at least.
Wherein, the FPGA in the described synchronization module is field programmable gate array dominant frequency 100M Hz at least.
Wherein, remaining monitoring, voting and the switchover policy of described CCDL module are: the remaining unit of all electrical load administrative centers powers up work, and when host CPU was working properly, backup CPU did not carry out any control, the transmission of messages of only responsible monitoring data bus, and accept corresponding data; When main remaining breaks down, switch to the work of backup remaining; When fault CPU determines to recover normally by the built in self testing measuring program after, become backup CPU and enter relatively voting and monitoring mode.
The principle of work or the flow process of a kind of unmanned aerial vehicle onboard three-redundancy electrical load of the present invention administrative center are: this three-redundancy electrical load administrative center receives the steering order of unmanned aerial vehicle onboard master system in real time by communication module; Finish between this three-redundancy electrical load administrative center program synchronous through synchronization module; Voltage, current status according to the steering order of host computer, systematic electricity bus-bar that the analog acquisition conditioning module is returned, and the load condition of the SSPC that returns of quantity of state Monitoring and Controlling module, find the solution the load equation, thereby form the load distribution instruction under the different flight state; Finish switching between this three-redundancy electrical load administrative center through the exchanges data of CCDL module and monitoring voting, finish distribution load by the electrical load administrative center of main work remaining; Voltage, current information with the load state information that collects and electric power bus-bar is uploaded to power supply processor (PSP) by communication module simultaneously.
3, advantage and effect: the present invention is that a kind of innovation part of the unmanned aerial vehicle onboard three-redundancy electrical load administrative center based on " DSP+FPGA " structure is:
(1) first control of three remaining computer intelligences and management structure design are applied in the unmanned aerial vehicle onboard power distribution system equipment at home.In this system, all remaining unit of electrical load administrative center power up work, and when host CPU was working properly, backup CPU did not carry out any control, the transmission of messages of only responsible monitoring data bus, and accept corresponding data; When main remaining breaks down, switch to the work of backup remaining; When fault CPU determines to recover normally by the built in self testing measuring program after, become backup CPU and enter relatively voting and monitoring mode.This structure automaticity height, processor be the work high conformity before and after switching, and mission reliability improves greatly;
(2) remaining monitoring, voting and the switching controls of three-redundancy electrical load administrative center realize in FPGA (field programmable gate array), have improved the processing speed of electrical load administrative center remaining fault greatly;
(3) set up quantity of state Monitoring and Controlling module and the analog acquisition conditioning module that is applicable to the unmanned plane electrical system, can effectively improve the detectability and the fault diagnosis accuracy of system;
(4) this electrical load administrative center is particularly suitable for the collecting and distributing type distribution system of large-scale unmanned plane, is the various power supplys that satisfy its needs that improve with electric loading in the machine.The intelligent electric Electrical Load Management Center replaces whole operations of pilot, automatically control and load management according to setting means, realize intelligent power distribution, remaining control and the fault handling of aircraft, reliability, maintenanceability and the serviceable life of improving large-scale unmanned plane distribution system greatly; When unmanned plane breaks down, carry out fault-tolerant processing according to the control strategy of setting, improve the large-scale unmanned plane probability that safety is maked a return voyage under limited power.
The present invention is by to the design innovation of electrical load administrative center hardware configuration and software configuration, makes the three remaining intelligent electric Electrical Load Management Center that are applied to the unmanned plane electrical system have that high reliability, fast-response speed, volume are little, the advantage of light weight.This electrical load administrative center cooperates with high performance electric power system processor, can realize the intelligent management to airborne consumer, can be used for the airborne distribution system of high reliability.
(4) description of drawings
Fig. 1 is an one-piece construction synoptic diagram of the present invention;
Fig. 2 is the structural representation of power module of the present invention;
Fig. 3 is a master routine software flow synoptic diagram of the present invention;
Fig. 4 is the synoptic diagram of main program flow chart interrupt service subroutine of the present invention;
Fig. 5 is the algorithm synoptic diagram of synchronization program of the present invention in DSP;
Fig. 6 is the algorithm synoptic diagram of synchronization program of the present invention in FPGA;
Fig. 7 is a CCDL communication synoptic diagram of the present invention.
Symbol description is as follows among the figure:
A, B, C represent that three remainings among the three remaining DSP are respectively A remaining, B remaining and C remaining among the figure;
Among the figure in the M presentation graphs line at two M places link together;
Among the figure in the T presentation graphs line at two T places link together;
PSP represents the processor of powering among the figure;
DSP represents digital signal processor among the figure;
CCDL represents the cross aisle data chainning among the figure;
SSPC represents solid-state power controller among the figure.
(5) embodiment:
See Fig. 1, a kind of unmanned aerial vehicle onboard three-redundancy electrical load of the present invention administrative center, with DSP TMS320F2812 and FPGAEP2C35F484 is core, and it comprises CPU central processing module, quantity of state Monitoring and Controlling module, synchronization module, CCDL module, analog acquisition conditioning module, drive control module, communication module and eight parts of power module.See Fig. 3 and Fig. 4, this three-redundancy electrical load administrative center utilizes the interrupt service subroutine of DSP TMS320F2812 to receive the steering order of host computer and real-time renewal host computer order register in real time; Finish between this three-redundancy electrical load administrative center program synchronous through the synchronized algorithm among the DSP; Voltage, the current status of the PC control instruction that receives according to interrupt service subroutine, the systematic electricity bus-bar that the analog acquisition conditioning module is returned, and the load condition of the SSPC that returns of quantity of state Monitoring and Controlling module, find the solution the load equation, thereby form the load distribution instruction under the different flight state; Finish switching between this three-redundancy electrical load administrative center through the exchanges data among the FPGA EP2C35F484, monitoring voting and remaining handoff algorithms, and finish to the intelligent power distribution of load and with the load state information that collects and voltage, the current information of electric power bus-bar by Systems Redundancy Management in the main redundancy electrical load administrative center and to be uploaded to host computer.
See Fig. 2, described power module is finished the electric energy of whole electrical load administrative center is supplied with.Its major function is to be converted into the stabilized power source that satisfies each module needs of electrical load administrative center by multiple DC/DC modular converter.Power module mainly is made up of XZR05S/24S05, TPS70445, TPS75733, TPS76801 chip, and it converts airborne 28V direct supply to+5V ,+direct supply of 3.3V and+different power supply systems such as 1.2V.
Power module converts airborne+28V direct current Bus Voltage to+direct supply of 5V by the XZR05S/24S05 chip, then the direct supply by TPS70445 chip general+5V convert that FPGA needs to+3.3V and+direct supply of 1.2V, direct supply by TPS75733 chip general+5V converts that DSP needs to+direct supply of 3.3V, the direct supply by TPS76801 chip general+5V convert to the DSP needs+direct supply of 1.2V.
Described CPU central processing module is the core of electrical load administrative center, functions such as the control of the co-ordination of responsible redundance CPU, the collection of status information, system directive and execution.Its structure realizes by building digital signal processor (DSP) system and software programming; It is in real time by the steering order of communication module reception from host computer, receive load state information simultaneously from quantity of state Monitoring and Controlling module feedback, control analog acquisition conditioning module is gathered voltage, the current signal of electric power bus-bar, comprehensively find the solution the load equation, form the distribution instruction of respective load.
The CPU central processing module is by the real-time reception PC control instruction of interrupt service subroutine, in interrupt service subroutine, by check bit one eight of the back of the packet that receives increases, judge whether the packet that receives is effective steering order, if packet is effective steering order, then deposit control corresponding register among the DSP in, otherwise give up; Finish the synchronous of three remaining CPU through synchronization module, obtain the load state information that quantity of state Monitoring and Controlling module is fed back by corresponding registers among the inquiry DSP, the break-make that obtains load according to the load equation solution is instructed, and deposits it in distribution order register.
Described quantity of state Monitoring and Controlling module is the software module that the system platform monitoring is provided for the CPU central processing module.Its structure is programmed by dsp software and is realized, DSP finishes to the collection of load signal and uploading of load state information SSPC according to the communications protocol of SSPC to SSPC sending controling instruction packet; This module is finished the collection to all load state information of solid-state power controller SSPC on the one hand, according to the corresponding SSPC action of the distribution instruction control of CPU central processing module, and the feedback of status of detection SSPC, thereby realize the distributing function of electrical load administrative center.On the other hand, the various load state information that obtain are fed back to CPU central processing module and host computer, utilize these status informations to carry out built-in test (being BIT) and fault diagnosis.
Quantity of state Monitoring and Controlling module is obtained steering order from the control register of DSP, send the steering order packet that meets communications protocol to SSPC, make SSPC finish collection to load information, SSPC is uploaded to quantity of state Monitoring and Controlling module with the load state information of gathering, and deposits among the DSP in the corresponding status register; Obtain the distribution instruction that the CPU central processing module calculates in the distribution order register of quantity of state Monitoring and Controlling module from DSP, send the break-make instruction to SSPC, finish distribution control to respective load, by carrying out BIT and fault diagnosis according to the load information in the status register among the DSP, break down if finish the SSPC of distribution, then switch to backup SSPC and finish distribution.
See Fig. 5 and Fig. 6, described synchronization module is this distinctive module of three-redundancy electrical load administrative center.Its structure is by writing synchronized algorithm and realize through digital I/O mouth and the FPGA device of DSP in DSP, each remaining DSP sends a high level signal at the digital I/O mouth that begins by DSP of each duty cycle to FPGA, (time of waiting for when the first time is synchronous is 0.5s to FPGA in official hour, the synchronous stand-by period afterwards is 100us) detect the high level signal that three remaining DSP send, then FPGA replys a high level signal to synchronous successful remaining DSP when receiving the high level signal of two or three remaining DSP, finish and shake hands for the first time, same mode is finished second handshake, thereby finishes the synchronous of three-redundancy electrical load administrative center; It is by the mode of " two shaking hands ", promptly this three-redundancy electrical load administrative center carries out the synchronizing signal transmission mutually by the CCDL module, sends synchronous clock request and syn ack signal, the executive software synchronized algorithm, and allow limited time deviation, so that output signal is synchronous.When main electrical load administrative center does not respond the synchronization request of Hot Spare remaining in setting-up time, the high remaining of backup electrical load administrative center's priority will be finished switching controls by FPGA.The innovation part of this module is to improve greatly by the response speed of the traditional bus load mode of the digital I/O mouth transfer ratio of DSP.
Synchronization module is to be made of synchronized algorithm among the DSP and the synchronized algorithm among the FPGA.In DSP, synchronized algorithm judge this subsynchronous whether be that first time of three remaining DSP is synchronous, if be that it is 0.5s that synchronization module is provided with the synchronous stand-by period, is 100us otherwise the synchronous stand-by period is set synchronously for the first time; Forbid interrupt service subroutines all among the DSP; DSP sends the high level synchronizing signal by digital I/O mouth DO to FPGA, enter the synchronous circulation program, detect simultaneously and wait for synchronously whether number of times surpasses limit value, if synchronization times surpasses limit value then jumps out synchronous circulation, the step-out number of times adds one, restart synchronously, otherwise wait for that synchronously number of times adds one; Synchronization module detects whether FPGA sends feedback signal from high level to the I/O of DSP mouth DI, if DSP receives the high level signal that FPGA sends, then expression is shaken hands successfully for the first time, otherwise represents this synchronization failure, restarts synchronously; DSP sends the synchronizing signal of high level once more to FPGA after the success of shaking hands for the first time, detect the high level signal of FPGA feedback simultaneously, if the second handshake success, then synchronous circulation is withdrawed from position, synchronous mark position, otherwise represent this synchronization failure, restart synchronously; After jumping out synchronous circulation, enable interrupt service subroutine; Detect the synchronous mark position, if three remaining DSP success is synchronously represented in set, the step-out counter O reset, synchronization program finishes, otherwise judges the step-out number of times, if the step-out number of times, is represented this remaining DSP fault greater than 5 times, restarts this remaining DSP.
In FPGA, synchronized algorithm is waited for the synchronous high level signal that three remaining DSP send in real time, if receive the synchronous high level signal of three remaining DSP, then FPGA is to three remaining DSP synchronized transmission feedback high level signals, and expression is success synchronously; If receive the synchronous high level signal of two remaining DSP, then FPGA sends the feedback high level signal to these two remaining DSP, represents the success synchronously of these two remainings; If only receive the synchronous high level signal of a remaining DSP, then represent three remaining DSP synchronization failures, FPGA is not to any remaining DSP feedback signal.
See Fig. 7, described CCDL module is this distinctive module of three-redundancy electrical load administrative center, comprises remaining data monitoring, remaining data voting and three parts of remaining switching.The structure of CCDL module is by write the remaining data monitoring in FPGA, remaining data voting and remaining handoff algorithms are realized, three remaining DSP instruct PC control, the load state information of gathering and send to FPGA according to the distribution instruction that the load equation solution obtains, FPGA deposits these data respectively among the FPGA in the corresponding storage unit, then these data are compared, when the data of two or more remaining DSP are identical, then FPGA sends enable signal according to the priority (configuring in advance) of three redundancy electrical load administrative centers to the high remaining DSP of priority, switches thereby finish remaining.The remaining DSP of fault is restarted automatically in the remaining data voting, enters the remaining data voting of next round, if still fault then this remaining DSP are thoroughly isolated, if recover normally then this remaining DSP priority is fallen one-level and become the work of backup remaining; Three-redundancy electrical load administrative center at first exchanges main remaining and two data that back up between the remaining by remaining data monitoring program, switches through the remaining of remaining data voting algorithm decision three-redundancy electrical load administrative center then.The remaining data monitoring mainly is the intersection transmission of finishing data between the three-redundancy electrical load administrative center, to realize sharing of data between three remainings; The remaining data voting is calculated strategy according to the data of sharing between the three-redundancy electrical load administrative center through corresponding voting, judges whether three-redundancy electrical load administrative center duty is normal; The result that remaining is switched according to the remaining data voting switches to the distribution that the normal remaining of duty is finished load, restarts or shield the remaining of fault simultaneously according to the remaining processing policy.The innovation part of this module be the CCDL module at the scene in the programmable gate array (being FPGA) utilize VHDL language to write the voting algorithm of realizing based on hardware logic electric circuit to realize that this remaining monitoring voting formula of realizing based on hardware logic electric circuit has higher reliability, quicker response than traditional monitoring voting formula of realizing based on software algorithm.
Remaining data monitoring algorithm utilizes data bus and the address bus between DSP and the FPGA, and load state information and distribution instruction that three remaining DSP are sent deposit in the relevant register successively, to realize sharing of three remaining DSP data; Remaining data voting algorithm obtains the data that three remaining DSP share by the inquiry corresponding registers, and relatively whether identical (suppose that three remaining DSP passages are respectively A, B, C, priority is followed successively by A＞B＞C) to the data of three remaining DSP from high to low.If the data of three remaining DSP are identical, the remaining handoff algorithms is changed to A channel according to the priority slicing of three remaining DSP, is finally finished the load distribution by the DSP of A channel; If there are the data of two remaining DSP identical, if the DSP data that are A channel and B passage are identical, then the remaining handoff algorithms is changed to A channel according to the priority slicing of two remaining DSP, finally finish the load distribution by A channel DSP, the remaining handoff algorithms makes fault remaining C-channel DSP restart simultaneously, enter the remaining data voting of next round, if the remaining data voting C-channel DSP of next round fault then thoroughly shield subchannel still, he otherwise would recover normal; If three remaining DSP data are all inequality, the remaining handoff algorithms selects the A channel of high priority to finish distribution to load according to the priority of three remaining DSP.After a thorough shielding of remaining quilt is arranged in three remainings, the work of remaining handoff algorithms degradation, promptly when two remaining DSP data are identical, the passage of selection high priority is finished the distribution to load, when two remaining DSP data are inequality, still select the passage of high priority to finish distribution to load.
Described analog acquisition and conditioning module, it mainly is by amplifier voltage collection circuit, Hall current mutual inductor HX10-P, modulus conversion chip AD7865; Sending the DSP device by the semaphore of gathering and nursing one's health to by the IO data line handles; Position annexation therebetween is: the amplifier voltage collection circuit is gathered the voltage signal of electric power bus-bar, and the Hall current mutual inductor is gathered the current signal of electric power bus-bar, delivers to modulus conversion chip AD7865 through modulate circuit and carries out analog to digital conversion.It utilizes amplifier voltage collection circuit, Hall current mutual inductor to change voltage, the electric current of corresponding electric power bus-bar, modulate circuit level signal that mutual inductor is obtained converts the signal that is fit to modulus conversion chip AD7865 conversion to then, carry out analog to digital conversion by AD7865, and 14 position digital signals that will be converted to are sent among the DSP.
Described drive control module, it is to be made of ULN2003 power drive chip; Position annexation therebetween is: the CPU central processing module is to the ULN2003 sending controling instruction, and power chip ULN2003 carries out power amplification with steering order, drives high-power contactor and finishes distribution; It is according to the steering order of CPU central processing module, and the corresponding high-power contactor of drive controlling is finished high-power distribution controls with electric loading such as bus-bars.
Described communication module, it forms the communication module circuit by traditional RS-422 and MIL-1553B chip.This three-redundancy electrical load administrative center finishes tripartite surface function by this module: 1. and upper machine communication, receive the steering order that host computer sends, send the various status informations of electric power bus-bar and load simultaneously to host computer; 2. finish the communication with solid-state power controller (SSPC), receive the various load state information that SSPC sends, send the distribution instruction to SSPC; 3. the exchanges data of finishing between the three-redundancy electrical load administrative center is shared.
Wherein, the processor of described CPU central processing module is the digital signal processor of dominant frequency 150M Hz.
Wherein, the FPGA in the described synchronization module is field programmable gate array dominant frequency 100M Hz.
Wherein, remaining monitoring, voting and the switchover policy of described CCDL module are: the remaining unit of all electrical load administrative centers powers up work, and when host CPU was working properly, backup CPU did not carry out any control, the transmission of messages of only responsible monitoring data bus, and accept corresponding data; When main remaining breaks down, switch to the work of backup remaining; When fault CPU determines to recover normally by the built in self testing measuring program after, become backup CPU and enter relatively voting and monitoring mode.
Claims (4)
1. unmanned aerial vehicle onboard three-redundancy electrical load administrative center, it is characterized in that: it is a core with DSP TMS320F2812 and FPGA EP2C35F484, realizes the control of robotization distribution and the intelligent management function of large-scale unmanned plane; It comprises that CPU central processing module, quantity of state Monitoring and Controlling module, synchronization module, cross aisle data chainning are CCDL module, analog acquisition conditioning module, drive control module, communication module and power module eight parts; Position annexation between them is: this three-redundancy electrical load administrative center receives the steering order of master system in real time by communication module; Finish between this three-redundancy electrical load administrative center program synchronous through synchronization module; Voltage, current status according to the steering order of host computer, systematic electricity bus-bar that the analog acquisition conditioning module is returned, and the solid-state power controller that quantity of state Monitoring and Controlling module is returned is the load condition of SSPC, find the solution the load equation, thereby form the load distribution instruction under the different flight state; Finish switching between this three-redundancy electrical load administrative center through the exchanges data of CCDL module and monitoring voting, finish distribution load by the electrical load administrative center of main work remaining; Simultaneously the load state information that collects and voltage, the current information of electric power bus-bar are uploaded to the power supply processor by communication module;
Described power module is to be converted into the stabilized power source that satisfies each module needs of electrical load administrative center by multiple DC/DC modular converter; Power module is made up of XZR05S/24S05, TPS70445, TPS75733, TPS76801 chip, power module converts airborne+28V direct current Bus Voltage to+direct supply of 5V by the XZR05S/24S05 chip, then the direct supply by TPS70445 chip general+5V convert that FPGA needs to+3.3V and+direct supply of 1.2V, direct supply by TPS75733 chip general+5V converts that DSP needs to+direct supply of 3.3V, the direct supply by TPS76801 chip general+5V convert to the DSP needs+direct supply of 1.2V;
Described CPU central processing module is the co-ordination of being responsible for redundance CPU, the collection of status information, the control and the execution function of system directive; Its structure is that dsp system and software programming realize by building digital signal processor; It is in real time by the steering order of communication module reception from host computer, receive load state information simultaneously from quantity of state Monitoring and Controlling module feedback, control analog acquisition conditioning module is gathered voltage, the current signal of electric power bus-bar, comprehensively find the solution the load equation, form the distribution instruction of respective load; The CPU central processing module is by the real-time reception PC control instruction of interrupt service subroutine, in interrupt service subroutine, by check bit one eight of the back of the packet that receives increases, judge whether the packet that receives is effective steering order, if packet is effective steering order, then deposit control corresponding register among the DSP in, otherwise give up; Finish the synchronous of three remaining CPU through synchronization module, obtain the load state information that quantity of state Monitoring and Controlling module is fed back by corresponding registers among the inquiry DSP, the break-make that obtains load according to the load equation solution is instructed, and deposits it in distribution order register;
Described quantity of state Monitoring and Controlling module is the software module that unmanned plane electrical system platform monitoring is provided for the CPU central processing module, its structure is programmed by dsp software and is realized, DSP finishes to the collection of load signal and uploading of load state information SSPC according to the communications protocol of SSPC to SSPC sending controling instruction packet; This module is finished the collection to all load state information of solid-state power controller SSPC on the one hand, according to the corresponding SSPC action of the distribution instruction control of CPU central processing module, and the feedback of status of detection SSPC, thereby realize the distributing function of electrical load administrative center; On the other hand, the various load state information that obtain are fed back to CPU central processing module and host computer, utilizing these status informations to carry out built-in test is BIT and fault diagnosis; Break down if finish the SSPC of distribution, then switch to backup SSPC and finish distribution;
Described synchronization module is to be made of synchronized algorithm among the DSP and the synchronized algorithm among the FPGA, and its structure is by writing synchronized algorithm and realize through digital I/O mouth and the FPGA device of DSP in DSP; In DSP, synchronized algorithm judge this subsynchronous whether be that first time of three remaining DSP is synchronous, if be that it is 0.5s that synchronization module is provided with the synchronous stand-by period, is 100us otherwise the synchronous stand-by period is set synchronously for the first time; Forbid interrupt service subroutines all among the DSP; DSP sends the high level synchronizing signal by digital I/O mouth DO to FPGA, enter the synchronous circulation program, detect simultaneously and wait for synchronously whether number of times surpasses limit value, if synchronization times surpasses limit value then jumps out synchronous circulation, the step-out number of times adds one, restart synchronously, otherwise wait for that synchronously number of times adds one; Synchronization module detects whether FPGA sends feedback signal from high level to the I/O of DSP mouth DI, if DSP receives the high level signal that FPGA sends, then expression is shaken hands successfully for the first time, otherwise represents this synchronization failure, restarts synchronously; DSP sends the synchronizing signal of high level once more to FPGA after the success of shaking hands for the first time, detect the high level signal of FPGA feedback simultaneously, if the second handshake success, then synchronous circulation is withdrawed from position, synchronous mark position, otherwise represent this synchronization failure, restart synchronously; After jumping out synchronous circulation, enable interrupt service subroutine; Detect the synchronous mark position, if three remaining DSP success is synchronously represented in set, the step-out counter O reset, synchronization program finishes, otherwise judges the step-out number of times, if the step-out number of times, is represented this remaining DSP fault greater than 5 times, restarts this remaining DSP; In FPGA, synchronized algorithm is waited for the synchronous high level signal that three remaining DSP send in real time, if receive the synchronous high level signal of three remaining DSP, then FPGA is to three remaining DSP synchronized transmission feedback high level signals, and expression is success synchronously; If receive the synchronous high level signal of two remaining DSP, then FPGA sends the feedback high level signal to these two remaining DSP, represents the success synchronously of these two remainings; If only receive the synchronous high level signal of a remaining DSP, then represent three remaining DSP synchronization failures, FPGA is not to any remaining DSP feedback signal;
Described CCDL module comprises remaining data monitoring, remaining data voting and three parts of remaining switching; The structure of CCDL module realizes by write remaining data monitoring algorithm, remaining data voting algorithm and remaining handoff algorithms in FPGA; Remaining data monitoring algorithm utilizes data bus and the address bus between DSP and the FPGA, and load state information and distribution instruction that three remaining DSP are sent deposit in the relevant register successively, to realize sharing of three remaining DSP data; Remaining data voting algorithm obtains the data that three remaining DSP share by the inquiry corresponding registers, and relatively whether the data of three remaining DSP are identical; If the data of three remaining DSP are identical, the remaining handoff algorithms is changed to A channel according to the priority slicing of three remaining DSP, is finally finished the load distribution by the DSP of A channel; If there are the data of two remaining DSP identical, if the DSP data that are A channel and B passage are identical, then the remaining handoff algorithms is changed to A channel according to the priority slicing of two remaining DSP, finally finish the load distribution by A channel DSP, the remaining handoff algorithms makes fault remaining C-channel DSP restart simultaneously, enter the remaining data voting of next round, if the remaining data voting C-channel DSP of next round fault then thoroughly shield subchannel still, he otherwise would recover normal; If three remaining DSP data are all inequality, the remaining handoff algorithms selects the A channel of high priority to finish distribution to load according to the priority of three remaining DSP; After a thorough shielding of remaining quilt is arranged in three remainings, the work of remaining handoff algorithms degradation, promptly when two remaining DSP data are identical, the passage of selection high priority is finished the distribution to load, when two remaining DSP data are inequality, still select the passage of high priority to finish distribution to load;
Described analog acquisition and conditioning module, it is made up of typical amplifier voltage collection circuit, Hall current mutual inductor HX10-P, modulus conversion chip AD7865, sends the DSP device by the semaphore of gathering and nursing one's health to by the IO data line and handles; Position annexation therebetween is: the amplifier voltage collection circuit is gathered the voltage signal of electric power bus-bar, and the Hall current mutual inductor is gathered the current signal of electric power bus-bar, delivers to modulus conversion chip through modulate circuit and carries out analog to digital conversion; It gathers voltage, the current signal of corresponding electric power bus-bar according to the steering order of CPU central processing module, and, system-level and status information equipment are sent to the CPU central processing module carry out fault diagnosis and processing through modulate circuit and analog to digital conversion circuit;
Described drive control module, it is to be made of ULN2003 power drive chip; Position annexation therebetween is: the CPU central processing module is to the ULN2003 sending controling instruction, and power chip ULN2003 carries out power amplification with steering order, drives high-power contactor and finishes distribution; It is according to the steering order of CPU central processing module, and the corresponding high-power contactor of drive controlling is finished high-power distribution controls with electric loading such as bus-bars;
Described communication module, it is that RS-422 serial bus communication chip MAXIM3160 by MAXIM company finishes.
2. a kind of unmanned aerial vehicle onboard three-redundancy electrical load according to claim 1 administrative center, it is characterized in that: the processor of this CPU central processing module is the dominant frequency digital signal processor of 150M Hz at least.
3. a kind of unmanned aerial vehicle onboard three-redundancy electrical load according to claim 1 administrative center, it is characterized in that: the FPGA in this synchronization module is field programmable gate array dominant frequency 100M Hz at least.
4. a kind of unmanned aerial vehicle onboard three-redundancy electrical load according to claim 1 administrative center, it is characterized in that: remaining monitoring, voting and the switchover policy of this CCDL module are: the remaining unit of all electrical load administrative centers powers up work, when host CPU is working properly, backup CPU does not carry out any control, the transmission of messages of only responsible monitoring data bus, and accept corresponding data; When main remaining breaks down, switch to the work of backup remaining; When fault CPU determines to recover normally by the built in self testing measuring program after, become backup CPU and enter relatively voting and monitoring mode.
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