CN101909348A - Transmission triggering frame-based wireless sensor network node special processor - Google Patents
Transmission triggering frame-based wireless sensor network node special processor Download PDFInfo
- Publication number
- CN101909348A CN101909348A CN2010101480667A CN201010148066A CN101909348A CN 101909348 A CN101909348 A CN 101909348A CN 2010101480667 A CN2010101480667 A CN 2010101480667A CN 201010148066 A CN201010148066 A CN 201010148066A CN 101909348 A CN101909348 A CN 101909348A
- Authority
- CN
- China
- Prior art keywords
- module
- wireless sensor
- instruction
- sensor network
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Mobile Radio Communication Systems (AREA)
Abstract
The invention discloses a transmission triggering frame-based wireless sensor network node special processor, which comprises an arithmetical logic instruction module (1), a bit operation instruction module (2), a register module (3), a data access instruction module (4), a control register module (5), a sleep and clock management instruction module (6), a radio frequency interface module (7) and an MAC protocol instruction module (8). All modules are connected through a special bus, and each instruction specifies a source address and a destination address for data transmission; and according to the specific instruction, the data is transmitted among different modules and is calculated in the transmission process among the modules. The processer avoids a plurality of defects caused by the traditional universal processor at sensor nodes; and compared with the conventional processor, the processor of the invention has the advantages of low power consumption, high calculation speed, simple structure, strong expandability and the like, and is more suitable to be applied to a wireless sensor network.
Description
[technical field]: the present invention relates to field of wireless transmission, particularly a kind ofly be used for application specific processor on the wireless sensor network node.
[background technology]: (Wireless Sensor Network WSN) is the network that is made of by the wireless communication technology self-organizing a large amount of sensor nodes to wireless sensor network.It can realize that the collection of data quantizes, handles and merge and the transmission application.It is formed by being deployed in sensor nodes a large amount of in the monitored area, by the network system of a multi-hop ad hoc of communication formation, thus the monitoring information of perception, collection and the processing network's coverage area of cooperation, and send to the observer.Wireless sensor network is concentrated-distributed information gathering, message transmission and the information processing technology network information system in one, has characteristics such as low cost, microminiaturization, low-power consumption.
The power consumption of sensor node, volume and cost are the subject matter that the wireless sensor network node design is considered, present wireless sensor network node generally adopts general processor, because general processor was not done optimization at the wireless sensor network applied environment specially, wireless sensor network protocols and algorithm are mainly realized by software, efficient is lower, the needs that are difficult to satisfy wireless sensor network at aspects such as power consumption and volumes, the large-scale application that has influenced wireless sensor network is promoted.
Therefore, the combined sensor node is used the actual special designs of carrying out, and design has low-power consumption, low cost, high integrated, high-performance, intellectuality and microminiaturized wireless sensor network application specific processor, meets the trend of technical development.This also lays the foundation for the large-scale application of wireless sensor network, has important practical significance and practical value.
[summary of the invention]:
The objective of the invention is to improve low, the problems of in wireless sensor network, using at present such as power consumption is big, arithmetic speed is slow, software programming complexity of general processor efficient, thereby propose a kind of application specific processor that is applicable to wireless biography device network node.
To achieve these goals, the invention provides a kind of application specific processor that is used for wireless sensor network node, comprise (1) arithmetical logic instruction module, (2) bit manipulation instruction module, (3) register module, (4) data access command module, (5) control register module, (6) dormancy and Clock management instruction module, (7) radio frequency interface module, (8) MAC protocol instructions module
Wherein, all modules all connect by bus, when processor is worked, according to the instruction of from program storage, obtaining, determine source address and destination address, bus is provided with above-mentioned signal according to instruction, finish the transmission of data, and calculating process occurs in the data transmission procedure.
In the technique scheme, described (1) arithmetical logic instruction module, (2) bit manipulation instruction module, (3) register module, (4) data access command module, (5) control register module have constituted the basic functions of processor, finish and the similar calculation function of general processor.
In the technique scheme, described (6) thus dormancy and Clock management instruction module are realized the dormancy of processor and are waken the purpose that plays the reduction power consumption up.
In the technique scheme, described (7) radio frequency interface module is under the control of described (8) MAC protocol instructions module, communicate with radio frequency chip, finish the function such as transmission, reception, modulation pattern, transmitting power adjustment, tranmitting frequency adjustment of data.
In the technique scheme, described (8) MAC protocol instructions module is divided into set the tone system demodulation modes, transmitting power, tranmitting frequency etc. in commands for controlling, and packet encapsulated and resolves, realizes when launching collision detection---avoidance mechanism, when the MAC module was worked, other modules can dormancy.
Advantage of the present invention and good effect:
1, the present invention is used for application specific processor on the wireless sensor network node procotol that the wireless sensor network frequency of utilization is very high and the algorithm of signal processing is realized with hardware logic, the high efficiency of performance hardware logic, the power consumption of saving wireless sensor network node.
2, the application specific processor that is used on the wireless sensor network node of the present invention is dispatched each module according to software, by writing different software, can dispatch hardware module with diverse ways, thereby realize transfer of data, functions such as forwarding have been brought into play the flexibility of software.
[description of drawings]:
Fig. 1 is a kind of wireless sensor network node special processor structure chart based on transmission triggering architecture of the present invention.
[embodiment]:
As shown in Figure 1, a kind of wireless sensor network application specific processor based on transmission triggering architecture of the present invention comprises (1) arithmetical logic instruction module, (2) bit manipulation instruction module, (3) register module, (4) data access command module, (5) control register module, (6) dormancy and Clock management instruction module, (7) radio frequency interface module, (8) MAC protocol instructions module.
Wherein, all modules all connect by bus, bus comprises source_sel, dest_sel, source_addr, dest_addr, data_in, data_out, signals such as interrupt, expression source selection respectively, target selection, source address, destination address, source data input, target data output, interrupt requests etc.And (7) radio frequency interface module links to each other with radio-frequency module by the SPI interface, and (4) data access command module links to each other with memory by external bus.
Every instruction in fact all is a transfer operation, and every command length is 2 bytes, and every instruction all can be divided into three fields: where source (SOURCE) specific data is from shifting out; Where target (DESTINATION) specific data is sent to; Form bit then indicates the source and is one and counts immediately that still a register indicates, and its form sees Table 1.
Table 1 command format
| FORMAT | SOURCE | DESTINATION |
(1) the arithmetical logic instruction module provide addition, full add method, subtraction, band borrow subtraction, position or, functions such as, the arithmetic shift left non-of position XOR, position, logical shift left, arithmetic shift right, logic shift right, position exchange, byte exchange with, position, wherein difference in functionality is distinguished according to source address, destination address and source and purpose selection signal.
(2) the bit manipulation instruction module is passed through the certain bits in source address or the destination address addressing operation number, and then specific bit is carried out operations such as set, zero clearing and negate.
(3) register module provides 16 16 bit registers, and each register can write or read the monocycle, and wherein, accumulator pointer register register pointed is designated as " effectively accumulator ", becomes the destination register of arithmetical logic instruction.Therefore, by changing the value of accumulator pointer register, any one in the middle of these 16 registers all can be designated as the Action Target of arithmetical logic instruction.
(4) the data access command module comprises that instruction pointer, stack pointer, two data pointers that can comprise plot and side-play amount from data pointer and of increase and decrease constitute, difference according to the address, visit this module and will carry out a directly or indirectly loading, perhaps storage operation, and may be behind dereference the increasing or decreasing data pointer.
(5) the control register module comprises accumulator pointer register, interrupt request register, clock select register, flag bit register etc., by these registers, can to program circuit, Interrupt Process, system clock input, and function such as integrating instrument selection control.
(6) dormancy and Clock management instruction module comprise the gated clock register, the dormancy period register, wake mask register etc. up, owing to have only the work of source and destination module in the one-period, other modules can dormancy to save power consumption, therefore, use the gated clock register to close non-active module clock and then reach purpose of energy saving.The dormancy period register is applicable to based on the application scenario that needs regular dormancy awakening in the time-multiplexed wireless sensor network, certain clock cycle of system hibernates or be waken up when running into interrupt signal, reduced system power dissipation significantly.
(7) radio frequency interface module is connected with radio-frequency module by the SPI interface, receives the data that the MAC module transmits, and the complicated control word that produces radio-frequency module.In addition, when radio-frequency module receives data, produce interrupt signal wake up process device, notice MAC module receives.
(8) MAC protocol instructions module is set operating frequency, transmitted power and modulation pattern etc. under the control of program.When not having data to send, MAC protocol instructions module is according to agreement, by the switching of radio frequency interface module control radio-frequency module between reception and two kinds of patterns of dormancy.When receiving mode, the signal content of MAC protocol instructions module after according to signal strength signal intensity and demodulation comes the validity of judgment data, and obtains data load.When being in emission mode, it at first will intercept channel, when judging that present channel be empty, just launch data, otherwise the wait random time monitors once more, till channel idle.In the network of beacon is arranged, can also in the gateway distributed time slot, carry out transmit operation.
Above-mentioned (7) radio frequency interface module and (8) MAC protocol instructions module have been finished the work of wireless network from physical layer and MAC layer.In wireless sensor network, the frequency of utilization of these operations is very high, with these procotol hardwareization, improved Energy Efficiency Ratio on the one hand, saved power consumption, what processor can parallel processing bottom task on the other hand speeds up, and has improved the ability of processor, has really realized characteristics such as the low-power consumption, low cost of wireless sensor network processor, high integrated, high-performance, intellectuality.
Claims (3)
1. one kind based on the application specific processor on the wireless sensor network node of transmission triggering architecture, comprising:
(1) arithmetical logic instruction module, (2) bit manipulation instruction module, (3) register module, (4) data access command module, (5) control register module, (6) dormancy and Clock management instruction module, (7) radio frequency interface module, (8) MAC protocol instructions module; Wherein, connect by bus between all modules, the source address and the destination address of every instruction specify data transfer according to specific instruction, transmit data between disparate modules, carry out computing in the transmission course of intermodule.
2. wireless sensor network application specific processor according to claim 1 is characterized in that, uses transmission triggering architecture, abandoned traditional command decoder, simple in structure, instruction moduleization, be easy to expand and revise, synchronization has only the work of part command unit, can reduce power consumption.
3. wireless sensor network application specific processor according to claim 1, it is characterized in that, use special-purpose MAC protocol instructions module (8) that the MAC agreement is handled, reduced power consumption, and realize network communication of wireless sensor by the anti-view of special-purpose power consumption wireless sensor network.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101480667A CN101909348A (en) | 2010-04-16 | 2010-04-16 | Transmission triggering frame-based wireless sensor network node special processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101480667A CN101909348A (en) | 2010-04-16 | 2010-04-16 | Transmission triggering frame-based wireless sensor network node special processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101909348A true CN101909348A (en) | 2010-12-08 |
Family
ID=43264631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010101480667A Pending CN101909348A (en) | 2010-04-16 | 2010-04-16 | Transmission triggering frame-based wireless sensor network node special processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101909348A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105573716A (en) * | 2015-12-15 | 2016-05-11 | 西安电子科技大学 | Application specific instruction set processor based on transport triggered architecture (TTA) |
-
2010
- 2010-04-16 CN CN2010101480667A patent/CN101909348A/en active Pending
Non-Patent Citations (2)
| Title |
|---|
| 《International Symposium on System-on-Chip》 20061116 Salmela,P等 Loop Scheduling for Transport Triggered Architecture Processors 第1-2页 1-3 , * |
| 《Symposium on Design Automation of High Performance VLSI Systems》 19940505 Corporaal, H. Design of Transport triggered architecture 第130-135页 1-3 , * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105573716A (en) * | 2015-12-15 | 2016-05-11 | 西安电子科技大学 | Application specific instruction set processor based on transport triggered architecture (TTA) |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10445287B2 (en) | Circuit switch pre-reservation in an on-chip network | |
| CN107635283B (en) | Indoor high-density mobile tag positioning system and positioning method | |
| US8606184B1 (en) | Coexistence message processing mechanism for wireless devices | |
| KR100818297B1 (en) | Method and Apparatus for performing wireless sensor network communicating selectively using Infrared and Radio Frequency Communication | |
| CN102612122A (en) | Low-power-consumption wireless sensor network system and controlling and awaking method thereof | |
| CN109828941A (en) | AXI2WB bus bridge implementation method, device, equipment and storage medium | |
| WO2018231550A1 (en) | Slave-to-slave communication in i3c bus topology | |
| CN108228492A (en) | A kind of multichannel DDR intertexture control method and device | |
| CN110363977A (en) | A kind of remote low power consumption wireless meter reading system based on LoRa technology | |
| CN101207602B (en) | Processing chip for wireless sensor network node | |
| CN202856992U (en) | Low-power-consumption wireless sensor network system | |
| US20050215248A1 (en) | Method and system of communication between a master device and a slave device | |
| CN105119726A (en) | Wireless sensor network node rapid awakening method and apparatus thereof | |
| CN110418397A (en) | A kind of the Internet of Things communication means and system of low-power consumption | |
| CN101909348A (en) | Transmission triggering frame-based wireless sensor network node special processor | |
| Sonavane et al. | Designing wireless sensor network with low cost and low power | |
| CN109743350B (en) | Unloading implementation method for switching communication mode of scientific computing application image area | |
| CN108668239B (en) | Wireless communication system with low power consumption and supporting one-to-many interaction and communication method thereof | |
| CN103813425A (en) | Traffic self-adaptive energy-saving media access control method | |
| CN105099505B (en) | A kind of communication system suitable for pulse ultra-broad band wireless network | |
| Zhu et al. | Design of a wireless sensor network node based on nRF2401 | |
| Kothari et al. | SOC design of a Low Power Wireless Sensor network node for Zigbee Systems | |
| Cui et al. | Energy-saving strategies of wireless sensor networks | |
| Weber et al. | Wake-up Receiver based routing protocol for indoor Wireless Sensor Networks | |
| Luo | Wireless transmission of RS232 interface signal based on ZigBee |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20101208 |