CN101908945B - High-capacity speed self-adaptation and error code-resistant wireless device - Google Patents
High-capacity speed self-adaptation and error code-resistant wireless device Download PDFInfo
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- CN101908945B CN101908945B CN2010102344091A CN201010234409A CN101908945B CN 101908945 B CN101908945 B CN 101908945B CN 2010102344091 A CN2010102344091 A CN 2010102344091A CN 201010234409 A CN201010234409 A CN 201010234409A CN 101908945 B CN101908945 B CN 101908945B
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Abstract
The invention discloses a high-capacity speed self-adaptation and error code-resistant wireless device, relating to speed self-adaptation and error code-resistant equipment based on wireless channel propagation in a communication field. The high-capacity speed self-adaptation and error code-resistant wireless device comprises an MII (Media Independent Interface) unit, a sharing cache, a priority management module, a link speed reporting module, an error control protocol passage and the like. The device realizes the functions of speed self-adaptation adjustment and error control, has the characteristics of high integration level, small size, favorable generality and expansibility, high safety, low cost, convenient maintenance, development and application, unified scheduling and management to various businesses, capability of ensuring the different service quality requirements on the various businesses, and the like, and is especially suitable for processing equipment for accomplishing speed self-adaptation and error code resistance in high-capacity wireless communication networks.
Description
Technical field
The present invention relates to a kind of high-capacity speed self-adaptation and error code-resistant wireless device in the communications field, be specially adapted to accomplish in the big capacity cordless communication network treatment facility of rate adaptation and anti-error code.
Background technology
Because opening that wireless channel is propagated and the time variation that the channel parameter changes, the frequency selective fading that causes channel with the time change decline.The mobility of radio communication can cause the complexity and the changeability at random that receives the place of reception environment again.In addition, along with enriching constantly of integrated services such as voice, video and multimedia, through service traffics, class of business and the service priority of wireless channel all at random variation.Therefore, need adaptive technique to improve, improve channel capacity utilization ratio of wireless resources.During transmission of digital signals, because the undesirable and The noise of channel transfer characteristic, the digital signal of being received mistake can occur inevitably on actual channel.For the situation in known signal to noise ratio is issued to certain bit error rate index, must adopt error-control technique.So how success effectively reaches rate adaptation and anti-error code treatment requirement has just become the realistic problem that in communication network, will solve under radio transmission conditions.
Summary of the invention
Technical problem to be solved by this invention just provides a kind ofly to be propagated based on wireless channel; Utilize self adaptation and error-control technique; Cordless communication network equipment is had the high-capacity speed self-adaptation and the error code-resistant wireless device of universal performance and scalability, and the present invention also has that integrated level height, volume are little, versatility and favorable expandability, safe, cheap, easy to maintenance, be convenient to characteristics such as research and development and application.
The objective of the invention is such realization:
The present invention includes link side MII interface unit 101, link side shared buffer memory module 102, exchange side MII interface unit 104 and shared buffer memory module 105; Also comprise priority management module 103, link rate report module 106 and error control protocol pass 107; Wherein link side MII interface unit 101 outbound ports 1 are connected with link side shared buffer memory module 102 inbound ports 1 through the MII standard interface, carry out metadata cache; Link side shared buffer memory module 102 outbound ports 2 are connected with priority management module 103 inbound ports 1, carry out priority management; Priority management module 103 outbound ports 2 are connected with exchange side MII interface unit 104 inbound ports 1, carry out the MII interface conversion; Exchange side MII interface unit 104 outbound ports 2 are connected with shared cache module 105 inbound ports 1, carry out metadata cache; Shared buffer memory module 105 outbound ports 2 are reported module 106 inbound ports 1 with link rate and are connected, and carry out link rate and report; Link rate is reported module 106 outbound ports 2 and is connected with link side MII interface unit 101 inbound ports 2, carries out the MII interface conversion; Exchange side MII interface unit 104 goes out inbound port 3 and is connected with error control protocol pass 107 discrepancy port ones, and the error control protocol pass is provided; Error control protocol pass 107 goes out inbound port 2 and goes out inbound port 3 with link side MII interface unit 101 and be connected, and the error control protocol pass is provided.
Priority management module 103 of the present invention comprises priority management unit 301, output work queue unit 302, flow controlling unit 303, and wherein link side shared buffer memory module 102 outbound ports 2 are connected with priority management unit 301 inbound ports 1, carry out priority management; Priority management unit 301 outbound ports 2 are connected with output work queue unit 302 inbound ports 1, carry out output work queue; Output work queue unit 302 outbound ports 2 are connected with flow controlling unit 303 inbound ports 1, carry out flow control; Flow controlling unit 303 outbound ports 2 are connected with exchange side MII interface unit 104 inbound ports 1, carry out the MII interface conversion.
Link rate of the present invention is reported module 106, comprises that data are screened module 601, link rate extraction module 602 reports into frame module 603 with link rate; Wherein shared buffer memory module 105 outbound ports 2 are connected with the inbound port 1 that data are screened module 601, and the Frame with link rate information is screened; The outbound port 2 that data are screened module 601 is connected with the inbound port 1 of link rate extraction module 602, carries out link rate and extracts; The inbound port 1 that the outbound port 2 and the link rate of link rate extraction module 602 reports into frame module 603 is connected, and the speed data that need are reported carries out the Ethernet framing on request; The outbound port 2 that link rate reports into frame module 603 is connected with link side MII interface unit 101 inbound ports 2, accomplishes link rate and reports processing.
Error control protocol pass 107 of the present invention comprises error detection unit 701, sliding window protocol unit 702 and retransmission unit 703; Wherein link side MII interface unit 101 goes out inbound port 3 and is connected with the inbound port 2 that goes out of retransmission unit 703, carries out under the situation of need data re-transmission, carrying out data re-transmission; The discrepancy port one of retransmission unit 703 is connected with the inbound port 2 that goes out of sliding window protocol unit 702, carries out the sliding window protocol of data retransmission and handles; The discrepancy port one of sliding window protocol unit 702 is connected with the inbound port 2 that goes out of error detection unit 701, and the error detection result is communicated by letter with sliding window protocol unit 702; The discrepancy port one of error detection unit 701 is connected with the inbound port 3 that goes out of exchange side MII interface unit 104, accomplishes the processing of mistake agreement control.
In this technical scheme, described MII interface is a medium independent interface, and it is the abbreviation of English Medium Independent Interface.
The relative background technology of the present invention has following advantage
1. the present invention adopts link side shared buffer memory 102 and shared buffer memory 105, realizes the management of multiple business uniform dispatching, has advantages such as high reliability, low delay.
2. the present invention adopts priority management module 103, realizes priority management, guarantees the different service quality requirement of multiple business.
3. the present invention adopts link rate to report module 106, according to different link rate self adaptation adjustment port speeds.
4. circuit module design of the present invention has good versatility and autgmentability, and good security performance.
5. each module of the present invention has integrated level height, little, the cheap characteristics of volume.
Description of drawings
Fig. 1 is a logic theory block diagram of the present invention.
Fig. 2 is priority management module 103 theory of constitution block diagrams of the present invention.
Fig. 3 is that link rate of the present invention is reported module 106 theory of constitution block diagrams.
Fig. 4 is error control protocol pass 107 theory of constitution block diagrams of the present invention.
Embodiment
Referring to figs. 1 through Fig. 2; The present invention is made up of link side MII interface unit 101, link side shared buffer memory 102, priority management module 103, exchange side MII interface unit 104, shared buffer memory 105, link rate report module 106, error control protocol pass 107, and each parts is pressed Fig. 1 logic block-diagram connection line.
Wherein link side MII interface unit 101 outbound ports 1 are connected with link side shared buffer memory 102 inbound ports 1 through internal interface; Intermodule adopts standard MII interface to connect; Comprise signals such as RxCLK, RxDV, RxD, RxEr, TxCLK, TxEn, TxD, Col, CRS, embodiment adopts and builds logical circuit in the large-scale F PGA EP2C35 of LXT30271A and altera corp of Intel Company and make.Link side shared buffer memory 102 outbound ports 2 are connected with priority management module 103 inbound ports 1 through internal interface; Accomplish storage; Be the pretreatment operation of further finishing dealing with, embodiment adopts among the large-scale F PGA EP2C35 of altera corp and makes through building logical circuit.Priority management module 103 outbound ports 2 are connected with exchange side MII interface unit 104 inbound ports 1 through internal interface; The ethernet frame that receives is carried out priority queueing according to agreement, data etc., and embodiment adopts among the large-scale F PGA EP2C35 of altera corp and makes through building logical circuit.Exchange side MII interface unit 104 outbound ports 2 are connected with shared buffer memory 105 inbound ports 1 through internal interface; Intermodule adopts standard MII interface to connect; Comprise signals such as RxCLK, RxDV, RxD, RxEr, TxCLK, TxEn, TxD, Col, CRS, embodiment adopts and builds logical circuit in the large-scale F PGA EP2C35 of LXT30271A and altera corp of Intel Company and make.Shared buffer memory 105 outbound ports 2 are reported module 106 inbound ports 1 through internal interface and link rate and are connected; After the examination of the link-state information in data extraction; Carry out link rate and report, embodiment adopts among the large-scale F PGA EP2C35 of altera corp and makes through building logical circuit.Link rate is reported module 106 outbound ports 2 and is connected with link side MII interface unit 101 inbound ports 2 through internal interface; Intermodule adopts standard MII interface to connect; Comprise signals such as RxCLK, RxDV, RxD, RxEr, TxCLK, TxEn, TxD, Col, CRS, embodiment adopts and builds logical circuit in the large-scale F PGA EP2C35 of LXT30271A and altera corp of Intel Company and make.Exchange side MII interface unit 104 goes out inbound port 3 and is connected through internal interface and error control protocol pass 107 discrepancy port ones; The error control protocol pass is provided; Intermodule adopts standard MII interface to connect; Comprise signals such as RxCLK, RxDV, RxD, RxEr, TxCLK, TxEn, TxD, Col, CRS, embodiment adopts and builds logical circuit in the large-scale F PGAEP2C35 of LXT30271A and altera corp of Intel Company and make.Error control protocol pass 107 goes out inbound port 2 and goes out inbound port 3 through internal interface with link side MII interface unit 101 and be connected; The error control protocol pass is provided, and embodiment adopts and builds logical circuit in the large-scale F PGA EP2C35 of LXT30271A and altera corp of Intel Company and make.
Link side shared buffer memory 102 of the present invention act as metadata cache.Make through building logical circuit in the large-scale F PGA EP2C35 chip of embodiment link side shared buffer memory 102 employing a slice altera corps.
The effect of priority management module 103 of the present invention is to carry out priority management.It comprises priority management unit 301, output work queue unit 302, flow controlling unit 303; Fig. 2 is that embodiment of the invention priority management module is formed functional-block diagram; And by its connecting circuit; Wherein the effect of priority management unit 301 is to carry out priority management, and the effect of output work queue unit 302 is to carry out output work queue, and the effect of flow controlling unit 303 is to carry out flow control.Make through building logical circuit in the large-scale F PGA EP2C35 chip of embodiment priority management unit 301, output work queue unit 302, flow controlling unit 303 employing a slice altera corps.
The effect of shared buffer memory 105 of the present invention is metadata caches.Make through building logical circuit in the large-scale F PGA EP2C35 chip of shared buffer memory 105 employing a slice altera corps.
The effect that link rate of the present invention is reported module 106 is to carry out link rate to report.Make through building logical circuit in the large-scale F PGA EP2C35 chip of link rate report module 106 employing a slice altera corps.
The effect of error control protocol pass 107 of the present invention is processing of accomplishing the control of mistake agreement, makes through building logical circuit in the large-scale F PGAEP2C35 chip of error control protocol pass 107 employing a slice altera corps.
The concise and to the point operation principle of the present invention is following: the business of various priority gets into link side shared buffer memory 102 through link side MII interface unit 101; Carry out priority management, output work queue, flow control through priority management module 103, afterwards data are sent into exchange side MII interface unit 104 and send.The data of the miscellaneous service that exchange side MII interface unit 104 receives are sent into shared buffer memory 105, through link rate report module 106 link rate are reported to link side MII interface unit 101 and are carried out the rate adaptation adjustment.Error control protocol pass 107 provides path for the error control agreement, and business is carried out error control.
Mounting structure of the present invention is following:
Parts link side MII interface unit of the present invention 101, link side shared buffer memory 102, priority management module 103, exchange side MII interface unit 104, shared buffer memory 105, link rate report module 106, error control protocol pass 107 be installed in a size long * wide be in 250 millimeters * 138 millimeters the printed board; It is in 400 millimeters * 416 millimeters * 177.80 millimeters the cabinet that printed board is installed in a long * wide * height; Cable socket is installed, the assembly cost invention on the panel.
Claims (4)
1. high-capacity speed self-adaptation and error code-resistant wireless device; It comprises link side MII interface unit (101), link side shared buffer memory module (102), exchange side MII interface unit (104) and shared buffer memory module (105); It is characterized in that: also comprise priority management module (103), link rate report module (106) and error control protocol pass (107); Wherein link side MII interface unit (101) outbound port 1 is connected with link side shared buffer memory module (102) inbound port 1 through the MII standard interface, carries out metadata cache; Link side shared buffer memory module (102) outbound port 2 is connected with priority management module (103) inbound port 1, carries out priority management; Priority management module (103) outbound port 2 is connected with exchange side MII interface unit (104) inbound port 1, carries out the MII interface conversion; Exchange side MII interface unit (104) outbound port 2 is connected with shared cache module (105) inbound port 1, carries out metadata cache; Shared buffer memory module (105) outbound port 2 is reported module (106) inbound port 1 with link rate and is connected, and carries out link rate and reports; Link rate is reported module (106) outbound port 2 and is connected with link side MII interface unit (101) inbound port 2, carries out the MII interface conversion; Exchange side MII interface unit (104) goes out inbound port 3 and is connected with error control protocol pass (107) discrepancy port one, and the error control protocol pass is provided; Error control protocol pass (107) goes out inbound port 2 and goes out inbound port 3 with link side MII interface unit (101) and be connected, and the error control protocol pass is provided.
2. high-capacity speed self-adaptation according to claim 1 and error code-resistant wireless device; It is characterized in that: described priority management module (103); Comprise priority management unit (301), output work queue unit (302), flow controlling unit (303); Wherein link side shared buffer memory module (102) outbound port 2 is connected with priority management unit (301) inbound port 1, carries out priority management; Priority management unit (301) outbound port 2 is connected with output work queue unit (302) inbound port 1, carries out output work queue; Output work queue unit (302) outbound port 2 is connected with flow controlling unit (303) inbound port 1, carries out flow control; Flow controlling unit (303) outbound port 2 is connected with exchange side MII interface unit (104) inbound port 1, carries out the MII interface conversion.
3. high-capacity speed self-adaptation according to claim 1 and 2 and error code-resistant wireless device; It is characterized in that: described link rate is reported module (106), comprises that data are screened module (601), link rate extraction module (602) reports into frame module (603) with link rate; Wherein shared buffer memory module (105) outbound port 2 is connected with the inbound port 1 that data are screened module (601), and the Frame with link rate information is screened; The outbound port 2 that data are screened module (601) is connected with the inbound port 1 of link rate extraction module (602), carries out link rate and extracts; The outbound port 2 of link rate extraction module (602) is connected with the inbound port 1 that link rate reports into frame module (603), and the speed data that need are reported carries out the Ethernet framing on request; The outbound port 2 that link rate reports into frame module (603) is connected with link side MII interface unit (101) inbound port 2, accomplishes link rate and reports processing.
4. according to claim 1 or 3 described high-capacity speed self-adaptation and error code-resistant wireless devices, it is characterized in that: described error control protocol pass (107) comprises error detection unit (701), sliding window protocol unit (702) and retransmission unit (703); Wherein link side MII interface unit (101) goes out inbound port 3 and is connected with the inbound port 2 that goes out of retransmission unit (703), carries out under the situation of need data re-transmission, carrying out data re-transmission; The discrepancy port one of retransmission unit (703) is connected with the inbound port 2 that goes out of sliding window protocol unit (702), carries out the sliding window protocol of data retransmission and handles; The discrepancy port one of sliding window protocol unit (702) is connected with the inbound port 2 that goes out of error detection unit (701), and the error detection result is communicated by letter with sliding window protocol unit (702); The discrepancy port one of error detection unit (701) is connected with the inbound port 3 that goes out of exchange side MII interface unit (104), accomplishes the processing of mistake agreement control.
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