CN101894826B - Circuit connection device - Google Patents

Circuit connection device Download PDF

Info

Publication number
CN101894826B
CN101894826B CN2009101384597A CN200910138459A CN101894826B CN 101894826 B CN101894826 B CN 101894826B CN 2009101384597 A CN2009101384597 A CN 2009101384597A CN 200910138459 A CN200910138459 A CN 200910138459A CN 101894826 B CN101894826 B CN 101894826B
Authority
CN
China
Prior art keywords
dielectric layer
hole
metal column
circuit
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2009101384597A
Other languages
Chinese (zh)
Other versions
CN101894826A (en
Inventor
贾增元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BYD Semiconductor Co Ltd
Original Assignee
BYD Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BYD Co Ltd filed Critical BYD Co Ltd
Priority to CN2009101384597A priority Critical patent/CN101894826B/en
Publication of CN101894826A publication Critical patent/CN101894826A/en
Application granted granted Critical
Publication of CN101894826B publication Critical patent/CN101894826B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a circuit connection device which comprises a first dielectric layer, a second dielectric layer, and an insulating layer positioned between the first dielectric layer and the second dielectric layer. Simultaneously, the invention also discloses another circuit connection device in which at least one end surface of two end surfaces of a metal column is isolated by an insulating ring or an insulating strip and the corresponding dielectric layer, so that the first dielectric layer and the second dielectric layer can not be connected through the metal column into a true electrically conductive path, and the circuit device with the structure becomes the pseudo device accordingly. In addition, because the actual dimension of the insulating ring or the insulating strip is very small and can not be distinguished easily, and the proper outline of the boundary of a through hole becomes very blurry due to processing reasons, the difference between the pseudo device or pseudo circuit connecting line and the true device or true circuit connecting line can not be distinguished easily, and an imitator can not accurately obtain the true circuit structure.

Description

A kind of circuit connecting mechanism
Technical field
The present invention relates to ic manufacturing technology, be specifically related to a kind of circuit connecting mechanism.
Background technology
Current, along with the fast development of integrated circuit technique, the function of integrated circuit is more and more stronger, and its application is broadened also, so IC design exploitation more and more becomes the direction that each manufacturer in the industry gives priority to.Because a successful IC products often means huge economic well-being of workers and staff, therefore, how preventing that the IC products that designs from just illegally being stolen and copying becomes the problem that IC design manufacturer presses for solution.Wherein, prevent that product from illegally being stolen normally secret means through various non-technological layers realize that related content does not belong to the scope that this paper discusses; Because current integrated circuit all is according to the domain of design in advance, utilizes the chip manufacture streamline to make, so various function elements and connected mode in the integrated circuit are more fixing.In ic processing; The functional unit of integrated circuit mainly comprises: various active devices---comprise P-type mos (P-typeMetal Oxide Semiconductor; PMOS), N type metal oxide semiconductor (N-type MetalOxide Semiconductor; NMOS), PNP triode, NPN triode, diode, various passive devices---comprise resistance, electric capacity, inductance, and the circuit connection that above-mentioned various devices are coupled together.
Fig. 1 (a) shows in the existing integrated circuit, the stereogram of metallic circuit line signal between device, and Fig. 1 (b) is the technique of painting signal of the design layout of this metallic circuit line, Fig. 1 (c) then is this metallic circuit line sketch map of section vertically.
It is to be noted; Understand for sketch map is simple in structure; All will omit with other structure that the present invention has nothing to do among said sketch map and each figure hereinafter, these it will be apparent to those skilled in the art that prior art and schemes of the present invention of omitting for basic understanding IC design processing technology can not constitute substantial influence.
In Fig. 1 (a), the rectangle of top is first dielectric layer, and the rectangle of below is second dielectric layer, is that (non-metallic layer, main component is SiO to insulating barrier usually in the middle of two dielectric layers 2, the not shown said insulating barrier of this solid), offer through hole in the insulating barrier, said first, second dielectric layer links to each other through a cylinder in the through hole; Wherein, Said first, second dielectric layer is metal level; The metal column of said cylinder for constituting by metallic copper or aluminium; Thereby first dielectric layer and second dielectric layer form a conductive path through said metal column, this conductive path in the circuit structure of integrated circuit promptly corresponding to described metallic circuit line.
In the integrated circuit processing technology; Said metal column is to carry out Metal Deposition through the through hole that etching is obtained (Via hole or Contact hole) to obtain; Said first, second dielectric layer also deposits after over etching again and obtains; Concrete machining manufacture is those skilled in the art's common practise, and irrelevant with the application, so introduce no longer in detail.
Design layout shown in Fig. 1 (b) is the vertical view of stereochemical structure shown in Fig. 1 (a); Comprising left, center, right totally three rectangle frames (being followed successively by A, B, C), middle rectangle frame B inside also is nested with a littler rectangle frame D (being through hole), and rectangle A is the projection of first dielectric layer on horizontal plane with the zone of B composition; The zone that rectangle B and C form then is the projection of second dielectric layer on horizontal plane; Rectangle B is the intersection of said first dielectric layer and the projection of second dielectric layer on horizontal plane, and the rectangle frame D that wherein comprises is the projection of said metal column on horizontal plane, and is visible; According to this figure and visible according to Fig. 1 (a); The upper surface of metal column links to each other with first dielectric layer, and the lower surface of metal column then links to each other with second dielectric layer, thereby first dielectric layer and second dielectric layer form a conductive path through said metal column.
Fig. 1 (c) is the sectional structure chart after vertically the structure shown in Fig. 1 (a) and (b) being cut open; Wherein the height of the thickness of first, second dielectric layer and metal column and width are not set off a discussion by concrete circuit technology standard decision and irrelevant with the application here.
Fig. 2 (a) and (b) are depicted as the sketch map of another kind of circuit connection structure; With Fig. 1 each figure shown in different; This circuit connection is that metal links to each other the circuit connection that constitutes (for being different from the metallic circuit line described in Fig. 1 with polysilicon (Poly); The circuit connection that hereinafter circuit connection among Fig. 2 is called metal and Poly), Fig. 2 (a) is the technique of painting signal of the design layout of this kind circuit connection, and Fig. 2 (b) then is this circuit connection sketch map of section vertically.Fig. 2 (a) and Fig. 1 (b) are basic identical; Difference only is that first dielectric layer and second dielectric layer among Fig. 1 (b) are metal level; And one of two dielectric layer among Fig. 2 (a) be metal level, another is the Poly layer, and is identical among the connected mode of said two dielectric layers and Fig. 1 (b); Correspondingly; Fig. 2 (b) is and the corresponding profile of Fig. 2 (a); Can know with the contrast of Fig. 1 (c) by Fig. 2 (b); Structure shown in profile shown in Fig. 2 (b) and Fig. 1 (c) is basic identical, and difference only is that first dielectric layer and second dielectric layer among Fig. 1 (c) are metal level, and one of two dielectric layer among Fig. 2 (b) be metal level, another is the Poly layer.
Circuit structure shown in Fig. 1 (a)~(c), Fig. 2 (a)~(b); Though be the structural representation of two kinds of circuit connections; But the various active and passive device (like resistance, electric capacity, inductance, diode, metal-oxide-semiconductor and triode etc.) at integrated circuit all includes similar syndeton---said syndeton is formed by first dielectric layer, second dielectric layer and the metal column that connects said two dielectric layers.
Because above-mentioned each circuit devcie structurally has general regularity, therefore often can tell the various circuit devcies that comprise in this circuit according to the circuit profile of the integrated circuit that machines.These characteristics are often utilized by experienced imitated person; After the encapsulation of integrated circuit is removed; Imitated person often can be through photograph, observation and the analysis to the chip circuit plate; Again reduce the circuit structure of this integrated circuit, thereby this IC products is copied, thereby damaged the interests of IC design manufacturer.
Summary of the invention
The embodiment of the invention provides a kind of circuit connecting mechanism, can form pseudo-device and tseudo circuit line high with real circuits device and circuit connection similarity and that be difficult to distinguish, makes imitated person can't obtain circuit structure accurately.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of circuit connecting mechanism comprises first dielectric layer, second dielectric layer and the insulating barrier between said first dielectric layer and second dielectric layer:
Offer through hole in the said insulating barrier, the both ends open of this through hole is respectively towards said first dielectric layer and second dielectric layer; Said first dielectric layer has first hollow bulb in the position of said through hole one end opening of correspondence;
Said through hole is embedded with metal column; An end face of this metal column is concordant towards the open end of first dielectric layer with said through hole; And be socketed with dead ring with outward flange and first sheet metal that is contained in said first hollow bulb contacts; Said metal column is through dead ring and first dielectric layer insulation isolation, this first sheet metal dorsad one side and said first dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad; Another end face of said metal column is concordant towards the open end of second dielectric layer with said through hole, and contacts with said second dielectric layer.
A kind of circuit connecting mechanism comprises first dielectric layer, second dielectric layer and the insulating barrier between said first dielectric layer and second dielectric layer:
Offer through hole in the said insulating barrier, the both ends open of this through hole is respectively towards said first dielectric layer and second dielectric layer; Said first dielectric layer has first hollow bulb in the position of said through hole one end opening of correspondence;
Said through hole is embedded with metal column; An end face of this metal column is concordant towards the open end of first dielectric layer with said through hole; And contact with first insulating trip in being contained in said first hollow bulb; And said metal column is through first insulating trip and first dielectric layer insulation isolation, this first insulating trip dorsad one side and said first dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad; Another end face of said metal column is concordant towards the open end of second dielectric layer with said through hole, and contacts with said second dielectric layer.
Visible by above-mentioned technical scheme; The sort circuit jockey of the embodiment of the invention is with at least one end face in the metal column both ends of the surface; Keep apart through dead ring or insulating trip and corresponding dielectric layer; Win dielectric layer and second dielectric layer can't be communicated with through metal column becomes a real conductive path, thereby makes the circuit devcie with said structure correspondingly become pseudo-device; In addition; Only can tell a fuzzy etching trace because the profile in border at said through hole both ends open place own is also unintelligible; The actual size of said in addition dead ring or insulating trip is very small again, thereby is difficult to distinguish said pseudo-device or tseudo circuit line and the truly difference of device or real circuits line.Therefore; In case imitated person thinks pseudo-device by mistake to be true device; Just can not obtain real circuit structure exactly; The circuit of copying out also just must be realized the function of true design circuit, thereby through utilizing described circuit connecting mechanism, can realize effectively protection to the circuit structure of integrated circuit.
Description of drawings
Fig. 1 (a) is the perspective view of metallic circuit line between device in the prior art.
Fig. 1 (b) is the sketch map of metallic circuit line design layout in the prior art.
Fig. 1 (c) is a metallic circuit connecting line construction generalized section vertically in the prior art.
Fig. 2 (a) is the sketch map of the design layout of second kind of circuit connection in the prior art.
Fig. 2 (b) is second kind of circuit connection structure generalized section vertically in the prior art.
Fig. 3 is the sketch map of first kind of circuit connecting mechanism cross-section structure in the embodiment of the invention.
Fig. 4 (a) is the sketch map of the design layout of true resistance in the prior art.
Fig. 4 (b) is the sketch map of pseudo-resistance cross-section structure in the embodiment of the invention.
Fig. 5 (a) is the sketch map of the design layout of true electric capacity in the prior art.
Fig. 5 (b) is the sketch map of pseudo-electric capacity cross-section structure in the embodiment of the invention.
Fig. 6 (a) is the sketch map of the design layout of true NMOS pipe in the prior art.
Fig. 6 (b) is the sketch map of pseudo-NMOS pipe cross-section structure in the embodiment of the invention.
Fig. 7 is the sketch map of pseudo-metallic circuit line cross-section structure in the embodiment of the invention.
Fig. 8 is the cross-sectional view of the preferred embodiment of first kind of circuit connecting mechanism in the embodiment of the invention.
Fig. 9 is the sketch map of second kind of circuit connecting mechanism cross-section structure in the embodiment of the invention.
Figure 10 is the cross-sectional view of the preferred embodiment of second kind of circuit connecting mechanism in the embodiment of the invention.
Figure 11 is the sketch map of the third circuit connecting mechanism cross-section structure in the embodiment of the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
The embodiment of the invention provides a kind of circuit connecting mechanism, for the ease of understanding, still adopts sectional structure chart that this device is described here.
Fig. 3 shows the sectional structure chart of said circuit connecting mechanism, comprising: first dielectric layer, second dielectric layer and the insulating barrier between said first dielectric layer and second dielectric layer;
Offer through hole in the said insulating barrier, the both ends open of this through hole is respectively towards said first dielectric layer and second dielectric layer;
Said first dielectric layer has first hollow bulb in the position of said through hole one end opening of correspondence (position A among Fig. 3);
Said second dielectric layer has second hollow bulb in the position of the said through hole other end of correspondence opening (position B among Fig. 3);
Said through hole is embedded with metal column; An end face of this metal column is concordant with said through hole one end opening; And be socketed with dead ring with outward flange and first sheet metal that is contained in said first hollow bulb contacts, this first sheet metal dorsad one side and said first dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad; Another end face of said metal column is concordant with said through hole other end opening; And be socketed with dead ring with outward flange and second sheet metal that is contained in said second hollow bulb contacts, this second sheet metal dorsad one side and said second dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad.
It is thus clear that; The present invention is than prior art; Difference is that the present invention revises the connected mode of metal column and first, second dielectric layer, and feasible original metal column that directly links to each other with first, second dielectric layer is kept apart through dead ring and said first, second dielectric layer.
In order to further specify the application of the present invention in side circuit; To be that example is elaborated below with several kinds of devices in the integrated circuit of reality; Owing to include two or more through holes usually in the concrete device, and the structure of each through hole is all identical and each through hole is separate, therefore for the sake of simplicity; Be example all among each embodiment hereinafter with the structure of single through hole; Metal column and the concrete structure of junction, upper and lower end face thereof in the single through hole only are shown, so explanation is in the lump herein hereinafter explained no longer one by one; Those skilled in the art are to be understood that for the circuit devcie that comprises a plurality of through holes, only need all to adopt identical structure can realize the present invention to each through hole:
One, Fig. 4 (a) is depicted as the design layout of true resistance in the prior art; Visible by left part among Fig. 4 (a); The Poly layer links to each other through the metal column among the through hole A with the first metal layer among the figure; End face of metal column among the through hole A links to each other with the first metal layer at this moment, and another end face links to each other with the Poly layer; In like manner, in the right portions of Fig. 4 (a), the Poly layer links to each other through the metal column among the through hole B with the first metal layer.Need to prove; The first metal layer in left side and the first metal layer on right side are equivalent to two end points of resistance device; Using same names to call is the rule because of according to integrated circuit processing technology field; The two ends of this resistance device place in circuit are necessary for a kind of material, and the first metal layer of the left and right sides itself does not directly link to each other, but the through hole through the left and right sides links to each other with the Poly layer respectively.
Fig. 4 (b) is for using the cross-sectional view of the pseudo-resistance that obtains after the present invention, the embodiment when just the present invention is applied in resistance, and it is corresponding one by one, only distinct in the through hole junction with through-hole structure in the true resistance shown in Fig. 4 (a).In the pseudo-resistance shown in Fig. 4 (b); This moment the metal column in the through hole an end face; It is not physically connected to the first metal layer; And just be connected on the isolated sheet metal of keeping apart with the first metal layer (i.e. first sheet metal among the figure), keep apart through dead ring between said sheet metal and the first metal layer; And another end face of said metal column equally just has been connected on the isolated sheet metal of keeping apart with the Poly layer (i.e. second sheet metal among the figure), isolates through dead ring equally between this sheet metal and the Poly layer.It is thus clear that; This moment, the metal column in the through hole can't be communicated with into a conductive path with said the first metal layer and Poly layer at all, had therefore used the circuit devcie shown in Fig. 4 (b) of circuit connecting mechanism provided by the invention and in fact be on the circuit profile similar and in fact do not have the pseudo-resistance of the electric property of true resistance with resistance.
Two, Fig. 5 (a) is depicted as the design layout of true electric capacity in the prior art; By visible among Fig. 5 (a); As two pole plates of electric capacity, P1, P2 link to each other with the first metal layer through at least one through hole respectively respectively for first polysilicon layer (P1) and second polysilicon layer (P2).
Fig. 5 (b) is for using the cross-sectional view of the pseudo-electric capacity that obtains after the present invention, and it is corresponding one by one, only distinct in the through hole junction with through-hole structure in the true electric capacity shown in Fig. 5 (a).In the pseudo-electric capacity shown in Fig. 5 (b); On the one hand; One of them end face of metal column in the through hole is not physically connected to the first metal layer; And just be connected on the isolated sheet metal of keeping apart with the first metal layer, keep apart through dead ring between said sheet metal and the first metal layer; On the other hand, another end face of this metal column equally just has been connected on the isolated sheet metal of keeping apart with P1 (or P2) layer, isolates through dead ring equally between this sheet metal and P1 (or P2) layer.It is thus clear that; This moment, this metal column can't be communicated with into a conductive path with said the first metal layer and P1 (or P2) layer at all, had therefore used in fact the circuit devcie shown in Fig. 5 (b) of circuit connecting mechanism provided by the invention does not in fact just seemingly have the electric property of true electric capacity on circuit profile with capacitance kind pseudo-electric capacity.
Three, Fig. 6 (a) is depicted as the design layout of true NMOS pipe in the prior art, and by visible among Fig. 6 (a), in the zone of the left and right sides, the first metal layer passes through at least one through hole and active area respectively, and (Active Area, AA) layer links to each other.
Fig. 6 (b) is for using the cross-sectional view of the pseudo-NMOS pipe that obtains after the present invention, and it is corresponding one by one, only distinct in the through hole junction with through-hole structure during the true NMOS shown in Fig. 6 (a) manages.In the pseudo-NMOS pipe shown in Fig. 6 (b); On the one hand; One of them end face of metal column in the through hole is not physically connected to the first metal layer; And just be connected on the isolated sheet metal of keeping apart with the first metal layer, keep apart through dead ring between said sheet metal and the first metal layer; On the other hand, another end face of this metal column equally just has been connected on the isolated sheet metal of keeping apart with the AA layer, isolates through dead ring equally between this sheet metal and the AA layer.It is thus clear that; This moment, this metal column can't be communicated with into a conductive path with said the first metal layer and AA layer at all, therefore used the circuit devcie shown in Fig. 6 (b) of circuit connecting mechanism provided by the invention in fact just on circuit profile with the NMOS tubing like and the pseudo-NMOS that in fact do not have an electric property of true NMOS pipe manages.
Four, according to the design layout of the real metal circuit connection shown in the background technology partial graph 1 (b); The first metal layer links to each other through the metal column in the through hole with second metal level among the figure; End face of metal column in the through hole links to each other with the first metal layer at this moment, and another end face links to each other with second metal level.
Fig. 7 is for using the cross-sectional view of the pseudo-metallic circuit line that obtains after the present invention; Embodiment when the present invention just is applied in circuit connection (being lead); It is corresponding fully, only distinct in the through hole junction with through-hole structure in the real metal circuit connection shown in Fig. 1 (b).In pseudo-metallic circuit line shown in Figure 7; On the one hand; An end face of the metal column in the through hole; It is not physically connected to the first metal layer, and just has been connected on the isolated sheet metal of keeping apart with the first metal layer, keeps apart through dead ring between said sheet metal and the first metal layer; On the other hand, another end face of said metal column equally just has been connected on the isolated sheet metal of keeping apart with second metal level, isolates through dead ring equally between this sheet metal and second metal level.It is thus clear that; This moment, the metal column in the through hole can't be communicated with into a conductive path with said the first metal layer and second metal level at all, and in fact the circuit devcie shown in Figure 7 of therefore having used circuit connecting mechanism provided by the invention is similar and in fact do not have a pseudo-metallic circuit line of the electric property of true lead with the real metal circuit connection on the circuit profile.
As for other circuit devcie that often occurs in the integrated circuit; Like circuit connection of PMOS pipe, NPN and positive-negative-positive triode, diode, inductance and/or metal and Poly etc.; The execution mode of its corresponding pseudo-device; Those skilled in the art can combine the description of common practise and above-mentioned each embodiment rationally to derive, for avoiding repeating to enumerate no longer one by one here.
Visible through above-mentioned each routine displaying; The device that the embodiment of the invention provides is revised with the mode that first, second dielectric layer links to each other metal column in the prior art; In the prior art; The metal column both ends of the surface directly link to each other with first, second dielectric layer, and the present invention is revised as it: the metal column both ends of the surface link to each other with two sheet metals respectively, and every sheet metal further links to each other with said dielectric layer through a dead ring.Therefore, in fact said metal column does not really link to each other with first, second dielectric layer, thereby first dielectric layer and second dielectric layer also just can't be through real conductive paths of metal column connection becoming.Therefore, the circuit connection with said structure is exactly a pseudo-line, and the resistance with said structure is exactly a pseudo-resistance ... visible, any circuit devcie with said structure correspondingly is exactly a pseudo-device.
In addition; Only can tell a fuzzy etching trace because the profile in border at said through hole both ends open place own is also unintelligible; The actual size of said in addition dead ring or insulating trip is very small again; Therefore pseudo-line or pseudo-device that the device processing that provides according to the embodiment of the invention obtains; Under the situation of the design layout that does not have original processing institute foundation, imitated person only is difficult to pick out pseudo-device and true device with observing and taking pictures, thereby can think pseudo-device or pseudo-line by mistake to be true device or true line.Understand easily; Since include numerous circuit devcies in the integrated circuit, therefore, in case imitated person thinks pseudo-device by mistake to be true device; Just can not obtain real circuit structure exactly; The circuit of copying out also just must be realized the function of true design circuit, thereby through utilizing described circuit connecting mechanism, can realize effectively protection to the circuit structure of integrated circuit.
Preferably; In above-mentioned each embodiment; Can also make amendment to the structure of said circuit connecting mechanism; The cross-section structure of the circuit connecting mechanism of this preferred mode is as shown in Figure 8, comprising: first dielectric layer, second dielectric layer and the insulating barrier between said first dielectric layer and second dielectric layer;
Offer through hole in the said insulating barrier, the both ends open of this through hole is respectively towards said first dielectric layer and second dielectric layer;
Said first dielectric layer has first hollow bulb in the position of said through hole one end opening of correspondence;
Said through hole is embedded with metal column, and on an end of second dielectric layer, the end face of this metal column is concordant with the open end of said through hole, and contacts with said second dielectric layer;
On an end of first dielectric layer; The end face of said metal column is concordant with the open end of said through hole; And be socketed with dead ring with outward flange and the sheet metal that is contained in said first hollow bulb contacts; This sheet metal is the one side of said metal column dorsad, and the one side of said insulating barrier is concordant dorsad with said first dielectric layer.
Understand easily; This execution mode means; Keep apart through dead ring with dielectric layer as long as deposit at least at one end in the metal column two ends; Can make said first dielectric layer and second dielectric layer to be communicated with through metal column equally becomes a real conductive path, thereby the circuit devcie with this structure is a pseudo-device just equally also.
The present invention also provides another kind of circuit connecting mechanism, and its cross-section structure is as shown in Figure 9, is found out easily by Fig. 9, and the structure of this moment and difference shown in Figure 3 only are:
Structure shown in Figure 3 includes two parts in first and second hollow bulb, sheet metal and with the dead ring of its socket;
And structure shown in Figure 9 in first and second hollow bulb, then all includes only an insulating trip.
Corresponding with Fig. 3 and two kinds of execution modes shown in Figure 8; Shown in Figure 10 is the another kind of execution mode corresponding with Fig. 9; Unique difference of itself and structure shown in Figure 9 is: in the structure shown in Figure 10; Have only in the dielectric layer in first dielectric layer and second dielectric layer to include hollow bulb, and further comprise the dielectric layer of hollow bulb and the metal column in the through hole is isolated with said through insulating trip.
It may be noted that; Fig. 3 and structure shown in Figure 8 are on the circuit profile effect that finally obtains; Than Fig. 9 and structure shown in Figure 10; Have better camouflage property and fascination (because the area of dead ring is therefore more not obvious much smaller than the area of insulating trip), therefore should be regarded as preferred implementation.But the circuit devcie with Fig. 9 and structure shown in Figure 10 can be used as pseudo-device equally and pseudo-line is used to protect integrated circuit.Because in current integrated circuit; The quantity of circuit devcie is more and more; The process of integrated circuit also dwindles day by day; Imitated person wants from the very small circuit devcie of a large amount of circuit devcies and/or size, to tell pseudo-device or the pseudo-line with Fig. 9 or structure shown in Figure 10, still unusual difficulty.Therefore more and/or integrated circuit technology size hour has pseudo-device or pseudo-line like Fig. 9 and structure shown in Figure 10 when circuit devcie quantity, still can effectively protect the circuit structure of integrated circuit.
At last; Those skilled in the art are according to above-mentioned execution mode; Also expecting easily can be with the scheme cross coupled of above-mentioned two kinds of circuit connecting mechanisms; Thereby draw the present invention other possible implementation can also be arranged, the cross-section structure that this execution mode is corresponding is shown in figure 11: at this moment, all comprise hollow bulb in first dielectric layer and second dielectric layer; Wherein, the hollow bulb of first dielectric layer comprises insulating trip, and the hollow bulb of second dielectric layer then comprises sheet metal and dead ring, and the structure of remainder is all identical with each embodiment of preamble, no longer details.

Claims (6)

1. a circuit connecting mechanism comprises first dielectric layer, second dielectric layer and the insulating barrier between said first dielectric layer and second dielectric layer, it is characterized in that:
Offer through hole in the said insulating barrier, the both ends open of this through hole is respectively towards said first dielectric layer and second dielectric layer; Said first dielectric layer has first hollow bulb in the position of said through hole one end opening of correspondence;
Said through hole is embedded with metal column; An end face of this metal column is concordant towards the open end of first dielectric layer with said through hole; And be socketed with dead ring with outward flange and first sheet metal that is contained in said first hollow bulb contacts; Said metal column is through dead ring and first dielectric layer insulation isolation, this first sheet metal dorsad one side and said first dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad; Another end face of said metal column is concordant towards the open end of second dielectric layer with said through hole, and contacts with said second dielectric layer.
2. device according to claim 1 is characterized in that, said second dielectric layer has second hollow bulb in the position of the said through hole other end of correspondence opening;
Another end face of said metal column is concordant towards the open end of second dielectric layer with said through hole; And be socketed with dead ring with outward flange and second sheet metal that is contained in said second hollow bulb contacts; Said metal column insulate through dead ring and second dielectric layer and contacts, this second sheet metal dorsad one side and said second dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad.
3. device according to claim 1 is characterized in that, said second dielectric layer has second hollow bulb in the position of the said through hole other end of correspondence opening;
Another end face of said metal column is concordant towards the open end of second dielectric layer with said through hole; And contact with insulating trip in being contained in said second hollow bulb; And said metal column insulate through insulating trip and second dielectric layer and contacts, this insulating trip dorsad one side and said second dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad.
4. a circuit connecting mechanism comprises first dielectric layer, second dielectric layer and the insulating barrier between said first dielectric layer and second dielectric layer, it is characterized in that:
Offer through hole in the said insulating barrier, the both ends open of this through hole is respectively towards said first dielectric layer and second dielectric layer; Said first dielectric layer has first hollow bulb in the position of said through hole one end opening of correspondence;
Said through hole is embedded with metal column; An end face of this metal column is concordant towards the open end of first dielectric layer with said through hole; And contact with first insulating trip in being contained in said first hollow bulb; And said metal column is through first insulating trip and first dielectric layer insulation isolation, this first insulating trip dorsad one side and said first dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad; Another end face of said metal column is concordant towards the open end of second dielectric layer with said through hole, and contacts with said second dielectric layer.
5. device according to claim 4 is characterized in that, said second dielectric layer has second hollow bulb in the position of the said through hole other end of correspondence opening;
Another end face of said metal column is concordant towards the open end of second dielectric layer with said through hole; And be socketed with dead ring with outward flange and the sheet metal that is contained in said second hollow bulb contacts; Said metal column insulate through dead ring and second dielectric layer and contacts, this sheet metal dorsad one side and said second dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad.
6. device according to claim 4 is characterized in that, said second dielectric layer has second hollow bulb in the position of the said through hole other end of correspondence opening;
Another end face of said metal column is concordant towards the open end of second dielectric layer with said through hole; And contact with second insulating trip in being contained in said second hollow bulb; And said metal column insulate through insulating trip and second dielectric layer and contacts, this second insulating trip dorsad one side and said second dielectric layer of said metal column the one side of said insulating barrier is concordant dorsad.
CN2009101384597A 2009-05-18 2009-05-18 Circuit connection device Expired - Fee Related CN101894826B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009101384597A CN101894826B (en) 2009-05-18 2009-05-18 Circuit connection device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009101384597A CN101894826B (en) 2009-05-18 2009-05-18 Circuit connection device

Publications (2)

Publication Number Publication Date
CN101894826A CN101894826A (en) 2010-11-24
CN101894826B true CN101894826B (en) 2012-05-30

Family

ID=43103970

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009101384597A Expired - Fee Related CN101894826B (en) 2009-05-18 2009-05-18 Circuit connection device

Country Status (1)

Country Link
CN (1) CN101894826B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104749846B (en) * 2015-04-17 2017-06-30 京东方科技集团股份有限公司 A kind of array base palte and preparation method thereof, display panel

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1825591A (en) * 2005-01-18 2006-08-30 三星电子株式会社 Semiconductor memory device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1825591A (en) * 2005-01-18 2006-08-30 三星电子株式会社 Semiconductor memory device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2003-188174A 2003.07.04

Also Published As

Publication number Publication date
CN101894826A (en) 2010-11-24

Similar Documents

Publication Publication Date Title
US8507957B2 (en) Integrated circuit layouts with power rails under bottom metal layer
KR101934316B1 (en) Power Rail Inbound MOL (MIDDLE OF LINE) Routing
CN104425443B (en) The semiconductor logic circuit manufactured using multilayered structure
CN104576605B (en) Conductor integrated circuit device is used in display device driving
CN1472812A (en) Semiconductor memory device with signal distributive circuits formed above memory unit
CN102881660A (en) Semiconductor device and test method
US6818931B2 (en) Chip design with power rails under transistors
KR102133377B1 (en) Semiconductor device and method for manufacturing the same
US10658294B2 (en) Structure and method for flexible power staple insertion
JP2006510225A5 (en)
CN105609466B (en) Metallic section is as the regional interconnection part in then pad and IC device
CN103378137A (en) Gate electrodes with notches and methods for forming the same
KR101931415B1 (en) Middle-end-of-line strap for standard cell
CN101894826B (en) Circuit connection device
KR100366905B1 (en) Semiconductor integrated circuit having thereon on-chip capacitors
CN100565892C (en) Manufacture method with semiconductor device and this device of imageing sensor
US20060102958A1 (en) Systems and methods for voltage distribution via multiple epitaxial layers
US8674355B2 (en) Integrated circuit test units with integrated physical and electrical test regions
US20200194301A1 (en) Metal interconnection and forming method thereof
CN101136402B (en) Semiconductor device and manufacturing method thereof
CN100468722C (en) Security-sensitive semiconductor product, particularly a smart-card chip
US8729660B2 (en) MEMS integrated chip with cross-area interconnection
US8775995B2 (en) Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer
CN106601706B (en) A kind of semiconductor devices and electronic device
EP4362074A1 (en) Semiconductor device and method for fabricating the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20191227

Address after: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong

Patentee after: SHENZHEN BYD MICROELECTRONICS Co.,Ltd.

Address before: 518118 Pingshan Road, Pingshan Town, Shenzhen, Guangdong, No. 3001, No.

Patentee before: BYD Co.,Ltd.

TR01 Transfer of patent right
CP01 Change in the name or title of a patent holder

Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province

Patentee after: BYD Semiconductor Co.,Ltd.

Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province

Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd.

Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province

Patentee after: BYD Semiconductor Co.,Ltd.

Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province

Patentee before: BYD Semiconductor Co.,Ltd.

CP01 Change in the name or title of a patent holder
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120530

CF01 Termination of patent right due to non-payment of annual fee