CN101894802A - Flash memory and manufacturing method thereof - Google Patents
Flash memory and manufacturing method thereof Download PDFInfo
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- CN101894802A CN101894802A CN2009100518503A CN200910051850A CN101894802A CN 101894802 A CN101894802 A CN 101894802A CN 2009100518503 A CN2009100518503 A CN 2009100518503A CN 200910051850 A CN200910051850 A CN 200910051850A CN 101894802 A CN101894802 A CN 101894802A
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Abstract
The invention provides a flash memory and a manufacturing method thereof. The manufacturing method of the flash memory includes that: a semiconductor substrate is provided, the semiconductor substrate is provided with a grid structure, the semiconductor substrates at the two sides of the grid structure are internally provided with a source electrode and a drain electrode, the semiconductor substrate is provided with an interlayer stratum medium covering the grid structure, wherein the interlayer stratum medium contains a conductive plug which penetrates the interlayer stratum medium and exposes the source electrode, or drain electrode or grid structure; a metal connection line is formed on the conductive plug and partial stratum medium; and a barrier layer is formed on the stratum medium and the metal connection line. The invention improves the programming and erasing speed of flash memory, further durability of programming/erasing cycle is improved, so that the service life of flash memory is prolonged.
Description
Technical field
The present invention relates to semiconductor device fabrication process, especially a kind of flash memory and preparation method thereof.
Background technology
Flash memory is a class nonvolatile memory, even still can the retention tab internal information after power supply is closed; But, and do not need special high voltage in system's electric erasable and overprogram; Flash memory has the advantages that cost is low, density is big.
Flash memory, it generally is (Stack-Gate) structure that is designed to have stacked gate, this structure comprises tunnel oxide, be used for the polysilicon floating gate of store charge, silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide, ONO) dielectric layer and be used for the polysilicon control grid utmost point of control data access between the grid of structure.
The manufacturing process of existing flash memory as shown in Figures 1 to 4.With reference to figure 1, provide Semiconductor substrate 100; Then, form tunnel oxide 106 on Semiconductor substrate 100, the material of tunnel oxide 106 is silica; The technology that tradition forms tunnel oxide 106 is thermal oxidation method, under hot environment, Semiconductor substrate 100 is exposed in the aerobic environment, and described technology realizes in boiler tube usually.
As shown in Figure 2, on tunnel oxide 106, form first conductive layer 108, the material of described first conductive layer 108 for example is a doped polycrystalline silicon, the method of its formation for example is Low Pressure Chemical Vapor Deposition (LPCVD), with the silicomethane is after gas source deposits one deck polysilicon layer, the implantation manufacture craft of mixing again; Then, in forming dielectric layer 116 between grid on first conductive layer 108, the material of dielectric layer 116 for example is silica, silica/silicon nitride or silicon oxide/silicon nitride/silicon oxide (ONO) between these grid; The silicon oxide layer that requires contact with floating grid because of flash memory must possess excellent electrical property, and avoiding under normal voltage, electric leakage or too early electric problem of collapsing take place to be used for the floating grid of store charge; Material with dielectric layer between grid 116 is that silicon oxide/silicon nitride/silicon oxide is an example, form layer of even silicon oxide layer 110 with Low Pressure Chemical Vapor Deposition (LPCVD), then on silicon oxide layer 110, form silicon nitride layer 112, and then form another layer silicon oxide layer 114 with Low Pressure Chemical Vapor Deposition with Low Pressure Chemical Vapor Deposition.
Then, the material of using chemical vapour deposition technique to form second conductive layer, 118, the second conductive layers 118 on dielectric layer between grid 116 for example is doping compound crystal silicon and metal silicide; Form cap layer 120 with chemical vapour deposition technique on second conductive layer 118, the material of described cap layer 120 is a silicon nitride.On cap layer 120, form the photoresist layer (not shown), through overexposure, developing process, the definition gate patterns; With the photoresist layer is mask, and the etching cap layer 120 and second conductive layer 118 form control grid 118a; Continuation is dielectric layer 116, first conductive layer 108 and tunnel oxide 106 between the mask etching grid with the photoresist layer, forms floating grid 108a; Constitute gate stack structure by dielectric layer 116, floating grid 108a and tunnel oxide 106 between cap layer 120, control grid 118a, grid.
Please refer to Fig. 3, photoresist layer is removed in ashing; With the gate stack structure is mask, injects ion, formation source/drain electrode extension area 122 in the Semiconductor substrate 100 of gate stack structure both sides; Then, form side wall 124 with the gate stack structure both sides; With gate stack structure and side wall 124 is mask, injects ion in Semiconductor substrate 100, forms source/drain 102.
As shown in Figure 4, on Semiconductor substrate 100, form interlayer dielectric layer 101 with chemical vapour deposition technique; Spin coating photoresist layer (not shown) on interlayer dielectric layer 101 through after the photoetching process, defines via hole image on photoresist layer; With the photoresist layer is mask, along via hole image etching interlayer dielectric layer 101 to exposing source electrode or drain electrode; In through hole, fill full conductive materials, form conductive plunger 103; Then, on conductive plunger 103, form metal connecting line 104, be electrically connected with source electrode or drain electrode by conductive plunger 103.
Existing formation in the flash memory process, owing to have plasma in the depositing operation that back segment is adopted when forming the high density plasma CVD layer, etching technics, the alloy technique or hydrogen ion diffuses in the tunnel oxide 106, cause durability reduction in flash memory programming/erase cycles process, and cause programming and wipe the speed reduction, influence the life-span of flash memory.
Summary of the invention
The problem that the present invention solves provides a kind of flash memory and preparation method thereof, prevents that durability reduces in flash memory programming/erase cycles process, and programming and wipe speed and reduce, and influences the life-span of flash memory.
The invention provides a kind of manufacture method of flash memory, comprise: Semiconductor substrate is provided, be formed with grid structure on the described Semiconductor substrate, be formed with source electrode and drain electrode in the Semiconductor substrate of grid structure both sides, be formed with the interlayer dielectric layer of overlies gate structure on the Semiconductor substrate, wherein include in the interlayer dielectric layer and run through the conductive plunger that interlayer dielectric layer exposes source electrode or drain electrode or grid structure; On conductive plunger and part interlayer dielectric layer, form metal connecting line; On interlayer dielectric layer and metal connecting line, form the barrier layer.
The present invention also provides a kind of flash memory, comprising: Semiconductor substrate; Be positioned at the grid structure on half conductive substrate; Be positioned at the source electrode and the drain electrode of grid structure semiconductor substrates on two sides; Be positioned on the Semiconductor substrate and the interlayer dielectric layer of overlies gate structure; Run through the conductive plunger that interlayer dielectric layer and source electrode or drain electrode or grid structure are connected; Be positioned at the metal connecting line on conductive plunger and the part interlayer dielectric layer; Be positioned at the barrier layer on interlayer dielectric layer and the metal connecting line.
Compared with prior art, the present invention has the following advantages: after forming metal connecting line, carry out last part technology before, on interlayer dielectric layer and metal connecting line, form the barrier layer.Making plasma in deposition, etching and the alloy process of last part technology and hydrogen ion can't pass the barrier layer enters in the tunnel oxide, improve tunnel oxide and caught the ability of electric charge, improve the programming of flash memory and wiped speed, and then improved the durability of program/erase cycle, the life-span of flash memory is prolonged.
Description of drawings
Fig. 1 to Fig. 4 is the existing schematic diagram of making flash memory;
Fig. 5 is the embodiment flow chart that the present invention forms flash memory;
Fig. 6 to Figure 10 is the embodiment schematic diagram that the present invention makes flash memory.
Embodiment
The flow process that the present invention forms flash memory as shown in Figure 5, execution in step S11, Semiconductor substrate is provided, be formed with grid structure on the described Semiconductor substrate, be formed with source electrode and drain electrode in the Semiconductor substrate of grid structure both sides, be formed with the interlayer dielectric layer of overlies gate structure on the Semiconductor substrate, wherein include in the interlayer dielectric layer and run through the conductive plunger that interlayer dielectric layer exposes source electrode or drain electrode or grid structure; Execution in step S12 forms metal connecting line on conductive plunger and part interlayer dielectric layer; Execution in step S13 forms the barrier layer on interlayer dielectric layer and metal connecting line.
The flash memory that forms based on above-mentioned execution mode comprises: Semiconductor substrate; Be positioned at the grid structure on half conductive substrate; Be positioned at the source electrode and the drain electrode of grid structure semiconductor substrates on two sides; Be positioned on the Semiconductor substrate and the interlayer dielectric layer of overlies gate structure; Run through the conductive plunger that interlayer dielectric layer and source electrode or drain electrode or grid structure are connected; Be positioned at the metal connecting line on conductive plunger and the part interlayer dielectric layer; Be positioned at the barrier layer on interlayer dielectric layer and the metal connecting line.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fig. 6 to Figure 10 is the embodiment schematic diagram that the present invention makes flash memory.As shown in Figure 6, provide Semiconductor substrate 200; Then, on Semiconductor substrate 200, produce oxidizing process or furnace oxidation method formation tunnel oxide 206 with situ steam; The Semiconductor substrate 200 that will have tunnel oxide 206 is put into boiler tube 205, and tunnel oxide 206 is annealed, and makes the dangling bonds termination of the silicon of silica in the tunnel oxide 206 and Semiconductor substrate 200 near interfaces.
As shown in Figure 7, the Semiconductor substrate 200 that will have tunnel oxide 206 is taken out from boiler tube 205; Form first conductive layer 208 then on tunnel oxide 206, its material for example is a doped polycrystalline silicon, and the method that forms first conductive layer 208 for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carries out the ion doping step and forms; And then on ground floor electricity layer 208, form dielectric layer 216 between grid, and the material of dielectric layer 216 for example is silica, silica/silicon nitride or silicon oxide/silicon nitride/silicon oxide (ONO) etc. between grid, the formation method for example is a Low Pressure Chemical Vapor Deposition; The material that forms second conductive layer, 218, the second conductive layers 218 with chemical vapour deposition technique on dielectric layer between grid 216 for example is doped polycrystalline silicon or metal silicide; Form cap layer 220 with chemical vapour deposition technique on second conductive layer 218, the material of cap layer 220 has etching selectivity and has different etching selectivities, for example silicon nitride with the inner layer dielectric layer of follow-up formation.
In the present embodiment, the material of dielectric layer 216 is a silicon oxide/silicon nitride/silicon oxide between grid, and wherein the thickness of ground floor silica 210 is 40 dusts～40 dusts, preferred 50 dusts; The thickness of silicon nitride 212 is 80 dusts～100 dusts, preferred 90 dusts; The thickness of second layer silica 214 is 30 dusts～50 dusts, preferred 40 dusts.
Continuation forms first photoresist layer (not shown) with reference to figure 7 with spin-coating method on cap layer 220, through exposure imaging technology, and the definition gate patterns; With first photoresist layer is mask, the etching cap layer 220 and second conductive layer 218, with second conductive layer 218 after the etching as control grid 218a; Continuing simultaneously with the photoresist layer is mask, and dielectric layer 216 between etch-gate, first conductive layer 208 and tunnel oxide 206 be to exposing Semiconductor substrate, with first conductive layer 208 after the etching as floating grid 208a; Constitute gate stack structure by dielectric layer 216, floating grid 208a and tunnel oxide 206 between cap layer 220, control grid 218a, grid.
As shown in Figure 8, first photoresist layer is removed in ashing; With the gate stack structure is mask, injects ion in the Semiconductor substrate 200 of the active area 204 of gate stack structure both sides, then carries out annealing process, formation source/drain electrode extension area 222; Then, form side wall 224 in the gate stack structure both sides, the formation step of side wall 224 for example forms a layer insulating (not shown) earlier, the material of this insulating barrier is that etching selectivity has different etching selectivities with the inner layer dielectric layer of follow-up formation, silicon nitride for example, utilize the anisotropic etching method to remove partial insulative layer then, form side wall 224 in the gate stack structure sidewall; Be mask then, in Semiconductor substrate 200, inject ion, form source/drain 202 with gate stack structure and side wall 224.
As shown in Figure 9, form interlayer dielectric layer 201 with chemical vapour deposition technique on Semiconductor substrate 200, the material of described interlayer dielectric layer 201 can be silica, tetraethoxysilane etc.; Spin coating photoresist layer (not shown) on interlayer dielectric layer 201 through after the photoetching process, defines via hole image on photoresist layer; With the photoresist layer is mask, with the dry etching method along via hole image etching interlayer dielectric layer 201 to exposing source electrode or drain electrode or grid structure surface.After removing photoresist layer, form conductive layer, and will fill full conductive materials in the through hole on interlayer dielectric layer 201 surfaces; With chemical mechanical polishing method the conductive layer on the interlayer dielectric layer 201 is planarized to and exposes interlayer dielectric layer 201, form conductive plunger 203.Then, on interlayer dielectric layer 201 and conductive plunger 203, form metal connecting line 204 with chemical vapour deposition technique or galvanoplastic, etching adopts lithographic method to keep metal connecting line 204 on part interlayer dielectric layer 201 and conductive plunger 203, makes it pass through conductive plunger 203 and source electrode or drain electrode or grid structure and is electrically connected.
Owing to have plasma in the back segment depositing operation, etching technics, alloy technique or hydrogen ion diffuses in the tunnel oxide 206, cause durability reduction in flash memory programming/erase cycles process, and cause programming and wipe the speed reduction, influence the life-span of flash memory.For addressing the above problem, as shown in figure 10, forming thickness with chemical vapour deposition technique on interlayer dielectric layer 201 and metal connecting line 204 is the barrier layer 223 of 200 dusts～600 dusts, silicon oxide layer or silicon nitride layer that described barrier layer 223 can be an individual layer.Barrier layer 223 can prevent that plasma in deposition, etching and the alloy process of last part technology and hydrogen ion from passing and enter in the tunnel oxide 206, improve tunnel oxide 206 and caught the ability of electric charge, improve the programming of flash memory and wiped speed, and then improved the durability of program/erase cycle, the life-span of flash memory is prolonged.
And owing to the erase operation of stacked gate is undertaken by polysilicon-polysilicon silicon to tunnel oxide, and programming operation utilizes the drain region hot carrier to inject to carry out, thus in the erase operation that is reduced in flash memory of program/erase durability than more important in the programming operation.In addition, because the oxide layer that is positioned on the barrier layer 223 is the silica that adopts the high-density plasma vapour deposition process to form, its thickness is 6000 dusts～8000 dusts, is easy to pass other rete at the process ionic medium body that forms oxide layer and hydrogen ion and enters in the tunnel oxide 206.Though the main effect on barrier layer 223 is isolation layers, can well completely cuts off of the injury of the plasma of oxide layer in making, and prevent that plasma from cruising in tunnel oxide metal connecting line; But at above-mentioned reason, also need the thickness on described barrier layer 223 is selected, when the material on barrier layer 223 was silica, the thick more blocking effect of thickness was good more, so barrier layer 223 thickness are that the isolated effect of first oxide layer of 600 dusts obviously is better than 200 dusts.But the thickness on barrier layer 223 can not be blocked up, can influence the electric conductivity of device.
The flash memory that forms based on the foregoing description comprises: Semiconductor substrate 200; Grid structure, be positioned on half conductive substrate 200, wherein grid structure comprises the tunnel oxide 206 that is positioned on the Semiconductor substrate 200, be positioned at the floating grid 208a on the tunnel oxide 206, be positioned at dielectric layer 216 between the grid on the floating grid 208a, be positioned at the control grid 218a on the dielectric layer 216 between grid, be positioned at the cap layer 220 on the control grid 218a; Source/drain electrode extension area 222 is positioned at the Semiconductor substrate 200 of grid structure both sides; Side wall 224 is positioned at the grid structure both sides; Source/drain 202 is positioned at the Semiconductor substrate 200 of grid structure and side wall 224 both sides, is in source/drain electrode extension area 222 belows; Interlayer dielectric layer 201 is positioned on the Semiconductor substrate 200 and overlies gate structure; Conductive plunger 203 runs through interlayer dielectric layer 201 and source electrode or drain electrode or grid structure and is connected; Metal connecting line 204 is positioned on conductive plunger 203 and the part interlayer dielectric layer 201; Barrier layer 223 is positioned on interlayer dielectric layer 201 and the metal connecting line 204.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the manufacture method of a flash memory is characterized in that, comprising:
Semiconductor substrate is provided, be formed with grid structure on the described Semiconductor substrate, be formed with source electrode and drain electrode in the Semiconductor substrate of grid structure both sides, be formed with the interlayer dielectric layer of overlies gate structure on the Semiconductor substrate, wherein include in the interlayer dielectric layer and run through the conductive plunger that interlayer dielectric layer exposes source electrode or drain electrode or grid structure;
On conductive plunger and part interlayer dielectric layer, form metal connecting line;
On interlayer dielectric layer and metal connecting line, form the barrier layer.
2. according to the manufacture method of the described flash memory of claim 1, it is characterized in that: the material on described barrier layer is silica or silicon nitride.
3. according to the manufacture method of the described flash memory of claim 2, it is characterized in that: the method that forms the barrier layer is a chemical vapour deposition technique.
4. according to the manufacture method of the described flash memory of claim 3, it is characterized in that: the thickness on described barrier layer is 200 dusts～600 dusts.
5. according to the manufacture method of the described flash memory of claim 1, it is characterized in that: form and also comprise step behind the described barrier layer:
On the barrier layer, form the oxide layer that thickness is 6000 dusts～8000 dusts with the high density plasma CVD method.
6. flash memory of forming of manufacture method according to claim 1, comprise: Semiconductor substrate, be positioned at the grid structure on half conductive substrate, be positioned at the source electrode and the drain electrode of grid structure semiconductor substrates on two sides, be positioned on the Semiconductor substrate and the interlayer dielectric layer of overlies gate structure, run through the conductive plunger that interlayer dielectric layer and source electrode or drain electrode or grid structure are connected, be positioned at the metal connecting line on conductive plunger and the part interlayer dielectric layer; It is characterized in that, also comprise: be positioned at the barrier layer on interlayer dielectric layer and the metal connecting line.
7. according to the described flash memory of claim 6, it is characterized in that: the material on described barrier layer is silica or silicon nitride.
8. according to the described flash memory of claim 7, it is characterized in that: the thickness on described barrier layer is 200 dusts～600 dusts.
9. according to the described flash memory of claim 6, it is characterized in that: also comprise: be positioned at the oxide layer on the barrier layer.
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| CN2009100518503A CN101894802A (en) | 2009-05-22 | 2009-05-22 | Flash memory and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779210A (en) * | 2014-01-14 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of flash device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104779210A (en) * | 2014-01-14 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of flash device |
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Open date: 20101124 |