CN101875480A - Front end micro cavity - Google Patents
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- CN101875480A CN101875480A CN2010102096890A CN201010209689A CN101875480A CN 101875480 A CN101875480 A CN 101875480A CN 2010102096890 A CN2010102096890 A CN 2010102096890A CN 201010209689 A CN201010209689 A CN 201010209689A CN 101875480 A CN101875480 A CN 101875480A
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Abstract
The present invention relates to a kind of method that in the technology of for example CMOS technology, forms microcavity, preferably include MEMS (MEMS).The MEMS resonator is just concentrated research in many research groups, and some firstlings are published in the recent period.Such device provides high quality factor (Q-factor), small size, highly integrated and potential low cost.These devices are estimated to replace bulky quartz crystals in high-precision oscillators, also can be used as the RF wave filter.Oscillator can be used in timing and the frequency reference application, such as mobile phone, the device that comprises bluetooth module and the RF module in other numerals and the telecommunication installation.
Description
Technical field
The present invention relates to a kind of method that forms microcavity, preferably include such as the MEMS in the technology of CMOS technology (MEMS).
Background technology
The MEMS resonator is just concentrated research in many research groups, and some firstlings are published in the recent period.Such device provides high quality factor (Q-factor), small size, highly integrated and potential low cost.These devices are estimated to replace bulky quartz crystals in high-precision oscillators, also can be used as the RF wave filter.Oscillator can be used in timing and the frequency reference application, such as mobile phone, the device that comprises bluetooth module and the RF module in other numerals and the telecommunication installation.
MEMS (MEMS) is very little technology, and it merges in nano-electromechanical system (NEMS) and the nanometer technology at nanoscale.MEMS also is known as micromechanics (in Japan) or microsystems technology-MST (in Europe).MEMS is independent of and is different from the hypothesis visual field (hypothetical vision) of molecule nano technology or molectronics.NEMS is made up of at the element of 1 to 100 μ m (promptly 0.001 to 0.1mm) size, and MEMS device general size scope is m to 1 millimeter of 20 μ.And they are made up of the element (as microsensor) of central location, microprocessor and several and the external influence of deal with data usually.In these size class, the normal structure of classical physics is always incorrect.Because high surface area and the volume ratio of MEMS, surpass bulk effect such as inertia or thermal mass such as static and wetting skin effect.
The MEMS device can be protected in cutting and moulding by the wafer-class encapsulation process.
Because the MEMS device is fragile, for example, owing to typically exist moving-member, and device performance is subjected to impurity (for example, particulate) influence, and they must be protected during wafer cutting and bonding.Because air pressure has a direct impact the MEMS Devices Characteristics, some MEMS structures (as, MEMS resonator) need and environment between gas-tight seal.For function optimization, other MEMS structure (as, mems switch) need accurately control gaseous environment.Integrated wafer-class encapsulation process can realize this protection.This means that the MEMS structure example is as being structured in the chamber with package casing, for example by using the procedure of processing of state-of-the-art technology.
Various files have been described the manufacturing of MEMS device.
US2007/0281381 A1 has described a kind of method of the MEMS of manufacturing equipment, in case CMOS technology is finished, discharges the MEMS structure from the back side, and can not damage cmos circuit.This device can be covered by polysilicon.When passing back etched, the silica of SOI wafer can be used as etching to be stopped.Subsequently, surround the silica of this device, discharge this structure by etching.
Though should be noted that claim MEMS can before the CMOS manufacturing step, between or make afterwards, the CMOS manufacturing step is not used to make MEMS.Further, do not provide the details of this manufacturing at all, say nothing of process sequence.
And as the shortcoming of top method, release opening overleaf is big relatively opening, therefore can not come by simple deposition technique closed, at least can not integrality that does not endanger MEMS and performance situation under so.Therefore, this opening needs for example to come by the wafer bonding closed.This is expensive, causes the risk of damaging or polluting MEMS, and bothers relatively.
US2008/0054759 A1 relates to the MEMS device of making on the wafer identical with cmos circuit.
For example the disclosed structure of those of Fig. 3 a-d relates to many extra processing steps, so that device and circuit to be provided, for example is used to form electrode and cladding material.These processing steps normally can not obtain in standard CMOS process.
And, should be noted that usually separately processing of MEMS, for example among Fig. 9 a-f like that, only substrate is identical.This integrated be expensive.Discharge the morning of MEMS structure and also often cause production loss, for example machinery in technology subsequently and thermal pressure and vibration.
WO2008/067294 A1 relates to the formation of the micro-structural of using CMOS technology.
In typical MEMS structure shown in Fig. 2 a-e.MEMS structure (290) comprises the material (212,240) that piles up, and the thickness of its middle level (240) is determined by the DRIE etching step, do not needed the clear and definite layer that stops.Thereby the quality of this structure does not have controlled, is not well controlled at least, and this is very big defective to resonator, this in addition can cause the device of cisco unity malfunction.
And, in order to encapsulate this structure, need use two wafer bonding steps from front and back.This is expensive and time-consuming.
The scheme of these prior aries produces thick layer, therefore, has introduced big pattern (topography), and this makes and standard technology integrated very difficult.And, the structure that needs the space is provided, as the cap when technology finishes, need around the exceptional space of the microcavity that generally includes device.Usually also need extra technology, it further produces additional pattern.Because a variety of causes, this pattern is not expected, for example patterning subsequently, sealing etc.And, have only company seldom really MEMS (MEMS) and standard technology (as CMOS technology) can be integrated at present.These are being important disadvantages aspect cost, reliability and the manufacturability.
Therefore, still need improved technology to make microcavity, for example be used for the wafer level chip-scale encapsulation of MEMS.
The present invention is intended to overcome one or more shortcomings of prior art, not other characteristic of entail dangers to microcavity.
Summary of the invention
The present invention relates to a kind of method that forms microcavity, this microcavity for example comprises MEMS (MEMS), in a technology, further form at least one semiconductor element concurrently with microcavity, and has a common processing step, CMOS technology for example discharges the step of microcavity after the formation that is included in described at least one semiconductor element is finished; A kind of microcavity comprises for example MEMS structure, and it comprises the release opening of passing substrate, and described microcavity is formed on this substrate; A kind of device that comprises top microcavity; And a kind of RF circuit that comprises top microcavity.
This method is used for for example device of accelerometer and various MEMS, and they can be packed, and they for example suppress (damp) by high pressure, and they are without any need for getter (getter).Note for example having on thick MEMS that the embodiment of cap-wafer may comprise getter, for example in gyrostatic situation (referring to for example Figure 14).
This method further provides and the cooperating of CMOS technology, and for example polysilicon or the connection metal that uses at common (MEMS and CMOS) saved masks, for example cost and processing time.
Like this, providing really can be with microcavity and the integrated method of standard technology.The example of this technology is silicon-on-insulator (SOI) technology, and it not only is well suited for makes thin SOI micro chamber device, and is suitable for it is combined with high voltage electronics.Fa Zhan a kind of main element is a cavity in the method for the invention, and this cavity is:
1) gas-tight seal: vacuum for example; And
2) little, i.e. wafer level chip-scale encapsulation (WL-CSP); And
3) firm; Cavity should be owing to the briquetting pressure of Plastic Package is damaged.
The present invention produces the layer and the space-saving structure of relative thin, as cap.And microcavity (as MEMS (MEMS)) is present and standard technology (as CMOS technology) is fully-integrated.Aspect cost, reliability and manufacturability, these are very big advantages.
In first aspect, the present invention relates to a kind of method that forms microcavity, this microcavity comprises for example MEMS (MEMS), in a technology, further form at least one semiconductor element concurrently with microcavity, and have common processing step, for example CMOS technology wherein preferably adopts polysilicon layer, for example the polysilicon gate layer adds cap to microcavity, comprises step:
-after finishing, described at least one semiconductor element formation discharges microcavity.
This microcavity can be any cavity that has in the preliminary dimension of micron or nanometer scale.Usually for example remove the predetermined portions of existing material, form microcavity by etching.
Notice that opposite with prior art, microcavity and at least one semiconductor element are really to make, and have common processing step in a technological process.
And release opening is relatively little opening, therefore can be closed by simple deposition technique, not the integrality of entail dangers to MEMS and performance.In a preferred embodiment, for example greater than 10 μ m or greater than the thick MEMS of 100 μ m and the thin MEMS of common a few μ m, one has high frequency, as greater than 1MHz or greater than 10MHz or even greater than 1GHz, and one have low frequency, as less than 1MHz, though usually at more than several times of 10KHz.
In a preferred embodiment, the present invention for example is different from further that US2007/0281381A1 is, the back side uses the splash-proofing sputtering metal layer to replace the wafer of bonding to seal.
In a preferred embodiment, the present invention for example further is different from, and US2007/0281381A1 is, the present invention directly uses the cap of the polysilicon gate layer of CMOS technology as the MEMS chamber, and is opposite with the more common etch resistant polysilicon cap of US2007/0281381 A1.
In a preferred embodiment, the present invention relates to the microcavity of a kind of MEMS of comprising.
Advantageously, the technology that forms semiconductor element is known technology, for example CMOS technology.Even more preferably so-called ABCD technology.An importance of the present invention is that microcavity is released after the technology that forms semiconductor devices finishes.Release means that microcavity comprises a kind of material, and this material is removed, and stays next cavity thus thereafter.Technological design more cleverly allows to form the cavity of Any shape, size, complexity etc. in principle.Therefore, the present invention allows the degree significantly certainly in the cavity design.
Another advantage is that various processing steps can be used jointly,, is used to form MEMS structure and semiconductor element that is.Like this, can use for example etching, the formation silica (as in STI or LOCOS) of substrate, silica (as the BOX layer), monocrystalline silicon layer, for example groove jointly, the deposition of one or more metal levels, the grinding of the deposition of one or more patterning step, polysilicon, second etch, one or more inter-metal dielectric layer and substrate, in the processing step one or more.
Preferably, select for use polysilicon layer that microcavity is added cap, for example the polysilicon gate layer.For other purposes, this polysilicon layer can be used in the CMOS technology, as, be used to limit the polysilicon layer of at least one semiconductor element.Even more preferably, this polysilicon layer is used to limit grid layer.Like this, the preferred embodiment further is reduced by at least an essential masks that is used to form microcavity, because be used to limit the cap that the mask of polysilicon gate for example also can be used to limit microcavity.Further advantage is not need independent sealing step, because this cap provides identical functions.This cap is provided as covering the layer of the microcavity that will form.
Therefore, the invention provides following advantage.
The MEMS size of devices can being determined in technology in early days, allows some zone (for example lead-in wire also can be MEMS self) correctly to be mixed to realize good contact.This for example can use the existing injection and the diffusing step of standard CMOS process to realize.
Adopt the rigid material package of MEMS device, opposite with the technology of its release, this means during technology does not need special care to processing of wafers.
Cavity may still need extra material to strengthen, but this can add when technology finishes fully, as, by the thicker passivation stack of use, and do not introduce extra pattern.
In MEMS and situation that SOI technology combines,, in principle, may use the trench isolations mask (MTI) that in SOI technology for example, has existed for MEMS limits (ditch).
Front end MEMS cap forms to generally include and uses the acquiescence layer: the gate polysilicon layer or first metal interconnecting layer are most probable a kind of.Therefore, for CMOS, do not have extra pattern is to be produced by MEMS at all.
Comprise that at the MEMS cap it also can be electrically connected, to form out-of-plane electrode in the situation of conductive layer (for example grid polycrystalline silicon or alternative metal interconnected).For example, this will make not only motion sensitive in the opposite of sensor, and responsive on 3D fully.The 3D sensor needs at least two devices usually completely.This 3D sensor also can be expected.
For the 1D in the flat surface sensor in pressure sensor for example, cap layer also can be used as unique electrode.
For prior art, owing to be not to adopt second wafer (wafer and wafer bonding), seal the back side but adopt metal to deposit, it is very low that total die thickness can keep.This has significant benefits when needs approach device (for example application of IC cards).Therefore, the present invention also relates to so thin device.
MEMS is integrated with the monolithic of the CMOS that is used for electronic device (setover, encourage, read etc.), will improve (reducing) power consumption usually and improve sensitivity/resolution ratio because do not exist by two independently the data that cause of tube core and/power loss.Therefore, the invention still further relates to so integrated.
In a preferred embodiment, the present invention relates to a kind of method, comprise step:
-substrate is provided, as silicon substrate, this substrate has the front and the back side that comprises at least one semiconductor element,
-first group of one or more release opening at the described back side of passing substrate is provided, the group that release opening is selected from groove, passage, hole and constitutes,
-passing described one or more release opening carries out etching, to discharge microcavity.
Preferably, provide described at least one semiconductor element in first side (for example positive), and discharge microcavity at opposite side (for example back side), otherwise or.At opposite side (for example back side) one or more release opening need be set, so that pass the material that substrate carries out etching and removes cavity inside.
Preferably, with form described at least one semiconductor element concurrently, in formation preferably includes the further processing step of microcavity of MEMS, form structure.
Because most of steps of this technology comprise silicon substrate, this substrate is preferred aspect machinability.
Described one or more release opening can be selected from the group that groove, passage, hole and combination thereof constitute.The gross area of release opening is preferably enough big, and is easy of the microcavity that will discharge to allow etching material, and allows the short processing time.Preferably, the gross area of opening is the 0.3%-50% on obtainable surface, preferably 5-40%, for example 10-25%.For example, can use be of a size of 0.6 μ mx0.6 μ m, spacing is the hole of 9 μ m.The density of opening is generally every μ m at 0.01-0.25
2, as the every μ m of 0.05-0.1
2Preferably, release opening is positioned at MEMS structure below, thereby saves the space.Preferably, the area of a release opening is enough greatly to allow etch chemistries approaching easily.
In a preferred embodiment, the present invention relates to a kind of method, further may further comprise the steps:
-for example by the aluminium of sputtering sedimentation, on the back side of substrate, deposit for example gas-tight seal layer of metal level, to seal by etching microcavity that form, that preferably include the MEMS device.
Preferably, microcavity is carried out gas-tight seal, with the function that minimizes ambient influnence and optimize microcavity.Preferably, microcavity comprises MEMS.
Preferably, sealant is the dielectric layer of metal level, for example oxide or silicon nitride, although be preferably metal level.Preferably, described metal level passes through sputtering sedimentation.Even more preferably be aluminium lamination.Utilizing sputter to carry out al deposition under the low-pressure (μ bar scope) very much.Then, " capture " this pressure in cavity, this uses (for example MEMS resonator, gyroscope) for those MEMS that need vacuum is preferred.And aluminium also is fully airtight.Be significantly higher than (though remaining the pressure that reduces, the mbar scope) under the pressure of aluminium, depositing the dielectric layer of PECVD silica for example or silicon nitride.These layers also still are subjected to the influence of the degassing (out-gas), have further improved the pressure in the cavity that seals.
In a preferred embodiment, the present invention relates to a kind of method, wherein microcavity comprises MEMS, and wherein before etching microcavity comprise for example dielectric substance of oxide, this method further may further comprise the steps:
-in the positive dielectric layer deposition of substrate, BOX layer for example,
-on described dielectric layer, deposit silicon layer,
-on described silicon layer, form second group of one or more release opening, the group that release opening is selected from groove, passage, hole and constitutes,
-in described silicon layer, form dielectric medium structure, and adopt dielectric substance to fill second group of one or more release opening,
-below the MEMS device, pass first group of one or more release opening of described back etched of substrate, be upward through the arrival dielectric layer always, remove dielectric substance in second group of one or more release opening in described silicon layer, and in described silicon layer, remove dielectric medium structure, thereby discharge MEMS
Wherein, etching preferably is selected from wet method or steam HF etching.
Preferably, dielectric layer deposition on the front of substrate, for example BOX layer.BOX layer (oxide of burying) also can be as the layer that stops of the release aperture of etched back.Alternatively, can use the SmartCut wafer, this wafer has the layer that contains oxide, this oxide may be oxidation rather than deposition, subsequently, two wafers that will have an oxide layer are bonding each other.One of these two wafers can carry out hydrogen and inject, and cause separating in situation lower floors such as pressure, temperature risings.The SOI substrate is provided like this.
Further preferably be on described dielectric layer, to deposit silicon layer, thereby form soi structure.Compare with the etching of timing, among the SOI thickness of silicon layer and thereby the quality control of MEMS device much better, stay silicon fiml overleaf after the etching.
Even further preferably in described silicon layer, forming second group of one or more release opening, release opening is selected from the group that groove, passage, hole and combination thereof are constituted.This second group of opening preferably has and the described similar characteristic of above-mentioned first group of opening.
Preferably, form the dielectric medium structure in the described silicon layer, adopt dielectric substance to fill second group of one or more release opening, thereby allow to form microcavity or its part further removing described dielectric in the treatment step.
In principle, the dielectric substance that uses in various processing steps in whole the present invention can be identical or different.For example importantly can optimize relative etching performance, to allow the big of microcavity design from degree with respect to material around.Described dielectric substance can be silica, buried oxide, LOCOS, etc., perhaps provide the dielectric substance of further advantage and/or characteristic, as height-K medium.
By first group of one or more release opening of described back etched of below the MEMS device, passing substrate, thereby be upward through always and arrive dielectric layer and remove in the described silicon layer dielectric substance in second group of one or more release opening, and remove dielectric medium structure in the described silicon layer, discharge MEMS.
In a preferred embodiment, etching preferably is selected from wet method or steam HF etching.HF (wet method or steam) is very selective for silicon, and it is an etching oxidation silicon in fact.Steam HF is preferred, because it does not need drying after etching, and the dry static friction (stiction) that can cause MEMS device and chamber wall.
In a preferred embodiment, the present invention relates to a kind of method, wherein, before etching, the back side of substrate is milled to the predetermined thickness at its back side, for example reaches the thickness of 50-400 μ m, preferably reaches the thickness of 100 μ m.
In order to reduce etching period, substrate can grind and be decreased to preferably as far as possible little thickness.Yet aspect intensity, substrate should be not thin excessively.
In a preferred embodiment, the present invention relates to a kind of method, further may further comprise the steps:
-substrate is provided, wherein beginning material is the thin film SOI substrate of standard, this SOI substrate comprises that buried silicon oxide layer (BOX) and thickness that monocrystalline substrate, thickness are generally 0.2-10 μ m (for example thickness is 1 μ m) are the thin single crystal silicon layer of 0.2-10 μ m (for example thickness is 1.5 μ m)
-for example by in described silicon layer, forming second group of one or more release opening and by etching with fill etching part and in described silicon layer, form dielectric medium structure, limit the microcavity that for example comprises the MEMS structure, this dielectric medium structure will discharge in handling after a while
One or more release opening in the described silicon layer of etching wherein, arrive BOX downwards, thereby except some anchor points, isolate the MEMS structure fully, anchor point forms the part of MEMS structure, MEMS is connected to environment on every side, wherein in some cases, this step with combine at the obtainable isolation step of one or more release opening (for example trench isolations step)
Silica-filled described one or more release opening of-employing,
-for example utilize the field of standard to isolate (for example STI or LOCOS), the top surface of separating MEMS, adopt the polysilicon layer of CMOS grid to cover whole M EMS structure subsequently in an example, the overlapping that wherein exceeds the cap layer (polysilicon) at the edge of MEMS structure and oxide (STI or LOCOS) is defined as and makes that some oxides are stayed on the side during release etch subsequently, and
-in identical step, also provide normal to isolate and gate patternization.
An advantage of the invention is and to use the SOI substrate.
In a preferred embodiment, the present invention relates to a kind of method, further comprise forming a separate layer,
Wherein, with first inter-metal dielectric (IMD) layer or LOCOS or STI as separate layer, and/or wherein metal (METAL1) or grid polycrystalline silicon as cap layer.
An advantage is not need extra processing, does not have owing to extra layer exists additional pattern.And because these layers are made up of the cmos layer of standard, these layers can be electrically connected according to the mode of acquiescence.
In second aspect, the present invention relates to a kind of microcavity, for example comprise the MEMS structure, comprise the release opening of passing substrate, on substrate, form described microcavity.Usually by the invention provides this microcavity.
In a preferred embodiment, the present invention relates to a kind of microcavity, further be included at least one semiconductor element on first side of described substrate, and the gas-tight seal layer on second side of described substrate.
This microcavity provides the advantage identical with this method.
The combining of at least one thick MEMS and at least one thin MEMS on same substrate more preferably.In present technique, a thick resonator and a thin resonator that is used for high frequency that is used for low frequency integrates.
A kind of interested and unique application is for example two combinations of MEMS oscillator in a clock chip.For example, on the one hand, a 32KHz (more accurately, 2
15Hz) clock appears in many application usually, as is used for the low power standby option, and it can have limited absolute frequency precision, on the other hand, more clock or timing device are used, and it needs much higher frequency (several MHz, for example 48MHz) and much better frequency accuracy.
For the high frequency clock system, USB2 for example at 6MHz or higher, is commonly used now up to the device of the fixed frequency of 48MHz.These HF oscillator application are very crucial to shake, as clock, Digital Video System or other digital signal processors of audio player, processor, or USB2, USB3.
Like this, in the present invention, low-frequency resonator and high-frequency reonsator are made on same tube core.This technological process also is suitable for these resonators and (Bi) cmos circuit are integrated very much, and (Bi) cmos circuit is bonded to one group two (or more a plurality of) oscilator system based on MEMS with it.
The integrated MEMS resonator that is used for low frequency (LF) clock is that these two kinds of devices need different thickness of detector ideally with the common problem of the thin MEMS resonator that is used for high frequency (HF).This programme provides a kind of technology with two kinds of layer thicknesses.These are thin soi layer and thick processing wafer substrates.
For the HF resonator, the inventor observes following phenomenon.
For the HF frequency oscillator, the resonator of the fine qualification of thickness between 1 to 2 μ m is easily.In our example, use the thick SOI of 1.5 μ m.The advantage of these gadget thickness is to realize good doping, and the etching of device trenches and release aperture can be made compatible with standard CMOS.
Use very fine photoetching (have+/-the DUV stepper of 0.2 μ m gap ability of 10nm precision is many 8 " factory is obtainable standard device) can produce less than the technology of 500ppm and scatter (process spread), this allows to be used for the clock of USB2 standard (+/-300ppm absolute frequency precision).Together with standard CMOS groove etching technique, can obtain to be better than+/-excellent precision of 20nm, do not need more complicated deep reactive ion etch technology.Use for example SmartCut
The advantage of SOI is that good layer thickness limits, and this has provided the more accurate resonant frequency of reproducing of device together with other aspects.For higher frequency, need higher accuracy usually, because the wavelength of the standing wave in the resonator will be than those weak points of high frequency.For example, in bulk-mode resonator, for 26MHz keynote (ground tone), device size is about 160 μ m.Frequency is high more, and required how much qualifications of resonator are just good more usually.The use of this precision and those standard IC production technology is decisive advantages of HF resonator, and it has the thin layer thickness (" surface micromachined ") of MEMS device.
The piezoresistance reading device also ability of the doping from optimize silicon benefits, and is used for the optimization of device, and ion injects and the trap diffusion because thin device layer is suitable for.Even capacitor element also benefits from the doping that electrode has optimization, to make the dead resistance minimum by the doping of injecting.
For the good Q factor that obtains enough low decay (as, greater than 10000), for many HF resonators, vacuum should be less than 1mbar.
For the LF resonator, the inventor observes following phenomenon.
Because resonant frequency F
Res=1/2 π * √ (k/m) for the LF resonator, has little quality m (1*10
-10Kg) resonating device is about needs 1 very low spring constant k.If the thin thickness (between 1 and 2 μ m) of layer, then the quality of resonator can be increased, but this also will cause bigger surface area.This makes that production is very difficult, because the large tracts of land that combines with low spring constant is very sensitive to capillary force, stiction is a subject matter.Therefore, several times or 10 times or more times of thick thickness of detector will significantly increase quality, and k also can be bigger, therefore cause more feasible LF resonator.Even the resonant frequency accelerometer that is lower than 100KHz mostly also is made into thickness usually and surpasses 50nm.
The equation that moves is m*a+b*v+k*x=F
Ext
Wherein
The m=quality,
The 2nd rank time-derivative of a=displacement or acceleration,
The 1st rank time-derivative of v=displacement or speed,
The b=damped coefficient,
The k=spring constant,
The x=displacement,
F
Ext=external force, the electric power of Tathagata self-electrode
If m and k are very low, the item that then has quality (kinetic energy) and spring constant (spring potential energy) is controlled by damping easily.At 100 times of lower parts of frequency, vacuum requirement can rise to 100 times higher.For low-frequency resonator, recommendation be to compare with its HF homologue to have 10 to 100 times of bigger quality, therefore, thickness of detector should have some 10 to 100 times bigger.Compare with the resonator at bulk-mode (stretching-compression) type of HF, device itself may be selected to be beam mode (bending-mode)/flexing pattern (flex-mode) resonator.
LF is difficult to adopt identical layer thickness to make with the HF resonator together.By the present invention, LF and HF resonator are bonded on the chip.
This method also is particularly suitable for CMOS or BiCmos integrated.Two devices can be shared same vacuum chamber, but this is optional.
This LF device is realized in handling wafer substrates, for example passes through deep reactive ion etch, if required, and after substrate thinning is arrived required thickness, as 50 μ m, 100 μ m or bigger.Utilization is handled wafer contact hole or other known mode over against the back of the body (front-to-back), can realize electrically contacting to bonding welding pad or integrated circuit.In more detail, for example WO2004/071943 has required a kind of structure, and the top contact of wherein passing the insulating barrier in the SOI substrate is used for suspension body MEMS device, discharges from handling the chip back surface substrate.The present invention can utilize this structure aspect following: make thin soi layer on another MEMS top, form the single chip architecture of uniqueness of two MEMS with different layers thickness of two silicon layers that are arranged in the SOI substrate.Can with its be integrated in the same substrate such as the electronic device monolithic of CMOS.
HF MEMS resonator and the single chip integrated application that combines of LF resonator can be used as the replacement of two or more timing devices such as quartz crystal or ceramic crystal.
The another kind of application is that two (or more a plurality of) MEMS resonators and pierce circuit chip are packaged together, and wherein the pierce circuit chip will comprise the pierce circuit that keeps the resonator vibration.This is the chip of clock for a long time of single encapsulation.For many application, need several clock signals, as be distributed in various clock signals on the PC mainboard, perhaps be used to have the combination of clock of the digital signal processor of wireless or wire communication function, wherein WLAN, FM radio or the USB of communication function as having GSM.The present invention has imagined these application.
The another kind of application is that pierce circuit and MEMS resonator are integrated in the same chip, and we are particularly suitable for this at present technology, but the MEMS resonator also can be integrated by other technological process.Integrated advantage will be the wafer scale fine setting, be used for realizing and the suitable precision of quartz oscillator (XO, 50ppm frequency accuracy).
The favourable combination of two MEMS devices is to be arranged in the XY induction acceleration meter that thick body is handled wafer substrates, and the vertical sensitive acceleration meter that is arranged in thin soi layer, and thin soi layer is because its thin spring and very suitable.This technological process is convenient to make the vertical displacement that the vertical electrode at top of sensor measures the Z accelerometer that moves both vertically.
In the third aspect, the present invention relates to a kind of device, suppress breach (notch), phase shifter, lc circuit, semiconductor devices as bandpass filter, harmonic wave, it comprises according to microcavity of the present invention, microcavity perhaps formed according to the present invention.
Adopt on the chip of the present invention integratedly, do not have because the loss of signal that chip extremely chip connects.Therefore, this causes power consumption still less.
In fourth aspect, the present invention relates to a kind of RF circuit, comprise according to microcavity of the present invention, perhaps the microcavity of the method according to this invention formation.
Adopt on the chip of the present invention integratedly, do not have because the loss of signal that chip extremely chip connects.Therefore, this causes power consumption still less.
Further illustrate the present invention by following accompanying drawing and example, but do not wish that accompanying drawing and example limit the scope of the invention.It will be apparent to one skilled in the art that various embodiment can be combined, and can imagine by the present invention.
Description of drawings
Fig. 1 illustrates the beginning material.
Fig. 2-4 illustrates the first step that limits the MEMS structure.
Fig. 5 illustrates further processing.
Fig. 6-7 illustrates the top surface of the MEMS that will separate.
Fig. 8 illustrates the remainder that CMOS handles.
Fig. 9 illustrates the grinding to silicon substrate.
Figure 10 illustrates the etching of groove.
Figure 11 illustrates the release of MEMS device.
Figure 12 illustrates the sealing of MEMS device.
Figure 13 illustrates the release of the first and second MEMS devices.
Figure 14 illustrates the sealing of the first and second MEMS devices.
The specific embodiment
Fig. 1 illustrates the beginning material as standard thin film SOI substrate, and wherein the SOI substrate comprises monocrystalline substrate (100), buried silicon oxide layer (BOX, common 1.5 μ m are thick) (101), and thin single crystal silicon layer (SOI, common 1.5 μ m are thick) (102).This substrate acquiescence is used for high-pressure process, as ABCD3 and ABCD9.Soi layer also is desirable for making good MEMS structure (for example resonator).Compare with for example using polysilicon (for example, analog device) time, its material parameter control is much better.
Should be noted that and also may use much thick soi layer (10-20 μ m).By this way, may use any standard CMOS process, and the further technology of similar ABCD for example.Simultaneously, some MEMS device also will benefit from the quality that increases, and wherein the quality of Zeng Jiaing is to follow thicker layer to take place.
Fig. 2-4: the first step is to limit the MEMS structure.This is to be undertaken by following operation: deposition light erosion resistant agent layer (103) mask is provided and forms the image of described mask, and around this etch structures groove, it will be released in technology subsequently.Groove (114) etching is down to BOX, thereby isolates MEMS structure (115) fully, and except some anchor points, obviously, these anchor points are arranged in third dimension degree (not shown).Should be noted that in some cases this etching is combined with obtainable trench isolations step.
Fig. 5: in order can further to handle, the MEMS device is discharged and very fragile, groove is filled with silica (111), as according to for example fill the similar mode of STI.
The top surface of Fig. 6,7a:MEMS also needs to separate.This realizes by using pattern field to isolate (STI or LOCOS) (121), adopts the polysilicon layer (105) of CMOS grid subsequently in this example, covers whole M EMS structure.Note, between polysilicon and active area, also exist gate oxide usually.It should be noted that, further, on on the edge top of MEMS structure, the essential qualification of overlapping that exceeds the cap layer (polysilicon) of oxide (STI or LOCOS), so that during release etch (Figure 11), there are some gate oxides to stay on the side, thereby make polysilicon still cover cavity fully around the MEMS device.Fig. 7 b illustrates a kind of alternative form, but wherein cap layer horizontal expansion, for example, if this layer provides on LOCOS layer (121).Its a kind of advantage is, in release etch, gate oxide does not need etched, if especially some LOCOS etching place of staying the chamber.Like this, prevented relevant complicated of capillary force in the gate oxide for example.
These steps in fact have been the parts that standard CMOS is handled: in identical step, also provide normal to isolate and gate patternization.
Alternatively, also can use first inter-metal dielectric (IMD) layer to replace LOCOS or STI, and use metal to replace grid polycrystalline silicon as cap layer, especially for thin (1.5 μ m) SOI thickness as separate layer.This will cause significantly thicker MEMS device, and may cause the more spaces on the MEMS device in the cavity.This may be a kind of advantage, for example, when cap because when for example tension force is crooked, especially in bigger structure example as greater than 100 μ m diameters.
The remainder that CMOS handles is summarised among Fig. 8.Wherein form various separation layers (106), for example dielectric layer.Similarly, form various metal levels (107).Further, form final sealant usually, for example the silicon nitride (not shown).
Fig. 9: after standard is finished dealing with, grind the thickness that silicon substrate (100) is decreased to the 50-400 μ m order of magnitude (this thickness for example depend on still can mechanical treatment minimum thickness).Thereafter, deposition photoresist material (108) and being patterned.Thereafter, etching resist.
Figure 10: from the back side of substrate, below the MEMS device, upwards to the BOX layer, pass silicon and etch groove (124) always,
Figure 11: discharge the MEMS device by removing oxide then, thereby form cavity (134), for example by using wet method or steam HF etching.Because the ditch trench etch downwards until BOX, adopts oxide to fill, and the covering of oxide piece, so can in an etching step, discharge.Those skilled in the art will recognize that the key point that only has in this step is the adjusting of accurate etching period, with the overlapping of the design of cap (equally referring to Fig. 6,7 commentary).
Figure 12: in order to seal the MEMS device, be enough at the backside deposition gas-tight seal layer (190) of wafer, metal level for example.Especially the aluminium of sputtering sedimentation has bad step covering: the hole will be from the top closure, in the inner not significant deposition of groove.After the sealing, because the sealing of whole chamber tegillum, the vacuum level in the chamber will be near the pressure between the sputtered aluminum depositional stage, and this layer has all (seen) front-end processing temperature step (usually greater than 1000 ℃) of seeing, this means to expect the very little degassing.
Claims (7)
1. method that in CMOS technology, forms one or more microcavity (134), each microcavity comprises MEMS (MEMS), and this CMOS technology further forms at least one semiconductor element, and has common processing step, and this method comprises:
-substrate (100) is provided, this substrate has the front and the back side that is used to hold described at least one semiconductor element,
-in the positive dielectric layer deposition (101) of substrate (100),
-go up deposition silicon layer (102) at described dielectric layer (101),
-in described silicon layer (102), form one group of one or more positive release opening (114,115), the group that described release opening is selected from groove, passage, hole and constitutes,
-in described silicon layer (102), form dielectric medium structure (121), and adopt dielectric substance to fill positive one group one or more release opening (114,115), make that microcavity (134) comprises dielectric substance before discharging,
-adopt metal or polysilicon layer (105) that dielectric medium structure (121) is added cap, dielectric medium structure (121) will become microcavity (134),
-after finishing, the formation of described at least one semiconductor element discharges microcavity (134), and wherein discharge microcavity and comprise
-by following steps, provide one group of one or more back side at the described back side of passing substrate (100) to discharge (124), the group that described release opening is selected from groove, passage, hole and constitutes,
-below the MEMS device, be upward through always and arrive dielectric layer (101), pass the described back side of substrate (100), described one group of one or more back side release opening (124) of etching, wherein said etching is selected from wet method or steam HF etching,
-removing dielectric substance in one group of one or more positive release opening (114,115) described in the described silicon layer (102), and in described silicon layer (102), remove dielectric medium structure, thus discharge microcavity (134).
2. method according to claim 1 wherein forms two or more microcavitys (134), comprises at least one first microcavity as thick microcavity, as at least one second microcavity of thin microcavity.
3. method according to claim 1 further may further comprise the steps:
-dense the seal of deposition gas (109a) on the back side of substrate (100) is with the microcavity (134) of sealing by etching formation.
4. method according to claim 1 wherein before etching, is ground the predetermined thickness that is decreased between 50 to the 400 μ m with the back side of substrate (100) at its place, back side.
5. method according to claim 1, the front that further is included in substrate (100) forms separate layer,
Wherein, with first inter-metal dielectric (IMD) layer or LOCOS or STI as separate layer, and wherein metal or grid polycrystalline silicon as cap layer.
6. method according to claim 1, the front that further is included in substrate (100) provides passivation layer.
7. method that forms the RF circuit, comprise that method according to claim 1 forms one or more microcavity (134) in CMOS technology, each microcavity comprises MEMS (MEMS), this CMOS technology further forms at least one semiconductor element, and has common processing step.
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