CN101872792A - Vertical thermal isolation structure of hybrid-type uncooled focal plane detector and manufacturing process thereof - Google Patents

Vertical thermal isolation structure of hybrid-type uncooled focal plane detector and manufacturing process thereof Download PDF

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Publication number
CN101872792A
CN101872792A CN200910094389A CN200910094389A CN101872792A CN 101872792 A CN101872792 A CN 101872792A CN 200910094389 A CN200910094389 A CN 200910094389A CN 200910094389 A CN200910094389 A CN 200910094389A CN 101872792 A CN101872792 A CN 101872792A
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chip
electrode
roic
detector
reading circuit
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CN200910094389A
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CN101872792B (en
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杨瑞宇
刘黎明
莫镜辉
杨培志
苏雷
韩毅
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Kunming Institute of Physics
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Kunming Institute of Physics
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract

The invention relates to a vertical thermal isolation structure of a hybrid-type uncooled focal plane detector and a manufacturing process thereof. The vertical thermal isolation structure is characterized in that organic convex plates for thermal isolation and electrical connection are respectively arranged on the gold electrode of a detector chip and the gold electrode of a readout circuit chip, climbing gold electrodes are arranged on the organic convex plates, chromium gold electrodes are arranged on the climbing gold electrodes, and indium columns for inverse coupling of the detector chip and the readout circuit chip are arranged on the climbing gold electrodes. The manufacturing process comprises preparation of the organic convex plates, growth of the climbing gold electrodes, preparation of the chromium gold electrodes, evaporation of the indium columns, high-temperature treatment and shrinkage, inverse coupling and integration of the indium columns and the like. The invention can greatly increase the response rate and detection rate of the uncooled focal plane detector, and significantly improve performance indexes of the uncooled focal plane detector.

Description

A kind of vertical heat insulation structure and manufacturing process of hybrid-type uncooled fpa detector
Technical field
The present invention relates to a kind of hybrid-type non-refrigerated infrared focal plane probe, particularly relate to the vertical hot isolation technology of a kind of hybrid-type non-refrigerated infrared focal plane probe chip and its reading circuit (ROIC) chip.
Background technology
Uncooled fpa detector (UFPA) can be divided into two kinds of one chip and hybrid-types.The one chip uncooled fpa detector adopts the technology of directly making responsive element array on reading circuit.The hybrid-type uncooled fpa detector then adopts responsive element array of detector and reading circuit to make respectively, then with the two technology that forms by indium (In) post flip-chip interconnection.At present, the interconnection technique between responsive unit of the detector of hybrid-type uncooled fpa detector and the reading circuit adopts softer metals indium (In) directly interconnected.Because the thermal conductance of indium (under the room temperature, reaches 0.816Wcm greatly usually -2K -1), adding the material barium strontium titanate (BST) of making the responsive unit of detector has bigger thermal response time constant (usually 10 -2The S magnitude), the infrared energy that causes the responsive unit of detector the to absorb electrical signal energy that also do not have enough time fully to be converted into is just spread heat energy by the indium post of high thermal conductance to reading circuit, make the responsive unit of detector can not get sufficient heat absorption.Bigger thermal diffusion between the responsive first material of detector and its reading circuit has reduced the responsiveness and the sensitivity of detector, causes the performance of hybrid-type uncooled fpa detector and application to be restricted.
Summary of the invention
Defective at prior art exists the invention provides the vertical hot isolation technology of a kind of uncooled fpa detector, by reducing the heat conduction between detector chip and the readout circuit chip, promotes the responsiveness and the sensitivity of detector.
Adopt the organic material top layer of a low thermal conductance, the form by the electrode climbing increases its heat conduction path and reduces thermal conductance.Utilize the method for photoetching, adopt photo-sensistive polyimide, made the machine platform that has of gridding by the development lift-off technology, this have effect that machine platform reaches mainly by the size in cross section, highly, and the logical ability of climbing of electrode determines.The size in cross section and highly determined its thermal conductance size, and the connectedness of electrode has determined what of blind element number of detector chip, thus determined the resolution of detector.
Vertical heat insulation structure of hybrid-type non-refrigerated infrared focal plane probe provided by the invention, it is characterized in that: on the gold electrode of the gold electrode of detector chip and readout circuit chip, adopt respectively to have that heat is isolated and organic boss of electrode interconnect function, design has the climbing gold electrode on organic boss, on the climbing gold electrode cr-au electrode is arranged, the indium post of interconnected detector chip of upside-down mounting and readout circuit chip is arranged on the cr-au electrode.
Vertical heat insulation structure of hybrid-type non-refrigerated infrared focal plane probe provided by the invention, realize by following concrete processing step:
1. the preparation of the gold electrode of detector chip is cleaned;
2. the patterned photoetching of the organic boss of detector chip is cleaned;
3. the growth of organic boss on the detector chip;
4. the peeling off of photoresist on the detector chip cleaned;
5. evaporation and the climbing of the gold electrode on the detector chip on organic boss;
On the detector chip the second time cr-au electrode graphical photoetching;
7. the evaporation of cr-au electrode on the detector chip;
8. the evaporation of indium film on organic boss on the detector chip;
9. the high-temperature process of detector chip, indium post growth and shrinking;
10. the cleaning of reading circuit (ROIC) chip;
11. the patterned photoetching first time of gold electrode on reading circuit (ROIC) chip is cleaned;
12. level (aluminium electrode) the gold evaporation electrode that powers on reading circuit (ROIC) chip cleans;
13. the patterned photoetching of the organic boss of chip on reading circuit (ROIC) chip is cleaned;
14. the growth of the organic boss on reading circuit (ROIC) chip;
15. peeling off of reading circuit (ROIC) photoresist cleaned;
16. evaporation and the climbing of gold electrode on organic boss on reading circuit (ROIC) chip;
17. on reading circuit (ROIC) chip the second time cr-au electrode graphical photoetching;
18. the evaporation of the cr-au electrode on reading circuit (ROIC) chip;
19. the evaporation of indium film on organic boss on reading circuit (ROIC) chip;
20. the high-temperature process of reading circuit (ROIC) chip, growth of indium post and contraction;
21. detector chip and reading circuit (ROIC) chip is interconnected integrated by the upside-down mounting of indium post.
Application of the present invention proves, adopts the vertical hot isolation technology of organic boss, effectively reduces the thermal diffusion between detector chip and reading circuit (ROIC) chip, and the responsiveness of hybrid-type uncooled fpa detector and sensitivity all are significantly improved.
Description of drawings
Fig. 1 is the growth schematic diagram of organic boss on detector chip and readout circuit chip;
Fig. 2 is the gold electrode schematic diagram of climbing on organic boss, grow;
Fig. 3 is the evaporation schematic diagram of cr-au electrode on the climbing gold electrode;
Fig. 4 is the evaporation schematic diagram of indium post;
Fig. 5 after heat treatment shrinks schematic diagram for the indium post of evaporation;
Fig. 6 is the schematic diagram of the indium post upside-down mounting on detector chip and the ROIC chip after interconnected.
Among the figure, 1. detector chip; 2. reading circuit (ROIC) chip; 3. gold electrode; 4. organic boss; 5. responsive element array; 6. climbing gold electrode; 7. cr-au electrode; 8. indium post.
Embodiment
Below in conjunction with accompanying drawing, by embodiment the present invention is described in further details, but protection scope of the present invention is not limited to the following examples.
Extremely shown in Figure 6 as Fig. 1, in structural design based on the hybrid-type uncooled fpa detector of 1 60 * 120 array scales of barium strontium titanate (BST) material, after having adopted the vertical heat insulation structure based on organic boss provided by the present invention, between detector chip and reading circuit (ROIC) chip, increase the boss 4 of the organic material preparation of two-layer low thermal conductance, and by replace the direct interconnect architecture of indium post of the prior art based on the indium post interconnection technique of organic boss 4.
Realize that process implementing of the present invention is for example down:
1. the preparation of the gold electrode of detector chip is cleaned;
2. the patterned photoetching of the organic boss of detector chip is cleaned;
3. the growth of organic boss on the detector chip;
4. the peeling off of photoresist on the detector chip cleaned;
5. evaporation and the climbing of the gold electrode on the detector chip on organic boss;
On the detector chip the second time cr-au electrode graphical photoetching;
7. the evaporation of cr-au electrode on the detector chip;
8. the evaporation of indium film on organic boss on the detector chip;
9. the high-temperature process of 100 ℃~180 ℃ of detector chips, indium post growth and shrinking;
10. the cleaning of reading circuit (ROIC) chip;
11. the patterned photoetching first time of gold electrode on reading circuit (ROIC) chip is cleaned;
12. level (aluminium electrode) the gold evaporation electrode that powers on reading circuit (ROIC) chip cleans;
13. the patterned photoetching of the organic boss of chip on reading circuit (ROIC) chip is cleaned;
14. the growth of the organic boss on reading circuit (ROIC) chip;
15. peeling off of reading circuit (ROIC) photoresist cleaned;
16. evaporation and the climbing of gold electrode on organic boss on reading circuit (ROIC) chip;
17. on reading circuit (ROIC) chip the second time cr-au electrode graphical photoetching;
18. the evaporation of the cr-au electrode on reading circuit (ROIC) chip;
19. the evaporation of indium film on organic boss on reading circuit (ROIC) chip;
20. the high-temperature process that reading circuit (ROIC) chip is 100 ℃~180 ℃, growth of indium post and contraction;
21. detector chip and reading circuit (ROIC) chip is interconnected integrated by the upside-down mounting of indium post.
Fig. 1 represents the preparation of organic boss 4, Fig. 2 represents the growth of climbing gold electrode 6 on organic boss 4, Fig. 3 represent to climb preparation of cr-au electrode 7 on the gold electrode 6, Fig. 4 represents the evaporation of indium post 8, Fig. 5 represents the situation of the indium post 8 of evaporation through 100 ℃~180 ℃ high-temperature process after-contraction, and Fig. 6 is the situation that detector chip and ROIC chip pass through the interconnected integrated complete detector of indium post upside-down mounting.
By taking said structure and technology, significantly reduced the heat conduction of detector chip and reading circuit (ROIC) chip, thereby made detector have sufficient thermal response and high sensitivity, its voltage response rate is greater than 5 * 10 5V/W -1, detectivity is greater than 5 * 10 8CmHz 1/2W -1

Claims (2)

1. vertical heat insulation structure of a hybrid-type non-refrigerated infrared focal plane probe, it is characterized in that: on the gold electrode (3) of the gold electrode (3) of detector chip and readout circuit chip, adopt respectively to have that heat is isolated and organic boss (4) of electrode interconnect function, design has climbing gold electrode (6) on organic boss, on the climbing gold electrode cr-au electrode (7) is arranged, the indium post (8) of interconnected detector chip of upside-down mounting and readout circuit chip is arranged on the cr-au electrode.
2. technology of making the described vertical heat insulation structure of claim 1 is characterized in that: carry out according to the following steps:
A. the preparation of the gold electrode of detector chip is cleaned;
B. the patterned photoetching of the organic boss of detector chip is cleaned;
C. the growth of organic boss on the detector chip;
D. the peeling off of photoresist on the detector chip cleaned;
E. evaporation and the climbing of the gold electrode on the detector chip on organic boss;
F. on the detector chip the second time cr-au electrode graphical photoetching;
G. the evaporation of cr-au electrode on the detector chip;
H. the evaporation of indium film on organic boss on the detector chip;
I. the high-temperature process of detector chip, indium post growth and shrinking;
J. the cleaning of reading circuit (ROIC) chip;
K. the patterned photoetching first time of gold electrode on reading circuit (ROIC) chip is cleaned;
L. level (aluminium electrode) the gold evaporation electrode that powers on reading circuit (ROIC) chip cleans;
M. the patterned photoetching of the organic boss of chip on reading circuit (ROIC) chip is cleaned;
N. the growth of the organic boss on reading circuit (ROIC) chip;
O. peeling off of reading circuit (ROIC) photoresist cleaned;
P. evaporation and the climbing of gold electrode on organic boss on reading circuit (ROIC) chip;
Q. on reading circuit (ROIC) chip the second time cr-au electrode graphical photoetching;
R. the evaporation of the cr-au electrode on reading circuit (ROIC) chip;
S. the evaporation of indium film on organic boss on reading circuit (ROIC) chip;
T. the high-temperature process of reading circuit (ROIC) chip, indium post growth and shrinking;
U. detector chip and reading circuit (ROIC) chip is interconnected integrated by the upside-down mounting of indium post.
CN200910094389XA 2009-04-23 2009-04-23 Vertical thermal isolation structure of hybrid-type uncooled focal plane detector and manufacturing process thereof Expired - Fee Related CN101872792B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102437166A (en) * 2011-10-09 2012-05-02 中国科学院苏州纳米技术与纳米仿生研究所 Manufacturing method of non-refrigeration infrared detection system pixel array
CN105070786A (en) * 2015-07-28 2015-11-18 昆明物理研究所 High temperature oxidation resistant lead-out electrode of reading circuit and preparation method of electrode
CN105140337A (en) * 2015-07-28 2015-12-09 昆明物理研究所 Cold pressure welding flip interconnection method for photoelectric sensor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1937190A (en) * 2006-10-13 2007-03-28 中国科学院上海技术物理研究所 Micromelting return reinforcing method for infrared focal plane array device mixed-interconnecting indium column

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102437166A (en) * 2011-10-09 2012-05-02 中国科学院苏州纳米技术与纳米仿生研究所 Manufacturing method of non-refrigeration infrared detection system pixel array
CN102437166B (en) * 2011-10-09 2013-05-01 中国科学院苏州纳米技术与纳米仿生研究所 Manufacturing method of non-refrigeration infrared detection system pixel array
CN105070786A (en) * 2015-07-28 2015-11-18 昆明物理研究所 High temperature oxidation resistant lead-out electrode of reading circuit and preparation method of electrode
CN105140337A (en) * 2015-07-28 2015-12-09 昆明物理研究所 Cold pressure welding flip interconnection method for photoelectric sensor
CN105140337B (en) * 2015-07-28 2017-03-08 昆明物理研究所 A kind of photoelectric sensor cold welding flip-chip interconnection method

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