CN101872773A - Thin-film transistor array substrate, display and manufacturing method thereof - Google Patents
Thin-film transistor array substrate, display and manufacturing method thereof Download PDFInfo
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- CN101872773A CN101872773A CN 201010212875 CN201010212875A CN101872773A CN 101872773 A CN101872773 A CN 101872773A CN 201010212875 CN201010212875 CN 201010212875 CN 201010212875 A CN201010212875 A CN 201010212875A CN 101872773 A CN101872773 A CN 101872773A
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Abstract
The invention provides a thin-film transistor array substrate, a display and a manufacturing method thereof. The TFT array substrate comprises at least two splicing regions. In a TFT pattern in each splicing region, a drain electrode and a grid metal layer both form an overlapping region. In the TFT pattern in at least one splicing region, the drain electrode extends from the first boundary of the grid metal layer to the outside of a second boundary, opposite to the first boundary. The drain electrodes comprise the overlapping regions and redundance regions, wherein the overlapping regions are formed by the drain electrodes and the grid metal layers, and the redundance regions extend to the outsides of the second boundaries of the grid metal layers; and the difference value of the area of the overlapping region in each splicing region is smaller than a threshold value. By changing the shapes of the patterns of the drain electrodes in the TFT patterns in the splicing regions, the condition that the difference of the area of the overlapping region formed by the drain electrode and the grid metal layer in each splicing region is not large is ensured, thereby attenuating the difference of the display brightness of each splicing region and reducing the generation of the exposure Kamla phenomenon.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of thin-film transistor array base-plate, display and manufacture method thereof.
Background technology
Informationized society more and more needs frivolous portable display device, and the product of comparative maturity is TFT (Thin Film Transistor, a thin-film transistor) LCD at present.
The TFT LCD mainly is to be made of tft array substrate, subtend color membrane substrates and the liquid crystal layer that is clipped in the middle of the two substrates.Wherein, tft array substrate mainly comprises gate metal layer, gate insulation layer, semiconductor layer, source-drain electrode metal level, dielectric film protective layer and the transparent pixels layer etc. of glass substrate and stacked setting on glass substrate.The manufacture process of tft array substrate is by multiexposure, multiple exposure, development and etching, the pattern on the mask is gone on the substrate, thereby formed the pattern of various elements.
In order to satisfy the demand of big display area, the size of TFT panel of LCD is increasing, makes the manufacturing process of tft array substrate also complicated all the more.In order to increase the size of tft array substrate, the size of mask also needs to increase thereupon, but because exposure machine is to the qualification of mask size, and there be difficulty, too high, the daily problems such as using inconvenience of depositing of cost made in the large scale mask, make when making tft array substrate, large-sized array base palte need be divided into several regions, make each regional corresponding mask version respectively, expose respectively with these masks during fabrication, finally piece together large-sized tft array substrate.
Yet, the inventor finds in research process, after the tft array substrate that adopts said method to make forms the TFT LCD, when energising work, the phenomenon that there is notable difference in display brightness often appears in each pattern splicing regions, this species diversity is called the exposure nurse and draws phenomenon owing to the amalgamation exposure produces.
Summary of the invention
The embodiment of the invention provides a kind of thin-film transistor array base-plate, display and manufacture method thereof, can weaken the display brightness difference of each splicing regions.
In order to solve the problems of the technologies described above, the technical scheme of the embodiment of the invention is as follows:
A kind of thin-film transistor array base-plate, comprise at least two splicing regions, in the thin-film transistor TFT pattern in each splicing regions, drain electrode all forms the overlapping region with gate metal layer, in the TFT pattern at least one splicing regions, drain electrode extends to the outside with right second border of described first borderline phase, overlapping region that described drain electrode comprises and described gate metal layer forms and the capacity area that extends to outside, described gate metal layer second border from first border of gate metal layer; The area difference of the overlapping region in each splicing regions is less than threshold value.
Further, described capacity area is at the splicing exposure aligning error amount of the length on the outside bearing of trend in described second border more than or equal to exposure machine.
Further, the described overlapping region area in each splicing regions equates.
Further, the figure that described overlapping region and described capacity area surrounded is a rectangle.
A kind of Thin Film Transistor-LCD, comprise thin-film transistor array base-plate, described thin-film transistor array base-plate comprises at least two splicing regions, in the thin-film transistor TFT pattern in each splicing regions, drain electrode all forms the overlapping region with gate metal layer, in the TFT pattern at least one splicing regions, drain electrode extends to the outside with right second border of described first borderline phase, overlapping region that described drain electrode comprises and described gate metal layer forms and the capacity area that extends to outside, described gate metal layer second border from first border of gate metal layer; The area difference of the overlapping region in each splicing regions is less than threshold value.
Further, described capacity area is at the splicing exposure aligning error amount of the length on the outside bearing of trend in described second border more than or equal to exposure machine.
Further, the described overlapping region area in each splicing regions equates.
Further, the figure that described overlapping region and described capacity area surrounded is a rectangle.
A kind of manufacture method of thin-film transistor array base-plate comprises:
Form the first stacked function film layer at least one splicing regions on glass substrate, this first function film layer comprises gate metal layer;
Formation source, drain electrode above the described first function film layer, to form the TFT pattern, wherein, in the TFT pattern in the described splicing regions, drain electrode extends to the outside with right second border of described first borderline phase, overlapping region that described drain electrode comprises and described gate metal layer forms and the capacity area that extends to outside, described gate metal layer second border from first border of gate metal layer; The area difference of the overlapping region that drain electrode and gate metal layer form in each splicing regions is less than threshold value;
Above the TFT pattern that forms, form the second function film layer, obtain thin-film transistor array base-plate.
Further, described capacity area is at the splicing exposure aligning error amount of the length on the outside bearing of trend in described second border more than or equal to exposure machine.
A kind of manufacture method of Thin Film Transistor-LCD comprises:
Form the first stacked function film layer at least one splicing regions on glass substrate, this first function film layer comprises gate metal layer;
Formation source, drain electrode above the described first function film layer, to form the TFT pattern, wherein, in the TFT pattern in the described splicing regions, drain electrode extends to the outside with right second border of described first borderline phase, overlapping region that described drain electrode comprises and described gate metal layer forms and the capacity area that extends to outside, described gate metal layer second border from first border of gate metal layer; The area difference of the overlapping region that drain electrode and gate metal layer form in each splicing regions is less than threshold value;
Above the TFT pattern that forms, form the second function film layer, obtain thin-film transistor array base-plate;
Described thin-film transistor array base-plate and established subtend color membrane substrates are fitted, enter successive process, form Thin Film Transistor-LCD.
The embodiment of the invention is by changing the shape of drain pattern in the interior TFT pattern of splicing regions, even make when there is certain error in exposure machine to the set positions between mask on the stitching direction of pattern, can guarantee that also drain electrode is more or less the same with the overlapping region area that gate metal layer forms in each splicing regions, thereby weakened the difference of the display brightness of TFT pattern correspondence in each splicing regions, reduced the generation that the nurse that exposes draws phenomenon.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 a-b is the planar structure schematic diagram that forms the TFT pattern in the prior art;
Fig. 1 c is the planar structure schematic diagram of the large scale TFT pattern that is spliced to form in the prior art;
Fig. 2 is the planar structure schematic diagram of the TFT pattern in two splicing regions among Fig. 1 c;
Fig. 3 is a parasitic capacitance schematic equivalent circuit in the TFT structure;
Fig. 4 is the planar structure schematic diagram of a TFT pattern in a kind of tft array substrate of the embodiment of the invention;
Fig. 5 is the planar structure schematic diagram of the interior TFT pattern of two splicing regions in a kind of tft array substrate of the embodiment of the invention;
Fig. 6 is the planar structure schematic diagram of the interior tft array pattern of two splicing regions in the embodiment of the invention;
Fig. 7 is the manufacture method flow chart of a kind of thin-film transistor array base-plate of the embodiment of the invention;
Fig. 8 is the manufacture method flow chart of a kind of TFT thin film transistor monitor of the embodiment of the invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Set forth a lot of details in the following description so that fully understand the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not been subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the invention is described in detail in detail; for ease of explanation; the schematic diagram of indication device structure can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
When using mask on substrate, to form the TFT pattern in the prior art, as shown in Figure 1a, after utilizing the gate mask plate to form the gate metal layer 11 of array arrangement, it is (clear for illustrating to form gate insulation layer and semiconductor layer again on each gate metal layer 11 successively, gate insulation layer and semiconductor layer do not illustrate in the drawings), shown in Fig. 1 b, utilize the source-drain electrode mask plate above each gate metal layer 11, to form source electrode 12, drain electrode 13 simultaneously then.When forming the large scale tft array substrate, need many group mask plates (comprising gate mask plate and source-drain electrode mask plate etc.) to form each zone map respectively, final each zone is spliced to form the large scale pattern, be patterned into example with two groups of mask plates, (clear shown in Fig. 1 c for illustrating, gate insulation layer and semiconductor layer do not illustrate in the drawings), utilizing first, behind the first grid metal level on the left of two gate mask plates form among the figure respectively and the second grid metal level on right side, utilize first source to leak mask plate and form the first source-drain electrode array pattern on the first grid metal level in left side in the drawings, utilize the second source-drain electrode mask plate to form the second source-drain electrode array pattern on the second grid metal level on right side in the drawings, thereby promptly can be spliced into large-sized tft array pattern after the both sides pattern all forms.
Yet, the tft array pattern that this is spliced to form is after final formation TFT LCD, during energising work, the phenomenon that display brightness there are differences often appears in each pattern splicing regions, the inventor is through discovering, it is by obvious different the causing of overlapping region area between the drain electrode in each splicing regions and the lower floor gate metal layer that there is the reason of notable difference in display brightness.
As shown in Figure 2, with a TFT pattern 20 utilizing the left side that the first source-drain electrode mask plate forms among Fig. 1 c with to utilize a TFT pattern 30 on the right side that the second source-drain electrode mask plate forms be example, describe.
Utilize in the TFT pattern 20 of first source-drain electrode mask formation, first drain electrode 21 forms first overlapping region 23 with the first grid metal level 22 of lower floor; Utilize second drain electrode 31 in the TFT pattern 30 that the second source-drain electrode mask forms, form second overlapping region 33 (for diagram is clear, gate insulation layer and semiconductor layer do not illustrate in the drawings) with the second grid metal level 32 of lower floor.
Structure and operation principle thereof according to tft array substrate, circuit diagram as shown in Figure 3 as can be known, when the grid voltage acute variation, the fluctuation of voltage can be by the voltage of Cgd capacitive effect to show electrode (drain electrode), make the magnitude of voltage of show electrode be greater than or less than correct magnitude of voltage, therefore be the bucking voltage that current electrode can be set in the drive integrated circult in the signal source, make the voltage difference of show electrode and current electrode can keep right value, and the bucking voltage that drive integrated circult provides is unique.So, if first overlapping region 23, when second overlapping region, 33 each self-corresponding Cgd electric capacity are identical, the identical bucking voltage that provides by drive integrated circult then, can be so that the magnitude of voltage of the show electrode of each Cgd electric capacity correspondence be identical, thereby two TFT patterns 20 among Fig. 2, the display brightness of 30 correspondences is identical, and then will be identical at the display brightness of the left and right sides pattern shown in Fig. 1 c, otherwise, if first overlapping region 23, second overlapping region, 33 each self-corresponding Cgd electric capacity difference, because the bucking voltage that drive integrated circult provides is identical, the magnitude of voltage of the show electrode of each Cgd electric capacity correspondence is still different, and then will cause two TFT patterns 20, the display brightness of 30 correspondences there are differences, and then the display brightness of left and right sides pattern there are differences among Fig. 1 c, when the area of first overlapping region 23 and second overlapping region 33 differed big, will there be comparatively evident difference in the display brightness between each corresponding region.
Can have a direct impact the capacitance of the corresponding parasitic capacitance in zone separately respectively based on the area in first overlapping region 23,33 liang of zones, second overlapping region, for the display brightness that guarantees TFT pattern in each splicing regions evenly, when making tft array substrate, first overlapping region 23 must equate as far as possible with the area of second overlapping region 33.
In the prior art, as shown in Figure 2, in the TFT of both sides pattern 20,30, drain 21,31 all on the direction that each self-corresponding gate metal layer 22,32 is extended (also being left and right directions) at first and second in Fig. 2, the border of first drain electrode 21 is positioned at the inside of first grid metal level 22, the border of second drain electrode 32 also is positioned at the inside of second grid metal level 32, and first and second overlapping region has occupied the zone near first, second gate metal layer 22,32 borders respectively.Yet, because there is certain splicing exposure aligning error in exposure machine, also be that exposure machine is when using different masks to form composed pattern on substrate, there is certain error in (also i.e. left and right directions among the figure) to the set positions between mask on the stitching direction of pattern, so when above-mentioned first drain electrode of formation 21 and second drain electrode 31 patterns, be easy to cause first, the area in two overlapping zones does not wait, as shown in Figure 2, when above-mentioned second drain electrode of formation 31 patterns, if an error displacement is moved on second source-drain electrode mask right side in figure, will cause the area of first overlapping region 23 and the area of second overlapping region 33 to have bigger difference, and then the display brightness that will produce TFT pattern in two splicing regions is obviously different, and the nurse that also promptly exposes draws phenomenon.
Based on this, the embodiment of the invention provides a kind of tft array substrate, display and manufacture method thereof, shape by drain pattern in the TFT pattern in the change splicing regions, even make when there is certain error in exposure machine to the set positions between mask on the stitching direction of pattern, can guarantee also in each splicing regions that the overlapping region area that the gate metal layer of drain electrode and lower floor forms is more or less the same, thereby weakened in the prior art difference of the display brightness of TFT pattern correspondence in each splicing regions, reduced the generation that the exposure nurse draws phenomenon.
The present invention is described in detail below by specific embodiment.
Referring to Fig. 4, be the planar structure schematic diagram of a TFT pattern in a kind of tft array substrate of the embodiment of the invention.
Tft array substrate can be included in gate metal layer, gate insulation layer, semiconductor layer, source, drain metal layer, dielectric film protective layer and the transparent pixels layer etc. of stacked setting on the glass substrate.In order to satisfy the requirement of big display area, when making the large scale tft array substrate, need to adopt many group masks to form the pattern of each splicing regions respectively, the pattern amalgamation of final each splicing regions back together forms large-sized tft array substrate, therefore, in this tft array substrate, can there be at least two splicing regions.Drain electrode all forms the overlapping region with gate metal layer in the TFT pattern in each splicing regions, and the area difference of overlapping region described in the TFT pattern of each splicing regions is less than threshold value.
Wherein, at least in a certain splicing regions structure of TFT pattern as shown in Figure 4, this figure is an example with any the TFT pattern in this splicing regions, and is clear in order to illustrate, function film layer between source, drain and gate metal level is not shown in the drawings, for example gate insulation layer, semiconductor layer.
In the TFT of present embodiment pattern, above the gate metal layer 41 that forms, utilize the source-drain electrode mask plate to form drain electrode 42 and source electrode 43 simultaneously.Drain electrode 42 is positioned at same plane substantially with source electrode 43, and is not overlapping, and all extends to the top of gate metal layer 41, and wherein, the forming process of gate metal layer 41 and structure thereof can be same as the prior art.
In this TFT pattern, draining 42 on the direction that gate metal layer 41 is extended, drain electrode 42 extends to the outside on second border 412 of gate metal layer 41 from first border 411 of gate metal layer 41, first border 411 is relative with second border 412, drain electrode 42 comprises overlapping region 421 that the gate metal layer 41 with the below forms and the capacity area 422 that extends to 412 outsides, second border.
In the present embodiment, source electrode 43 also can have and the 42 similar structures that drain, and source electrode 43 extends to the outside on first border 411 from second border 412, certainly, because source electrode 43 does not influence display brightness, this source electrode 43 also can adopt other pattern form, does not limit herein.
According to above structure, drain electrode 42 has been crossed over two borders of gate metal layer 41, and also extended capacity area 422 outside second border of gate metal layer 41 on the direction of extending to gate metal layer 41 in this splicing regions.This shows, when forming drain electrode, draining on the direction that gate metal layer is extended, even there is certain splicing exposure aligning error in exposure machine, for example the right side is offset an error amount in Fig. 4, because the existence of capacity area, can make splicing regions drain electrode and the overlapping region that forms of gate metal layer still across two borders of gate metal layer, make that the area of the interior overlapping region of this splicing regions is constant substantially, and with the overlapping region area difference of other splicing regions in threshold range, thereby the parasitic capacitance of overlapping region correspondence is roughly the same in each splicing regions, when the display work of follow-up formation, the difference of the display brightness of TFT pattern correspondence can be weakened in each splicing regions, has also reduced the generation that the nurse that exposes draws phenomenon.
In other embodiments, drain electrode in each splicing regions TFT pattern all can be adopted above-mentioned pattern or structure, and the area difference of the overlapping region that drain electrode and gate metal layer form in each splicing regions is less than threshold value, this threshold value can be according to the difference requirements of pattern splicing place display brightness on the tft array substrate is determined, for example, if require pattern splicing place display brightness unanimity, the overlapping region area that then can set in each splicing regions all equates.And, if make that the interior drain electrode of each splicing regions is identical with the overlapping region area that gate metal layer forms, can also further limit drain electrode, for example draining on the direction that gate metal layer is extended, the area of unit length all equates in overlapping region that drains in each splicing regions and the capacity area area surrounded.The concrete following examples of passing through describe.
As shown in Figure 5, be the planar structure schematic diagram of TFT pattern in two splicing regions in a kind of tft array substrate of the embodiment of the invention.
Tft array substrate comprises two splicing regions of A, B at least in the present embodiment, is that example describes (serve as that diagram is clear, gate insulation layer and semiconductor layer do not illustrate in the drawings) with two TFT patterns that lay respectively in two splicing regions.
In the present embodiment, the structural relation and the previous embodiment of the gate metal layer of TFT pattern and source electrode, drain electrode are similar in A, the B splicing regions.
When forming the TFT pattern of A splicing regions, at first utilize mask plate to form gate metal layer 51, utilize the source-drain electrode mask plate above gate metal layer 51, to form drain electrode 52 then, this drain electrode 52 extends to the outside on second border 512 relative with first border 511 from first border 511 of gate metal layer 51, drain electrode 52 comprises the overlapping region 521 that forms with gate metal layer 51, and the capacity area 522 that is positioned at 512 outsides, second border, 522 area surrounded in overlapping region 521 and capacity area are rectangle, therefore in drain electrode 52 on the direction that gate metal layer 51 is extended, the area of unit length is all identical in overlapping region 521 and capacity area 522 area surrounded.In this splicing regions, suppose that there is not error in exposure machine to the location of source-drain electrode mask plate, 52 the capacity area 522 of draining this moment is positioned at the outside on second border 512 fully.
When forming the TFT pattern in B splicing Ei zone, at first utilize mask plate to form the interior gate metal layer 61 of B splicing regions, utilize the source-drain electrode mask plate above gate metal layer 61, to form drain electrode 62 then, in this splicing regions, there is error in exposure machine to the location of source-drain electrode mask plate, make the right side (in figure arrow points) of source-drain electrode mask plate in Fig. 5 be offset an error amount, the drain electrode 62 that forms still extends to the outside on second border 612 relative with first border 611 from first border 611 of gate metal layer 61, but because the existence of offset error, capacity area 622 parts of this drain electrode 62 enter 612 inside, second border of gate metal layer 61, therefore drain and comprised part capacity area 622 in 62 overlapping regions 621 that form with gate metal layer 61,622 area surrounded in overlapping region 621 and capacity area are similarly rectangle, therefore draining 62 on the direction that gate metal layer 61 is extended, the area of unit length is all identical in overlapping region 621 and capacity area 622 area surrounded, therefore, even the source-drain electrode mask plate is offset an error amount, because the existence of capacity area 622, overlapping region 621 still can be across two borders of gate metal layer 61, and its area equates with the area of overlapping region 521.
When having splicing exposure aligning error for further assurance exposure machine, the area of overlapping region 621 is identical with the area of overlapping region 521, and capacity area 622 can be more than or equal to the splicing exposure aligning error amount of exposure machine in the length on the 612 outside bearing of trends of second border of gate metal layer 61.
Among the above embodiment with the drain electrode on the vertical direction of gate metal layer bearing of trend, the dual-side of the overlapping region of drain electrode all is positioned at the inside, border of gate metal layer, can also further on gate metal layer, set and hold surplus distance, make the overlapping region hold surplus distance being not less than this to gate metal layer in this minimum range perpendicular to the border on the bearing of trend perpendicular to the side on the bearing of trend, as shown in Figure 5, the coboundary of overlapping region is not less than the Rong Yu distance apart from the minimum range of the coboundary of gate metal layer.
Among the above embodiment, be that example describes all with a TFT pattern in a certain splicing regions in the tft array substrate, in actual generative process, when a plurality of splicing regions of utilizing many group masks to form respectively, can form a plurality of TFT patterns that are array distribution simultaneously, (for diagram is clear, gate insulation layer and semiconductor layer do not illustrate in the drawings) as shown in Figure 6.
Hence one can see that, when exposure machine when utilizing each mask to form the TFT pattern of above-mentioned splicing regions, draining on the direction that gate metal layer is extended, even there is certain splicing exposure aligning error in exposure machine, Fig. 5 for example, when utilizing mask plate to form the TFT pattern of right side splicing regions, even mask plate moves an error amount to the right, because drain electrode is gone up existence and its length of capacity area and is not less than splicing exposure aligning error amount, still can guarantee identical in the overlapping region of drain electrode and the gate metal layer formation of lower floor in the TFT pattern of right side splicing regions and the left side splicing regions, thereby the parasitic capacitance of each overlapping region correspondence is identical, when the display energising work of follow-up formation, make that the display brightness of TFT pattern correspondence is identical in each splicing regions, reduced the generation that the exposure nurse draws phenomenon.
The embodiment of the invention can also provide a kind of TFT LCD, this display can comprise the described tft array substrate of embodiment as described above, can also comprise the subtend color membrane substrates (being called the CF substrate again) of fitting mutually, repeat no more herein with this tft array substrate.
Below by specific embodiment the method that forms above-mentioned tft array substrate is described.
Referring to Fig. 7, be the manufacture method flow chart of a kind of thin-film transistor array base-plate of the embodiment of the invention.
This method can comprise:
Step 701 forms the first stacked function film layer at least one splicing regions on glass substrate, this first function film layer comprises gate metal layer.
This first function film can comprise gate metal layer, gate insulation layer, semiconductor layer etc., and forming process and prior art that each layer is concrete are similar, repeat no more herein.
Source, the drain pattern that forms in the splicing regions in this step is positioned at the top of the first function film layer, specifically above gate metal layer, utilize the source-drain electrode mask plate to form source, drain metal layer simultaneously, to form the TFT pattern, comprising steps such as the coating of photoresist, exposure, development, etchings, this forming process and prior art are similar, repeat no more herein.Also there are other thin layer, for example gate insulation layer, semiconductor layer etc. between source, drain metal layer and the gate metal layer.
Wherein, the drain electrode in this splicing regions extends to the outside with second border of first borderline phase from first border of gate metal layer, and this drain electrode comprises the overlapping region that forms with gate metal layer and extends to the capacity area of outside, gate metal layer second border.
The area difference of the overlapping region in each splicing regions in the TFT pattern is less than threshold value.This threshold value can for example, if require pattern splicing place display brightness unanimity, then can be set the interior overlapping region of each splicing regions area and equate according to the difference requirements of pattern splicing place display brightness on the tft array substrate is determined.
In order to make in drain electrode on the direction that gate metal layer is extended, when there is splicing exposure aligning error in exposure machine, drain electrode is all identical with the overlapping region area that the gate metal layer of lower floor forms in each splicing regions, can also be on the direction that gate metal layer is extended in drain electrode, make overlapping region and capacity area institute area surrounded in the TFT pattern in the splicing regions, the area of unit length equates.
Concrete can limit by the geometry of setting drain electrode, for example make drain electrode overlapping region, capacity area be rectangle, but also can make the capacity area at the splicing exposure aligning error amount of the length on the outside bearing of trend in second border of gate metal layer more than or equal to exposure machine by the designing mask version.
In this step, TFT pattern in this splicing regions and the TFT similar in the previous embodiment repeat no more herein.
Step 703 forms the second function film layer above the TFT pattern that forms, obtain thin-film transistor array base-plate.
Wherein, second function film can be thin layers such as dielectric film protective layer, transparent pixels layer.
Pass through said method, when exposure machine when utilizing mask to form the drain electrode of above-mentioned splicing regions respectively, draining on the direction that gate metal layer is extended, even there is certain splicing exposure aligning error in exposure machine, because the existence of capacity area and its length are not less than splicing exposure aligning error amount, can make in each splicing regions, drain electrode is identical with the overlapping region area that the gate metal layer of lower floor forms, thereby the parasitic capacitance of overlapping region correspondence is identical in each splicing regions, when the display energising work of follow-up formation, make that the display brightness of TFT pattern correspondence of each splicing regions is identical, reduced the generation that the exposure nurse draws phenomenon.
Referring to Fig. 8, be the manufacture method flow chart of a kind of TFT thin film transistor monitor of the embodiment of the invention.
This method can comprise:
Step 801 forms the first stacked function film layer at least one splicing regions on glass substrate, this first function film layer comprises gate metal layer.
Step 803 forms the second function film layer above the TFT pattern that forms, obtain tft array substrate.
Step 801～803 are similar with step 701～703 in the previous embodiment, repeat no more herein.
Step 804 is fitted tft array substrate and established subtend color membrane substrates, enters successive process, forms the TFT LCD.
Pass through said method, make in the TFT pattern in each splicing regions in the tft array substrate drain electrode identical with the overlapping region area of the gate metal layer formation of lower floor, thereby the parasitic capacitance of overlapping region correspondence is identical in each splicing regions, when the display energising work that forms, make that the display brightness of TFT pattern correspondence is identical in each splicing regions, reduced the generation that the exposure nurse draws phenomenon.
Above-described embodiment of the present invention does not constitute the qualification to protection range of the present invention.Any modification of being done within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within the claim protection range of the present invention.
Claims (11)
1. thin-film transistor array base-plate, it is characterized in that, comprise at least two splicing regions, in the thin-film transistor TFT pattern in each splicing regions, drain electrode all forms the overlapping region with gate metal layer, in the TFT pattern at least one splicing regions, drain electrode extends to the outside with right second border of described first borderline phase, overlapping region that described drain electrode comprises and described gate metal layer forms and the capacity area that extends to outside, described gate metal layer second border from first border of gate metal layer; The area difference of the overlapping region in each splicing regions is less than threshold value.
2. thin-film transistor array base-plate according to claim 1 is characterized in that, described capacity area is at the splicing exposure aligning error amount of the length on the outside bearing of trend in described second border more than or equal to exposure machine.
3. thin-film transistor array base-plate according to claim 1 is characterized in that, the described overlapping region area in each splicing regions equates.
4. according to any described thin-film transistor array base-plate in the claim 1 to 3, it is characterized in that the figure that described overlapping region and described capacity area surrounded is a rectangle.
5. Thin Film Transistor-LCD, comprise thin-film transistor array base-plate, it is characterized in that, described thin-film transistor array base-plate comprises at least two splicing regions, in the thin-film transistor TFT pattern in each splicing regions, drain electrode all forms the overlapping region with gate metal layer, in the TFT pattern at least one splicing regions, drain electrode extends to the outside with right second border of described first borderline phase, overlapping region that described drain electrode comprises and described gate metal layer forms and the capacity area that extends to outside, described gate metal layer second border from first border of gate metal layer; The area difference of the overlapping region in each splicing regions is less than threshold value.
6. Thin Film Transistor-LCD according to claim 5 is characterized in that, described capacity area is at the splicing exposure aligning error amount of the length on the outside bearing of trend in described second border more than or equal to exposure machine.
7. Thin Film Transistor-LCD according to claim 5 is characterized in that, the described overlapping region area in each splicing regions equates.
8. according to any described thin-film transistor array base-plate in the claim 5 to 7, it is characterized in that the figure that described overlapping region and described capacity area surrounded is a rectangle.
9. the manufacture method of a thin-film transistor array base-plate is characterized in that, comprising:
Form the first stacked function film layer at least one splicing regions on glass substrate, this first function film layer comprises gate metal layer;
Formation source, drain electrode above the described first function film layer, to form the TFT pattern, wherein, in the TFT pattern in the described splicing regions, drain electrode extends to the outside with right second border of described first borderline phase, overlapping region that described drain electrode comprises and described gate metal layer forms and the capacity area that extends to outside, described gate metal layer second border from first border of gate metal layer; The area difference of the overlapping region that drain electrode and gate metal layer form in each splicing regions is less than threshold value;
Above the TFT pattern that forms, form the second function film layer, obtain thin-film transistor array base-plate.
10. method according to claim 9 is characterized in that, described capacity area is at the splicing exposure aligning error amount of the length on the outside bearing of trend in described second border more than or equal to exposure machine.
11. the manufacture method of a Thin Film Transistor-LCD is characterized in that, comprising:
Form the first stacked function film layer at least one splicing regions on glass substrate, this first function film layer comprises gate metal layer;
Formation source, drain electrode above the described first function film layer, to form the TFT pattern, wherein, in the TFT pattern in the described splicing regions, drain electrode extends to the outside with right second border of described first borderline phase, overlapping region that described drain electrode comprises and described gate metal layer forms and the capacity area that extends to outside, described gate metal layer second border from first border of gate metal layer; The area difference of the overlapping region that drain electrode and gate metal layer form in each splicing regions is less than threshold value;
Above the TFT pattern that forms, form the second function film layer, obtain thin-film transistor array base-plate;
Described thin-film transistor array base-plate and established subtend color membrane substrates are fitted, enter successive process, form Thin Film Transistor-LCD.
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Application publication date: 20101027 |