CN101872648B - MOS (Metal Oxide Semiconductor) one time programmable device - Google Patents
MOS (Metal Oxide Semiconductor) one time programmable device Download PDFInfo
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- CN101872648B CN101872648B CN 200910057116 CN200910057116A CN101872648B CN 101872648 B CN101872648 B CN 101872648B CN 200910057116 CN200910057116 CN 200910057116 CN 200910057116 A CN200910057116 A CN 200910057116A CN 101872648 B CN101872648 B CN 101872648B
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Abstract
The invention discloses an MOS (Metal Oxide Semiconductor) one time programmable device which comprises a coupling capacitor, an NMOS (N-channel Metal Oxide Semiconductor) and a PMOS (P-channel Metal Oxide Semiconductor), wherein one end of the coupling capacitor is connected with an NMOS floating gate polysilicon layer; by utilizing the capacitor coupling voltage, the NMOS is subjected to thermion injection; thermions penetrate a gate oxide potential barrier and then are stored on the floating gate polysilicon layer to finish a programming work; a PMOS gate shares the same polysilicon layer with the NMOS floating gate layer; the primary state threshold voltage of a PMOS drain electrode is negative; the thermions stored on the floating gate polysilicon layer after programming enable a PMOS channel to be inverse, and the threshold voltage is positive; and based on the changes of the current of the PMOS channel before and after programming, 0 and 1 in the sense of a storage unit are distinguished. The MOS (Metal Oxide Semiconductor) one time programmable device can read data by using zero voltage and has very large current difference window before and after programming.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of MOS disposable programmable device.
Background technology
Common MOS disposable programmable device (one-time programmable memory, OTP) structure such as Fig. 1, shown in Figure 2, adding a NMOS by a coupling capacitance consists of, coupling capacitance one end is polysilicon layer, floating gate polysilicon with NMOS joins, during the access programmed circuit, another termination word line (Word Line) of coupling capacitance, the P trap of NMOS, source connects 0 volt, drain terminal connects bit line (Bit Line), during programming, utilize the coupling capacitance high voltage of will programming to be coupled to floating boom, and then utilize channel hot electron (Channel Hot Electron, CHE) be stored on the floating boom after making thermoelectron penetrate the gate oxidation potential barrier, owing to be floating boom, the thermoelectron of these injections can not disappear but be stored in the floating boom, makes the threshold voltage of NMOS that obviously skew occur, thereby can come distinguishing state by the switch of control NMOS, realize programming.
Above-mentioned common MOS disposable programmable device, because programming is same NMOS with what read usefulness, the threshold value before and after the programming just is, and as shown in Figure 3, has contradiction when reading out data:
5 volts of voltages of power supply read in the circuit if utilize, difference between current before and after the programming only has 2 orders of magnitude, for current difference window before and after the storage unit programming increases, need to increase the threshold voltage shift amount, certainly will require like this to increase the coupling capacitance area, with the efficient of raising capacitor coupling voltage, thereby can sacrifice the OTP memory cell area;
If design distinguished is in 2～3V of supply voltage reference voltage, in order to reading out data, the current difference window can increase greatly before and after the storage unit programming, difference between current can reach 8 more than the order of magnitude before and after the programming, but the design for the low capacity application, extra this part circuit that produces reference voltage has too been wasted area.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of MOS disposable programmable device, and this MOS disposable programmable device can fetch data with the zero volt voltage reading, and has very large programming front and back current difference window.
For solving the problems of the technologies described above, MOS disposable programmable device of the present invention, comprise a coupling capacitance and a NMOS, one end of coupling capacitance links to each other with the NMOS floating gate polysilicon layer, utilizing capacitor coupling voltage to make NMOS that thermoelectron occur injects, thermoelectron is stored on the floating gate polysilicon layer after penetrating the gate oxidation potential barrier, finish programing work, it is characterized in that, also comprise a PMOS, described PMOS grid share same polysilicon layer with described NMOS floating boom, described PMOS drain electrode original state threshold voltage is for negative, and the electronics that is stored in after the programming on the floating boom crystal silicon layer makes PMOS raceway groove transoid, and threshold voltage is for just, based on the variation of PMOS channel current before and after the programming, distinguish 0 and 1 on the storage unit meaning.
MOS disposable programmable device of the present invention, basis at common MOS disposable programmable device increases by a PMOS, utilize the NMOS of disposable programmable device to programme, store electrons on the NMOS floating boom, the PMOS grid are shared a polysilicon layer with NMOS floating boom floating boom, electric current before and after PMOS reads programming, the PMOS initial threshold voltage is for negative, threshold voltage is for just after the programming, as shown in Figure 3, can be under 0V voltage reading current, and have current difference window before and after the very optimistic programming, be conducive to circuit design, the extremely needed peripheral voltage change-over circuit of mos gate in the time that reading out data can being saved.
Description of drawings
Fig. 1 is common MOS disposable programmable device circuitry figure;
Fig. 2 is the domain of existing MOS disposable programmable device;
Fig. 3 is electric current-grid voltage curve figure before and after the existing MOS disposable programmable device programming;
Fig. 4 is the circuit theory diagrams of MOS disposable programmable device one embodiment of the present invention;
Fig. 5 is the domain synoptic diagram of MOS disposable programmable device one embodiment of the present invention;
Fig. 6 is the programming front and back electric current-grid voltage curve figure of MOS disposable programmable device one embodiment of the present invention.
Embodiment
MOS disposable programmable device one embodiment of the present invention such as Fig. 4, shown in Figure 5, comprise a coupling capacitance and a NMOS, one end of coupling capacitance links to each other with the NMOS floating gate polysilicon layer, utilizing capacitor coupling voltage to make NMOS that thermoelectron notes (CHE) occur enters, thermoelectron is stored on the floating gate polysilicon layer after penetrating the gate oxidation potential barrier, finish programing work, also comprise a PMOS, described PMOS grid share same polysilicon layer with described NMOS floating boom, described PMOS drain electrode original state threshold voltage is for negative, namely when PMOS gate voltage and source voltage are 0V, raceway groove is not opened (channel current levels off to 0), the electronics that is stored in after the programming on the floating boom crystal silicon layer makes PMOS raceway groove transoid, and threshold voltage is being for just, namely when PMOS gate voltage and source voltage are 0V, raceway groove is opened (channel current approaches to saturation), based on the variation of PMOS channel current before and after the programming, by current detection circuit, distinguish 0 and 1 on the storage unit meaning.
MOS disposable programmable device of the present invention, basis at common MOS disposable programmable device increases by a PMOS, utilize the NMOS of disposable programmable device to programme, store electrons on the NMOS floating boom, the PMOS grid are shared a polysilicon layer with NMOS floating boom floating boom, electric current before and after PMOS reads programming, the PMOS initial threshold voltage is for negative, threshold voltage is for just after the programming, as shown in Figure 6, can be under 0V voltage reading current, and have current difference window before and after the very optimistic programming, be conducive to circuit design, the extremely needed peripheral voltage change-over circuit of mos gate in the time that reading out data can being saved.
MOS disposable programmable device of the present invention can design NMOS and PMOS longitudinal arrangement, shares polysilicon gate, area full symmetric, and coupling capacitance adopts the NMOS gate capacitance, is arranged in NMOS and PMOS side, design coupling capacitance C
Coupling capacitanceArea is much larger than the NMOS/PMOS zone grid oxygen capacity area of described longitudinal arrangement, according to capacitive coupling relation, floating boom voltage V
Floating boomNear coupling capacitance terminal voltage V
The coupling capacitance end, V
Floating boom=V
The coupling capacitance end* C
Coupling capacitance/ (C
Coupling capacitance+ C
Transistor capacitance), better coupling efficiency is 60%～90%, coupling efficiency=C
Coupling capacitance/ (C
Coupling capacitance+ C
Transistor capacitance).The coupling capacitance end adds high voltage when programming, and floating boom voltage is high, satisfies NMOS OTP programming requirement; The coupling capacitance end adds 0V when reading, and floating boom voltage satisfies the condition that PMOS of the present invention reads near 0V.
The read-write mode of MOS disposable programmable device of the present invention, as shown in Figure 5, coupling capacitance termination word line (Word Line), the source of NMOS and P trap ground connection GND, miss line program (PGL Line), the source of PMOS and N trap meet the positive VDD of power supply, miss bit line (Bit Line), its read-write mode is as shown in table 1
Table 1
| Bit | Bit(un) | WL | WL(un) | PGL | PGLL(un) | NW | PW | |
| PGM | VDD | VDD | VPPH | 0 | VPPL | 0 | VDD | GND |
| READ | 0 | VDD | 0 | VDD | 0 | 0 | VDD | GND |
In the table:
Bit：Bit Line
Bit (un): not selected storage unit Bit Line
WL：Word Line
WL (un): not selected storage unit Word Line
PGL：PGL Line
PGL (un): not selected storage unit PGL Line
The NW:N trap
The PW:P trap
PGM: programming
READ: read
VDD: power supply high voltage
VPPH:10～15V word line high voltage
VPPL:5～9V line program high voltage
When this MOS disposable programmable device was programmed, the word line voltage that coupling capacitance connects was high voltage, and it is high voltage that NMOS leaks the line program voltage that connects, and it is high voltage that PMOS leaks the bit-line voltage that connects.
When this MOS disposable programmable device was read, the word line voltage that coupling capacitance connects was low-voltage, and it is low-voltage that NMOS leaks the line program voltage that connects, and it is high voltage that PMOS leaks the bit-line voltage that connects.
Claims (3)
1. MOS disposable programmable device, comprise a coupling capacitance and a NMOS, one end of coupling capacitance links to each other with the NMOS floating gate polysilicon layer, utilizing capacitor coupling voltage to make NMOS that thermoelectron occur injects, thermoelectron is stored on the floating gate polysilicon layer after penetrating the gate oxidation potential barrier, finish programing work, it is characterized in that, also comprise a PMOS, described PMOS grid share same polysilicon layer with described NMOS floating boom, and described PMOS drain electrode original state threshold voltage is for negative, the electronics that is stored in after the programming on the floating boom crystal silicon layer makes PMOS raceway groove transoid, threshold voltage based on the variation of PMOS channel current before and after the programming, is distinguished 0 and 1 on the storage unit meaning for just;
When this MOS disposable programmable device is programmed, the source of described NMOS and P trap ground connection, the source of described PMOS and N trap are just connecing power supply, the word line voltage that described coupling capacitance connects is high voltage, it is high voltage that described NMOS leaks the line program voltage that connects, and it is high voltage that described PMOS leaks the bit-line voltage that connects;
When this MOS disposable programmable device is read, the source of described NMOS and P trap ground connection, the source of described PMOS and N trap are just connecing power supply, the word line voltage that described coupling capacitance connects is low-voltage, it is low-voltage that described NMOS leaks the line program voltage that connects, and it is high voltage that described PMOS leaks the bit-line voltage that connects.
2. MOS disposable programmable device according to claim 1 is characterized in that, described NMOS and PMOS longitudinal arrangement, and the area full symmetric, described coupling capacitance adopts the NMOS gate capacitance, is arranged in described NMOS and PMOS side.
3. MOS disposable programmable device according to claim 2 is characterized in that described coupling capacitance C
Coupling capacitanceNMOS and PMOS grid oxygen capacitor C with described longitudinal arrangement
Transistor capacitanceThe Area Ratio coupling efficiency is 60%～90%, coupling efficiency=C
Coupling capacitance/ (C
Coupling capacitance+ C
Transistor capacitance).
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910057116 CN101872648B (en) | 2009-04-23 | 2009-04-23 | MOS (Metal Oxide Semiconductor) one time programmable device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200910057116 CN101872648B (en) | 2009-04-23 | 2009-04-23 | MOS (Metal Oxide Semiconductor) one time programmable device |
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| Publication Number | Publication Date |
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| CN101872648A CN101872648A (en) | 2010-10-27 |
| CN101872648B true CN101872648B (en) | 2013-04-24 |
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| CN109326603A (en) * | 2017-02-16 | 2019-02-12 | 杰华特微电子（张家港）有限公司 | A kind of single programmable read-only memory based on CMOS technology |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4129936A (en) * | 1976-09-09 | 1978-12-19 | Sakae Takei | Method for manufacturing monolithic semiconductor mask programmable ROM's |
| CN1143814A (en) * | 1995-08-21 | 1997-02-26 | Lg半导体株式会社 | Nonvolatile memory and emthod of programming the same |
| US6229733B1 (en) * | 1999-03-24 | 2001-05-08 | Texas Instruments Incorporated | Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide |
-
2009
- 2009-04-23 CN CN 200910057116 patent/CN101872648B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4129936A (en) * | 1976-09-09 | 1978-12-19 | Sakae Takei | Method for manufacturing monolithic semiconductor mask programmable ROM's |
| CN1143814A (en) * | 1995-08-21 | 1997-02-26 | Lg半导体株式会社 | Nonvolatile memory and emthod of programming the same |
| US6229733B1 (en) * | 1999-03-24 | 2001-05-08 | Texas Instruments Incorporated | Non-volatile memory cell for linear mos integrated circuits utilizing fused mosfet gate oxide |
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| CN101872648A (en) | 2010-10-27 |
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