CN101866847A - Method and device for improving width uniformity of groove - Google Patents
Method and device for improving width uniformity of groove Download PDFInfo
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- CN101866847A CN101866847A CN200910082354A CN200910082354A CN101866847A CN 101866847 A CN101866847 A CN 101866847A CN 200910082354 A CN200910082354 A CN 200910082354A CN 200910082354 A CN200910082354 A CN 200910082354A CN 101866847 A CN101866847 A CN 101866847A
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Abstract
The invention discloses a method for improving the width uniformity of a groove, which is applied to a groove etching process of a wafer in a reaction chamber. A side ring is arranged in the reaction chamber; the side ring is arranged around the wafer; the etching speed of the edge of the chip is controlled by changing the temperature of the side ring. The invention also discloses a device for improving the width uniformity of the groove. The etching speed of the groove of the edge of the wafer can be increased, and the width uniformity of the groove is effectively improved by adopting the method and the device.
Description
Technical field
The present invention relates to process for fabrication of semiconductor device, particularly a kind of method and device that improves width uniformity of groove.
Background technology
At present, in the last part technology of semiconductor device, can the multiple layer metal interconnection layer be set according to different needs, every layer of metal interconnecting layer comprises metal interconnecting wires and insulating barrier, this just need make groove and connecting hole to above-mentioned insulating barrier, plated metal in above-mentioned groove and connecting hole then, the metal of deposition is metal interconnecting wires, generally selects for use copper as metal interconnected wire material.Fig. 1 is in the prior art, the generalized section of part copper interconnection layer: etching groove 103 and connecting hole 104 on the insulating barrier that comprises etch stop layer 101 and silicon oxide layer 102, plated metal copper in groove 103 and connecting hole 104 then, copper interconnecting line 103 ' in the formation groove 103 and the copper interconnecting line 104 ' in the connecting hole 104, described copper interconnecting line 104 ' is connected with the copper interconnecting line 105 of lower floor.For for simplicity, Fig. 1 only shows the part metals interconnection layer.Obviously, be formed on the Semiconductor substrate, also have the number of metal interconnection layer, wherein can form various device architectures on the Semiconductor substrate, for example be defined in active area, isolated area on the substrate, and transistorized source/leakage and the grid in the active area.
In existing etching technics, general using plasma etching forms groove 103 and connecting hole 104.When etching groove 103, the general etching gas that adopts of main etching comprises: argon gas (Ar) and fluorine-containing (F) class gas such as carbon tetrafluoride (CF
4) etc., by the method that physical etchings and chemical etching combine, dielectric layer such as silicon oxide layer 102 are carried out etching.Wherein, Ar is mainly used in physical etchings, and the Ar plasma is known from experience in wafer surface and produced ion bombardment, can be physically removes material and can destroy chemical bond between the wafer surface atom from wafer surface, thereby improve etching reaction speed significantly.Fluorinated gas such as CF
4Be mainly used in chemical etching, produce chemically the easily plasma group of reaction, these groups can obviously increase etch rate.
Etching technics carries out in reaction chamber, in the prior art, the mist of Ar and CF4 is passed through pipeline, and then be divided into two branch roads, and all being provided with pore on every branch road, the mist of Ar and CF4 is by the pore on the branch road separately, feed in the reaction chamber Ar and CF respectively
4Mist (Dual Gas Flow DGF) than can setting the pore quantity ratio on two branch roads according to the difference of practical application, and then adjusts the size of reaction chamber zone line and fringe region in two throughputs of the zone line and the fringe region of reaction chamber.For example, the pore quantity ratio of fringe region and zone line can be adjusted into 1: 2.
Because the radio-frequency power power supply provides radio-frequency voltage, produces rf electric field in reaction chamber, and etching gas is excited into plasma.But because rf electric field inhomogeneous, institute is so that the plasma of generation is inconsistent in the uniformity of the zone line of reaction chamber and fringe region, and therefore, the etch rate of fringe region is less than the etch rate of zone line.
Further, in wafer, there is several chip unit (Die), has several single lines (Iso) and close line (Dense) in each chip unit.To Mi Xianchu, the spacing between grid and the grid reduces gradually from single line.Like this, will make the Iso of Waffer edge and the etching at Dense place lose the etch rate of speed less than other position.Because etching comprises lateral etching and vertical etching, the Waffer edge etch rate is little, what then the lateral etching speed of Waffer edge naturally can be than wafer zone line is little, the groove width of Waffer edge will be littler than the groove width of wafer zone line, therefore, each locational groove width W is inhomogeneous in the wafer, causes the square resistance uniformity of copper interconnecting line 103 ' in the wafer relatively poor, the position upper block resistance (R that promptly has on the wafer
s) bigger, the position upper block resistance that has is less.
Be the width uniformity of groove of shows wafer Iso and Dense, utilize scanning electron microscopy (SEM) to catch the groove width value of Iso and Dense.The range of Dense place groove width is 9.5 nanometers; The range of Iso place groove width is 29.9 nanometers.The width uniformity of groove index range of Iso or Dense is low more, illustrates that then the square resistance uniformity is high more.Range is meant: groove width maximum-groove width minimum value.Be accompanied by the develop rapidly of semiconductor fabrication, wafer is towards higher component density, the high integration direction develops, the manufacturing technology of semiconductor device has entered 65nm and even 45nm process node, the width uniformity of groove index range of control Iso or Dense is in the scope of 10 nanometers, more and more become a technical challenge, this from above-mentioned just as can be seen, though the range at Dense place is 9.5 nanometers, less than 10 nanometers, but the range at Iso place is 29.9 nanometers, much larger than 10 nanometers, this can have a strong impact on the performance of device, more and more becomes the key issue that improves device performance so improve width uniformity of groove.
For the zone line of eliminating reaction chamber and the difference of fringe region etch rate, promptly to improve the etching homogeneity in the entire wafer scope, can transfer the pore quantity of fringe region more still less than adjusting the pore quantity of fringe region and zone line, for example the pore quantity ratio of fringe region and zone line is 1: 4, the fringe region of She Dinging is more by Waffer edge like this, and area is smaller, so under the situation of same traffic, etching gas by the fringe region that sets is just more more relatively, improved the etch rate of fringe region.Change after the DGF ratio, though the uniformity at final Dense place increases, the range at Dense place reduces to 8.7 nanometers from 9.5 nanometers, and the uniformity at Iso place is still very poor, and the range at Iso place is 19.8 nanometers, much larger than 10 nanometers.Still can the performance of semiconductor device be made a big impact.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of method and apparatus that improves width uniformity of groove, and this method and apparatus can effectively improve width uniformity of groove.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
The invention discloses a kind of method that improves width uniformity of groove, be applied to be provided with side ring in the described reaction chamber in the etching groove operation of wafer in reaction chamber, described side ring is around the wafer setting, key is, by the temperature that changes side ring the etch rate of Waffer edge is controlled.
The temperature that reduces described side ring is at 20 degrees centigrade to 35 degrees centigrade.
The reduction of the temperature of described side ring is by the flow of cooling material in the control side ring chamber.
Described cooling material is cooling water, helium or nitrogen.
The invention also discloses a kind of device that improves width uniformity of groove, comprise the reaction chamber that is used for wafer etching groove operation, be provided with side ring in the described reaction chamber, described side ring is around the wafer setting, and key is that this device also comprises cooling control system, described cooling control system is located at outside the reaction chamber, be connected with side ring, be used to change the temperature of side ring, the etch rate of Waffer edge is controlled.
Described cooling control system reduces the temperature of side ring between 20 degrees centigrade to 35 degrees centigrade.
Described side ring is a toroidal cavity, is used to feed cooling material.
Described cooling control system comprises controllable valve, master controller, temperature sensor;
Temperature sensor detects difference side ring temperature constantly according to sample frequency;
Master controller is according to the temperature control flows of the temperature sensor flow through the cooling material of controllable valve;
Controllable valve is connected with side ring, and the cooling material controllable valve of flowing through enters side ring.
Described side ring is a conducting ring.
Described side ring is a kind of in quartz ring, silicon ring, carborundum ring, silicon nitride ring, aluminium nitride ring, the aluminium oxide ring.
As seen from the above technical solutions, the present invention is by reducing the temperature of side ring, be reduced in the consumption of Waffer edge side ring to fluoro-gas, the etching that just fluorine-containing etching gas more effectively can be used for groove, increased etch rate thus to the Waffer edge groove, thereby improve the uniformity of groove width, also promptly improved the uniformity of the square resistance of the metallic copper of filling in the groove, finally improved the performance of semiconductor device.
Description of drawings
Fig. 1 is the generalized section of part copper interconnection layer in the prior art.
Fig. 2 is the interior cut-away section schematic diagram of reaction chamber of prior art ionic medium processing unit.
Fig. 3 improves the schematic flow sheet of wafer width uniformity of groove for the present invention.
Fig. 4 improves the device schematic diagram of the preferred embodiment of wafer width uniformity of groove for the present invention.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
The present invention is by reducing the temperature of side ring, be reduced in the consumption of Waffer edge side ring to fluoro-gas, the etching that just fluorine-containing etching gas more effectively can be used for groove, increased etch rate thus to the Waffer edge groove, thereby improve the uniformity of groove width, also promptly improve the uniformity of the square resistance of the metallic copper of filling in the groove, finally improved the performance of device.
The present invention utilizes schematic diagram to describe in detail, when the embodiment of the invention is described in detail in detail, for convenience of explanation, the schematic diagram of expression structure can be disobeyed general ratio and be done local the amplification, should be with this as limitation of the invention, in addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
Fig. 2 is the interior cut-away section schematic diagram of reaction chamber of prior art ionic medium processing unit.The bottom electrode sub-assembly comprises a substrate 201 and position wafer chuck 202 thereon, and wafer 203 is contained on the wafer chuck 202, so that the part upper surface of cover wafers chuck 202 and side ring 204, that is to say that each several part is closely to mate.Wherein, can also be provided with (not shown)s such as coupling loop, insulator ring type filling on the substrate 201.Side ring 204 is electric conducting materials of heating in the process that plasma produces, is generally entity structure, can also protect wafer chuck 202 to avoid ion bombardment during etching processing.Side ring can adopt arbitrary shape, in order to provide more uniform temperature to the plasma in the reaction chamber, is preferably the ring-type that is provided with around wafer 203.Its cross section can also have projection, the upper surface flush of convex upper surface and wafer chuck 202, the projection of wafer 203 cover wafers chucks 202 and side ring 204 for rectangle or the madial wall along side ring as shown in Figure 2.In specific embodiment, side ring 204 can not have overlapping with wafer 203 yet.
Generally the material as side ring includes but not limited to silicon, silicon nitride, carborundum, aluminium nitride, aluminium oxide and quartz.Because side ring directly is exposed in the plasma,, can elect monocrystalline silicon, polysilicon and chemical vapour deposition (CVD) (Chemical Vapor Deposion, CVD) high-purity material of carborundum etc. as in order to make the minimum contamination of plasma.In the present embodiment, the material of side ring 204 is quartzy, in etching process, can be depleted, so need periodic replacement, the different frequencies of changing of degree according to plasma etching can be different, hour replacing of general per 200 radio frequencies (RF) once referred to the time that plasma is handled here in RF hour.This be because quartzy in etching process can with fluorine-containing etching gas CF for example
4, CH
2F
2Deng reaction, form volatile compound.
Because the concentration of the fluorochemical on wafer 203 edges can be by side ring 204 cancellations, therefore can make fluorochemical not carry out etching to Waffer edge effectively, among the present invention the side ring temperature is reduced, by reducing the temperature of side ring, be reduced in the consumption of 204 pairs of fluoro-gas of Waffer edge side ring, just fluorine-containing etching gas more effectively can be used for the etching of the groove at wafer 203 edges.The present invention improves the schematic flow sheet of wafer width uniformity of groove, as shown in Figure 3:
The temperature of step 301, reduction side ring, scope is between 20 degrees centigrade to 35 degrees centigrade;
Step 302, under described side ring temperature, carry out etching procedure and form groove.
In order to reduce the temperature of side ring, in the embodiment of the invention, side ring 204 is set to a toroidal cavity, be used in the side ring chamber, feeding cooling material, to reach the purpose that reduces the side ring temperature.And, be provided with projection along the madial wall in chamber, the upper surface flush of convex upper surface and wafer chuck 202, the projection of wafer 203 cover wafers chucks 202 and side ring 204, like this side ring 204 can be more directly to the edge generation effect of wafer 203.
The temperature of general side ring 204 is heated in plasma etch process at 40 to 50 degrees centigrade, and is roughly the same with the temperature of wafer, and the temperature of side ring can't be regulated as required.The present invention reduces to 20 degrees centigrade to 35 degrees centigrade with the side ring temperature.The side ring temperature controlling can be by adding cooling water in the side ring chamber, perhaps refrigerating gas such as helium and nitrogen reaches the purpose that reduces the side ring temperature, as long as can reach the effect that reduces the side ring temperature, any cooling material can be used for adding in the side ring chamber.Preferably, outside reaction chamber, be connected a cooling controller 400 with side ring 204, described cooling controller, comprise temperature sensor 401, master controller 402 and controllable valve 403, be used for the flow that control flexibly enters the cooling material in side ring chamber, to reach desirable side ring temperature.Temperature sensor 401 is connected with side ring 204, according to sample frequency difference side ring temperature is constantly detected; Master controller 402 is according to the temperature control flows of the temperature sensor flow through the cooling material of controllable valve 403; Controllable valve 403 is connected with side ring 204, and the cooling material controllable valve 403 of flowing through enters side ring 204.When temperature sensor 401 detected the side ring temperature and reaches 20 degrees centigrade of arbitrary needed temperature between 35 degrees centigrade, control finished.In sum, the device that the present invention improves the wafer width uniformity of groove comprises reaction chamber that is used for wafer etching groove operation and the cooling controller 400 that the side ring 204 that is provided with in the reaction chamber is cooled off control, the present invention improve the wafer width uniformity of groove preferred embodiment the device schematic diagram as shown in Figure 4, side ring 204 only is shown in the reaction chamber among the figure.
Side ring is made as a cavity that can feed cooling material, being used for reducing the temperature of side ring, is a preferred embodiment of the present invention, and the present invention is not limited to this, as long as can reduce any feasibility operating means of the temperature of side ring, can be used for realizing purpose of the present invention.
Reduction just because of the side ring temperature, improved the etch rate at wafer 203 edges, the etch rate at Waffer edge Iso and Dense place all has raising so, because Waffer edge Iso place is relatively more responsive to the reduction of temperature, so raising of Waffer edge Iso place etch rate, apparent in view than the Dense place, so after reducing the side ring temperature, Iso place at wafer, width uniformity of groove index range value significantly reduces, reduce to 8.8 nanometers by 29.9 original nanometers, this explanation the present invention can improve the width uniformity of groove at wafer Iso place, i.e. R greatly
sUniformity.Though the present invention makes the range at wafer Dense place that small rising be arranged, rise to 9.7 nanometers from original 9.5 nanometers, but still in the scope of 10 nanometers, so the width uniformity of groove index range that has finally reached wafer Iso and Dense place is controlled in the scope of 10 nanometers, improved width uniformity of groove effectively, thereby improved the uniformity of the square resistance of the metallic copper of filling in the groove, improved the performance of device.
If the material of side ring is the silicon close with backing material, comprise monocrystalline silicon or polysilicon, so because the difference of material, consumption to fluorine-containing etching gas is also different, for example monocrystalline silicon is just much smaller than quartz to the consumption of fluorine-containing etching gas, so when adjusting the temperature that reduces side ring 204, will reduce to the temperature of side ring 204 lower, just can reach the etching that makes fluorine-containing etching gas more effectively be used for the groove at wafer 203 edges, so the reduction of side ring temperature is different according to specifically using.
It should be appreciated by those skilled in the art, the cited wafer Iso and the groove width value at Dense place among the present invention, it is specific embodiment wherein, be not limited to the concrete numerical value shown in the foregoing description, during each enforcement because the influence of environment or other factors, its numerical value all can have small variation, but overall trend is constant.Adopt lower side ring temperature to improve width uniformity of groove, also be not limited to the concrete situation in the foregoing description, can adjust according to different process conditions, those skilled in the art obviously can carry out suitable modifications and variations not breaking away from the spirit or scope of the present invention.
Claims (10)
1. method that improves width uniformity of groove, be applied to be provided with side ring in the described reaction chamber in the etching groove operation of wafer in reaction chamber, described side ring is around the wafer setting, it is characterized in that, the etch rate of Waffer edge is controlled by the temperature that changes side ring.
2. the method for claim 1 is characterized in that, the temperature that reduces described side ring is at 20 degrees centigrade to 35 degrees centigrade.
3. method as claimed in claim 2 is characterized in that, the reduction of the temperature of described side ring is by the flow of cooling material in the control side ring chamber.
4. method as claimed in claim 3 is characterized in that, described cooling material is cooling water, helium or nitrogen.
5. device that improves width uniformity of groove, comprise the reaction chamber that is used for wafer etching groove operation, be provided with side ring in the described reaction chamber, described side ring is characterized in that around the wafer setting this device also comprises cooling control system, described cooling control system is located at outside the reaction chamber, be connected with side ring, be used to change the temperature of side ring, the etch rate of Waffer edge is controlled.
6. device as claimed in claim 5 is characterized in that, described cooling control system reduces the temperature of side ring between 20 degrees centigrade to 35 degrees centigrade.
7. device as claimed in claim 6 is characterized in that described side ring is a toroidal cavity, is used to feed cooling material.
8. device as claimed in claim 6 is characterized in that described cooling control system comprises controllable valve, master controller, temperature sensor;
Temperature sensor detects difference side ring temperature constantly according to sample frequency;
Master controller is according to the temperature control flows of the temperature sensor flow through the cooling material of controllable valve;
Controllable valve is connected with side ring, and the cooling material controllable valve of flowing through enters side ring.
9. as claim 7 or 8 described devices, it is characterized in that described side ring is a conducting ring.
10. as claim 7 or 8 described devices, it is characterized in that described side ring is a kind of in quartz ring, silicon ring, carborundum ring, silicon nitride ring, aluminium nitride ring, the aluminium oxide ring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910082354A CN101866847A (en) | 2009-04-14 | 2009-04-14 | Method and device for improving width uniformity of groove |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910082354A CN101866847A (en) | 2009-04-14 | 2009-04-14 | Method and device for improving width uniformity of groove |
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| CN101866847A true CN101866847A (en) | 2010-10-20 |
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| CN200910082354A Pending CN101866847A (en) | 2009-04-14 | 2009-04-14 | Method and device for improving width uniformity of groove |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102368467A (en) * | 2011-11-24 | 2012-03-07 | 上海宏力半导体制造有限公司 | Plasma processing apparatus and protection ring thereof |
| CN103928290A (en) * | 2013-01-11 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Etching method of wafer edge |
-
2009
- 2009-04-14 CN CN200910082354A patent/CN101866847A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102368467A (en) * | 2011-11-24 | 2012-03-07 | 上海宏力半导体制造有限公司 | Plasma processing apparatus and protection ring thereof |
| CN103928290A (en) * | 2013-01-11 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Etching method of wafer edge |
| CN103928290B (en) * | 2013-01-11 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | The lithographic method of crystal round fringes |
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Open date: 20101020 |